CN103220549B - Video generator and system - Google Patents
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- CN103220549B CN103220549B CN201310181878.5A CN201310181878A CN103220549B CN 103220549 B CN103220549 B CN 103220549B CN 201310181878 A CN201310181878 A CN 201310181878A CN 103220549 B CN103220549 B CN 103220549B
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Abstract
The invention discloses a video generator and a system. The video generator comprises a format conversion sub-module, a caching tank, a co-scheduling module, multilevel control indicators, caching windows, a clock lock and a broadcast control output module. The format conversion sub-module is used for converting the format of an input video and outputting the converted video to the caching tank; the caching tank is used for caching code stream data, allocating a specified quantity of multilevel control indicators for a code stream and opening up one caching window for each level of control indicator, wherein output of the caching window is connected with the broadcast control output module; the broadcast control output module is used for outputting a homologous asynchronous code stream; the output of the clock lock is connected with the broadcast control output module and is used for setting a system clock period through the code stream frame rate of the broadcast control output module and controlling the output-input operation of the system; and the co-scheduling module is used for controlling the format conversion sub-module, the multilevel control indicators and the clock lock and feeding back the states of the caching tank and the caching window to the co-scheduling module. The video generator and the system can be used for improving the accuracy and the objectivity of subjective testing of a video encoder and enhancing the testing efficiency.
Description
Technical field
The present invention relates to digital video decoding technical field, particularly relate to a kind of video generator and system.
Background technology
In conventional Multi Media Video Applications, conventional video resolution is for there being CIF(352*288) and 4CIF(704*576) etc., wherein 4CIF is the most hi-vision standard of SD video conference.The concept of " HD video " (High Definition Television Video) is proposed by professional radio, TV and film industries, and the form of the digital TV in high resolution of the highest ranking that American film Television Engineer association (SMPTE) formulates is: 1920 × 1080.In fact, the video resolution that HD digital TV (HDTV) field specifies mainly contains three kinds of forms, i.e. 720P, 1080I, (wherein " P " is progressive scan mode to 1080P, " I " is interlace mode), aspect ratio is 16:9, meet above condition and just can be referred to as HD video, high-definition digital video promotes one of current multimedia technology development major impetus, wherein, the digital video decoding technology of one of the most crucial technology of HD video reduces video data rate under the prerequisite ensureing visual effect as far as possible, be widely used in multimedia communication, radio and television, consumer electronics, the fields such as computer application.Since nineteen nineties, be that the source coding standard of representative through developing 10 years more with MPEG-2, new coding techniques emerges in an endless stream, the high-definition message source coding standard that current audio frequency and video industry can be selected has four: MPEG-2, MPEG-4, MPEG-4AVC(are called for short AVC, also claims JVT, H.264), AVS.Divide from enactor, first three standard is completed by MPEG expert group, and the 4th is the autonomous formulation of China.Divide from developing stage, MPEG-2 is first generation information source standard, and its excess-three is second generation standard.Compare from the key technical indexes-code efficiency: MPEG-4 is 1.4 times of MPEG-2, AVS and AVC is suitable, is all more than MPEG-2 twice.
Along with the demand of market to high definition product presented the trend of blowout in recent years, high-definition video equipment is also popularized fast, the performance of its core HD video encoder have also been obtained very large development, the performance of how to evaluate encoder, particularly high definition encoder is the study hotspot of image quality evaluation technology always.Image quality evaluation is the Combine distortion intensity of measurement one sub-picture, and quantization means is a single score value.Mainly be divided into subjective evaluation method and method for objectively evaluating, the subjective evaluation method of picture quality allows several observer watch a series of test pattern according to the interpretational criteria provided, and the quality of watched image is marked, then difference inspection is carried out in the scoring provided all observers, weighted average tries to achieve a score value (MOS, Mean Opinion Score), acquired results is the picture quality of this subjective assessment.Wherein, interpretational criteria comprises: the selection of the testee of non-expert type, the regulation of the controlled factordisease (selection of observed range, ambient lighting, cycle tests, the displaying time interval etc. of sequence) in test environment.Due to the final receiving terminal that people is all multimedia messagess, image finally must be undertaken analyzing, identify, understand and evaluating by people, therefore the accuracy that human subject evaluates is the highest, and the image data base of subjective assessment also just becomes the standard weighing objective evaluation model quality.
In more than ten years in the past, International Telecommunication Association's Radiocommunication Sector (ITU-R) tailor CCIR500-1 recommendation " subjective evaluation method of quality of TV image ", makes stipulations to the method for subjective assessment and standard.CCIR500-1 adopts Pyatyi evaluation quality yardstick and hinders yardstick.Table 1 is depicted as the image quality evaluation Pyatyi standard that CCIR500-1 recommends.
Table 1 Pyatyi yardstick grading evaluation mark
Conventional subjective evaluation method comprises absolute and relative two kinds.Absolute method refers to according to prespecified opinion scale or the experience of oneself, proposes Quality estimation to being evaluated image.Such as: DSIS (Double-Stimulus Impairment Scale), SSCQE (Single-StimulusContinuous Quality Evaluation) etc.Relative manner commonly uses the preferential yardstick of so-called group, is namely classified to bad by good by a collection of image by observer, compares mutually draw quality and provide corresponding mark image.As DSCQS (Double-Stimulus Continuous QualityScale) etc.The method of two stimulation DSIS directly tests human visual sensitivity because of it, and theory can obtain the proper distinguishable minimum of observer, can reach best measuring accuracy.
Video encoder adopts core algorithm to be inter prediction, the main purpose of inter prediction removes the sequential redundancy in video sequence, existing Encoder Optimization improves precision and the speed of prediction mostly, because it is to the of paramount importance link of performance impact in mixed video coding framework, also be that complexity is the highest, affect the principal element of code efficiency, large data particularly for HD video calculate, different coding device can cause different coding efficiency due to optimized algorithm, not only variant in picture quality, also greatly different on coding delay, how objective and accurate evaluation high definition is not all solved always well.The existing patent of invention evaluated about encoder, be mostly the evaluation and test of actual output bit rate for encoder and target bit rate, the subjectivity that well can not realize video encoder is tested and assessed.
Summary of the invention
The technical problem that the present invention solves is: test, the evaluation that how can well realize video encoder performance, the performance particularly for multiple stage encoder carries out contrast test.
The technical solution adopted for the present invention to solve the technical problems: a kind of video generator, comprises format conversion submodule, cache pool, cooperative scheduling module, Multistage Control pointer, buffer memory window, clock lock, Broadcast Control output module;
Described format conversion submodule is used for changing input video form, and by the video frequency output after conversion to cache pool;
Described cache pool is used for the buffer memory of bit stream data, is the Multistage Control pointer of Bit allocation specified quantity, and opens up a buffering window for every grade of steering needle in cache pool, and buffer memory window exports and connects Broadcast Control output module;
Described Broadcast Control output module is for exporting the asynchronous code stream of homology;
Described clock lock exports and connects Broadcast Control output module, for the code stream frame rate initialization system clock cycle by Broadcast Control output module, and the input-output operation of control system;
Described cooperative scheduling module is used for control format transform subblock, Multistage Control pointer and clock lock, and the state feedback of cache pool and buffer memory window inputs to cooperative scheduling module.
Further, as preferably, described cooperative scheduling module can independently control the code stream that Broadcast Control output module exports, and realizes playing, suspends, advances, retreats.
The invention also discloses a kind of video generation systems, comprise video generator, source code flow monitor, at least 1 Video Codec and at least 1 distortion monitor, the test code streams that described video generator exports connects the input of source code flow monitor without a road of time delay, one tunnel of time delay connects Video Codec input, test code streams after Video Codec encoding and decoding connects the input of distortion code stream monitor, source code flow monitor and distortion code stream monitor output feedack input, for adjusting time delay to video generator.
Further, as preferably, also comprise time counter and image capture device, described time counter is for calculating monitor time delay, and image capture device catches the time counter numerical value of monitor, calculates delay time.
Beneficial effect of the present invention:
The present invention can reduce same test source to the difference of different coding device in Image Coding time delay, well realizes the performance test of video encoder, subjective quality assessment, and the coding efficiency particularly for multiple stage high definition encoder carries out contrast test.
Accompanying drawing explanation
When considered in conjunction with the accompanying drawings, by referring to detailed description below, more completely can understand the present invention better and easily learn wherein many adjoint advantages, but accompanying drawing described herein is used to provide a further understanding of the present invention, form a part of the present invention, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention, wherein:
Fig. 1 is video generator example structure schematic diagram of the present invention.
Fig. 2 is video generation systems example structure schematic diagram of the present invention.
Fig. 3 is the workflow schematic diagram of video generator of the present invention.
Fig. 4 is format conversion sub modular structure schematic diagram.
Fig. 5 is cache pool structural representation.
Fig. 6 is cooperative scheduling module work flow chart.
Fig. 7 is clock lock construction schematic diagram.
Embodiment
Be described with reference to Fig. 1-7 pairs of embodiments of the invention.
For enabling above-mentioned purpose, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
As shown in Figure 1, a kind of video generator, comprises format conversion submodule 1, cache pool 3, cooperative scheduling module 2, Multistage Control pointer 4, buffer memory window 5, clock lock 6, Broadcast Control output module 7;
Described format conversion submodule 1 for changing input video form, and by conversion after video frequency output to cache pool 3;
Described cache pool 3, for the buffer memory of bit stream data, is the Multistage Control pointer 4 of Bit allocation specified quantity, and opens up a buffering window 5 for every grade of steering needle in cache pool 3, and buffer memory window 5 exports and connects Broadcast Control output module 7;
Broadcast Control output module 7 is for exporting source code flow and encoder code stream;
Described clock lock 6 exports and connects Broadcast Control output module 7, for providing clock;
Coordinated scheduling module 2 is for control format transform subblock, Multistage Control pointer 4 and clock lock 6, and the stateful connection of cache pool 3 and buffer memory window 5 inputs to coordinated scheduling module 2.
The video generator each several part that the present invention proposes is described below:
(1) for the format conversion of studio equipment adaptive identifying.Complete chrominance space to select and generate fast, complete the YUV422 form that original cycle tests is encoder standard by YUV420 format conversion.Taking of system resource can be improved with less calculation cost, reduce the complexity of video code conversion.
(2) for cache pool that large data system is handled up.First, according to the Installed System Memory amount of capacity setting data buffer memory degree of depth; Then, load cycle tests image and enter system cache pond; Finally, for the cycle tests in cache pool distributes steering needle in units of frame.Can resolution system I/O to the bottleneck of handling up of large-scale data, particularly improve fluency that HD video plays and increase Multistage Control to HD video.
(3) cooperative scheduling for the asynchronous output of same source data manages.The asynchronous output of same source data and cache pool data syn-chronization are loaded.First video data is sent according to Multistage Control pointer; Then according to buffer memory degree of depth holding position state load read-write thread Handshake Protocol; Finally start synchronous read-write scheduler program and load video sequence.Particularly can increase the load capability of the data of system, improve running efficiency of system, extend high definition sequence reproduction time.
(4) for controlling the independence of asynchronous output data.The multi-channel test video exported independently is controlled.First at the interpolation buffer window of cache pool to every grade of steering needle, pointer can move freely in buffer window; Subsequently the test video frame pointed by pointer is exported in real time.Particularly can increase the control to HD video, improve the availability of system.
(5) for ensureing the clock lock of Broadcast Control card smooth playing.System data and Broadcast Control card data clock are locked it.First in control program and Broadcast Control card playing program, add video and load agreement; Cache pool clearance spaces amendment buffer memory degree of depth holding position state is calculated subsequently according to Broadcast Control card play frame rate.The fluency that HD video is play can be ensured, improve the reliability and stability of system cloud gray model.For the high definition YUV sequence image of 1080P, for YUYV422 layout sequence, one frame standard YUYV422 image size is 4050KB ≈ 3.96MB, if frame per second is 30fps, desired data amount is 118.65MB/s, play according to four roads simultaneously, need 474.6MB/s data bandwidth, current internal memory, CPU, the speed of PCI-E × 16 bus is all more than 1GB/s, and the theoretical velocity of SATA hard disc design is 150MB/s, cut bandwidth shared by overhead, actual available data bandwidth is about 80 ~ 110MB/s, therefore, the bottleneck that 1080P high definition sequence is play in real time is that the low speed of SATA hard disc reads, the present invention adopts the design solution hard disk reading Data bottlenecks increasing and play buffer memory and loop-around data chained list.Source code flow is converted to through format conversion submodule the reference format code stream that encoder can input, cache pool is entered after the acquisition buffer memory degree of depth, cooperative scheduling module is data allocations Multistage Control pointer in cache pool after acquisition cache pool state, open up buffer memory window for every grade of steering needle and state returned cooperative scheduling module simultaneously, cooperative scheduling module starts clock lock and exports bit stream data in buffering window to monitor and encoder by Broadcast Control card is asynchronous.Meanwhile, cooperative scheduling module carries out output control according to the control command received to the data in buffering window.Fig. 3 is video generator workflow diagram.
As shown in Figure 2, a kind of video generation systems, comprise video generator 100, first code stream monitor 12, second code flow monitor 13, third yard flow monitor 14, the 4th code stream monitor 15, described video generator code stream exports the asynchronous test code streams of homology and inputs at a road output connection first code stream monitor 12 of moment t, and test code streams is at moment t-T
1, t-T
2and t-T
3output connects second code flow monitor 13, third yard flow monitor 14, the 4th code stream monitor 15 input.First code stream monitor 12, second code flow monitor 13, third yard flow monitor 14, the 4th code stream monitor 15 output can feed back to video generator 100 and input, for adjusting time delay.Because video encoder all has larger time delay, the time delay of different coding device is also different, in order to ensure the synchronism output of cycle tests in subjective testing, needs video generator to provide calibration function to encoder time delay, and provides test Play Control function.Video generator produces and is used for the discernible test code streams of video encoder, and give the monitor of multiple encoder and source code flow in t, test code streams produces time delay T respectively after encoder coding and decoding
1, T
2and T
3, decoded code stream is sent into monitor, and the time difference of the coding and decoding time delay that monitor shows is fed back to video generator, recalibrates the time delay of every road output code flow, the output after calibration is respectively t, t-T
1, t-T
2, t-T
3, like this in test code streams after each encoder, can time t synchronously enter monitor display.
Below the modules in video generator embodiment is described in further detail.
The maximum support resolution of video encoder is that the YUV sequence of 1920*1080 is as initial data, and common yuv format has YUY2, YUYV, YVYU, UYVY, AYUV, Y41P, Y411, Y211, IF09, IYUV, YV12, YVU9, YUV411, YUV420 etc., video generator needs to provide different-format sequence to be measured, and ensure that cycle tests is the image sequence of equal in quality, therefore video generator has same content, the conversion of same quality test Format Series Lines, systematic function.Format conversion submodule mainly completes following functions: call in local source code flow file and resolution parameter, calculate source code flow and the space shared by the every frame of target code stream, for object code flow assignment memory space and recording status signal, return state comprises success state and error state; The each component structure of YUV of source code flow is redistributed, if Fig. 4 is YUV422 form from YUV420 format conversion according to object code stream format; The object code flow index converted is returned and records transition status and also comprise ok state and error state.
Reference Fig. 5, Fig. 5 are cache pool structural representation.First be configured to cache pool according to system resource and distribute the buffer memory degree of depth, target code stream order after transcoding is loaded into buffer memory deep space, it is the grading control pointer of Bit allocation specified quantity in buffer memory deep space, and open up a buffering window for every grade of pointer, in buffering window, pointer is free to advance, rollback, when in Buffer Pool, the lowest address of the buffering window of first order pointer P1 is greater than the lowest address P0 of Buffer Pool, namely during & (P1-w/2) > & P0, the address space of & (P1-w/2) to & P0 is discharged, state information is sent to cooperative scheduling unit starting Buffer Pool data syn-chronization read-write program simultaneously.Such as, the present invention can realize by circular linked list the continuous renewal that 1080P HD video played data and hard disk read data, make to play bandwidth and differ 8.65MB/s with hard disk available data bandwidth, realize one minute Continuous Play needs buffer memory 8.65 × 60=519MB.The present invention adopts the buffer memory of 16GB, can Continuous Play about 30 minutes, can meet the requirement of video generator for encoder subjective testing.
Reference Fig. 6, Fig. 6 are cooperative scheduling management algorithm flow chart.For evading the bottleneck that data are transmitted, the present invention enables reading and writing, control, broadcasting four threads, and except control thread, other three threads need four pointers in simultaneous operation buffering window, if Co-scheduling performance is not good, the situation such as deadlock, RAM leakage that there will be causes system crash.By using mutual exclusion lock in reading and writing thread, ensure that the validity that data are once transmitted, adding Handshake Protocol at broadcasting thread simultaneously, ensureing the consistency of thread collaborative work, solve the real-time collaborative scheduling of the multiple task flow of big data quantity.Specific works flow process is as follows: first cooperative scheduling unit is according to the code stream after cache pool state load transcoding, then be loaded in Broadcast Control card output state by steering needle to video data in buffer memory window, call clock lock program in loading simultaneously, while output, cooperative scheduling program produces prime FIFO and reads enable signal and rear class FIFO storage enable signal, and Synchronization Control cache pool Data import and Broadcast Control card output state data discharge; When needs carry out grading control operation, cooperative scheduling program sends interrupts forward and backward level FIFO enable signal state, cache pool Data import and Broadcast Control card output state data are stopped to discharge, according to operational order, the grading control pointer in buffer memory window is adjusted, subsequently buffering window data to be loaded and Broadcast Control card output state data discharge, complete the independent Broadcast Control of multi-channel video.
Reference Fig. 7, Fig. 7 are clock lock schematic diagram.Wherein, CLK is the every frame time calculated by video frame rate fs: t=1/fs, the present invention it can be used as a system clock cycle, within the clock cycle of same system, cooperative scheduling program reads enable signal to prime FIFO and rear class FIFO storage enable signal carries out mutual exclusion setting, ensure in a system clock cycle, it is each once that system can complete read-write operation, thus ensure the fluency of video playback.
Although the foregoing describe the specific embodiment of the present invention, but those skilled in the art is to be understood that, these embodiments only illustrate, those skilled in the art, when not departing from principle of the present invention and essence, can carry out various omission, replacement and change to the details of said method and system.Such as, merge said method step, thus then belong to scope of the present invention according to the function that the method that essence is identical performs essence identical to realize the identical result of essence.Therefore, scope of the present invention is only defined by the appended claims.
Claims (4)
1. a video generator, is characterized in that, comprises format conversion submodule, cache pool, cooperative scheduling module, Multistage Control pointer, buffer memory window, clock lock, Broadcast Control output module;
Described format conversion submodule is used for changing input video form, completes the YUV422 form that original cycle tests is encoder standard by YUV420 format conversion, and by the video frequency output after conversion to cache pool;
Described cache pool is used for the buffer memory of bit stream data, is the Multistage Control pointer of Bit allocation specified quantity, and opens up a buffer memory window for every grade of steering needle in cache pool, and buffer memory window exports and connects Broadcast Control output module;
Described Broadcast Control output module is for exporting the asynchronous code stream of homology;
Described clock lock exports and connects Broadcast Control output module, for calculating cache pool clearance spaces amendment buffer memory degree of depth holding position state according to Broadcast Control card play frame rate, by the code stream frame rate initialization system clock cycle of Broadcast Control output module, and the input-output operation of control system;
Described cooperative scheduling module is by using mutual exclusion lock in reading and writing thread, and for control format transform subblock, Multistage Control pointer and clock lock, the state feedback of cache pool and buffer memory window inputs to cooperative scheduling module.
2. a kind of video generator as claimed in claim 1, it is characterized in that, described cooperative scheduling module can independently control the code stream that Broadcast Control output module exports, and realizes playing, suspends, advances, retreats.
3. a video generation systems, it is characterized in that, comprise the video generator described in claim 1 or 2, source code flow monitor, at least 1 Video Codec and at least 1 distortion monitor, the test code streams that described video generator exports connects the input of source code flow monitor without a road of time delay, one tunnel of time delay connects Video Codec input, test code streams after Video Codec encoding and decoding connects the input of distortion code stream monitor, source code flow monitor and distortion code stream monitor output feedack input, for adjusting time delay to video generator.
4. a kind of video generation systems as claimed in claim 3, it is characterized in that, also comprise time counter and image capture device, described time counter is for calculating monitor time delay, image capture device catches the time counter numerical value of monitor, calculates delay time.
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| JP2005341132A (en) * | 2004-05-26 | 2005-12-08 | Toshiba Corp | Video data processor and processing method |
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Inventor after: Gao Wen Inventor after: Qi Feng Inventor after: Jiang Tingting Inventor after: Ma Siwei Inventor after: Jia Huizhu Inventor after: Zhao Debin Inventor before: Gao Wen Inventor before: Qi Feng Inventor before: Jiang Tingting Inventor before: Ma Siwei Inventor before: Jia Huizhu Inventor before: Zhao Debin |