CN103220273A - Method and system for central processing unit (CPU) to forward message rapidly - Google Patents
Method and system for central processing unit (CPU) to forward message rapidly Download PDFInfo
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- CN103220273A CN103220273A CN2013100880577A CN201310088057A CN103220273A CN 103220273 A CN103220273 A CN 103220273A CN 2013100880577 A CN2013100880577 A CN 2013100880577A CN 201310088057 A CN201310088057 A CN 201310088057A CN 103220273 A CN103220273 A CN 103220273A
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Abstract
The invention provides a method and a system for a central processing unit (CPU) to forward a message rapidly. The method comprises the steps: S1: the message is sent to a first firewall by a test unit; S2: the message is encrypted by a first encryption and decryption chip in the first firewall according to a preset internet protocol security (IPSEC) encryption key of the message and the encrypted message is sent to a second firewall; and S3: the encrypted message is decrypted by a second encryption and decryption chip in the second firewall according to a preset IPSEC decryption key of the message and the decrypted message is sent to the test unit. According to the method and the system for the CPU to forward the message rapidly, the speed of the CPU in forwarding the message is higher than the speed of the encryption and decryption chips in processing the message.
Description
Technical field
The present invention relates to technical field of the computer network, the method and system that particularly a kind of CPU E-Packets fast.
Background technology
In multi-core network device, as the fire compartment wall network equipment, usually adopt 8 nuclear CPU, 16 nuclear CPU and 32 these three models of nuclear CPU are as low mid-to high-end product, per 4 CPU are encapsulated on the chip, and each chip attaches a hardware encipher decrypting device, just with respect to the network equipment at low mid-to high-end product respectively by 2,4,8 hardware encipher decrypting device, when using each CPU to handle message by stream, owing to use CPU by the stream method, the message of identical IP five-tuple will be distributed on the same CPU, therefore will be super busy owing to single forwarding CPU occurring, and for ESP(Encapsulate Security Payload, secure package load)/AH(Authenticaton Header, authentication header) message, CPU is busy with flowing searching of coupling and tlv triple, has just formed deciphering chip this moment and has transmitted the performance bottleneck that CPU carries out, and it is slow that CPU processing forward message is handled message than deciphering chip.
Summary of the invention
(1) technical problem of Xie Jueing
The technical problem that the present invention solves is to solve CPU to E-Packet and be lower than the speed that deciphering chip is handled message.
(2) technical scheme
The invention provides the method that a kind of CPU E-Packets fast, described method comprises:
S1: test cell sends message to first fire compartment wall;
S2: first deciphering chip in described first fire compartment wall is encrypted described message according to the default IPSEC encryption key of described message, and will encrypt message and send to second fire compartment wall;
S3: second deciphering chip in described second fire compartment wall is decrypted described encryption message according to the default IPSEC decruption key of described message, and decrypted message is sent to described test cell.
Preferably, step S2 specifically comprises:
S21: the CPU0 in first fire compartment wall sends to described first deciphering chip with the default IPSEC encryption key of described message and described message; CPU0 in described first fire compartment wall and the binding of the first fire compartment wall ingress port; The described first fire compartment wall ingress port is the port that described first fire compartment wall links to each other with test cell;
S22: described first deciphering chip is encrypted described message according to the IPSEC encryption key of described message, and described encryption message is sent to CPU1 in first fire compartment wall;
S23: the CPU1 in described first fire compartment wall receives described encryption message, and described encryption message is sent to second fire compartment wall; CPU1 in described first fire compartment wall and described first fire compartment wall outlet port binding; Described first fire compartment wall outlet port is the port that described first fire compartment wall links to each other with vpn tunneling.
Preferably, CPU2 in first fire compartment wall and described first fire compartment wall ingress port binding;
CPU3 in first fire compartment wall and described first fire compartment wall outlet port binding.
Preferably, step S3 specifically comprises:
S31: the CPU3 in second fire compartment wall sends to described second deciphering chip with the default IPSEC decruption key of described encryption message and described encryption message; CPU3 in described second fire compartment wall and the binding of the second fire compartment wall ingress port; The described second fire compartment wall ingress port is the port that described second fire compartment wall links to each other with vpn tunneling;
S32: described second deciphering chip is decrypted described encryption message according to the IPSEC decruption key of described encryption message, and described decrypted message is sent to CPU2 in second fire compartment wall;
S33: the CPU2 in described second fire compartment wall sends to described test cell with described decrypted message; CPU2 in described second fire compartment wall and second fire compartment wall outlet port binding; Described second fire compartment wall outlet port is the port that described second fire compartment wall links to each other with test cell.
Preferably, CPU1 in second fire compartment wall and described second fire compartment wall ingress port binding;
CPU0 in second fire compartment wall and described second protecting wall outlet port binding.
The present invention also proposes the system that a kind of CPU E-Packets fast, and described system comprises:
Test cell is used for sending message to first fire compartment wall;
Described first fire compartment wall is used to receive the message that described test cell sends;
First deciphering chip is positioned at described first fire compartment wall, is used for according to the default IPSEC encryption key of described message described message being encrypted, and will encrypts message and send to second fire compartment wall;
Described second fire compartment wall is used to receive the described encryption message that first deciphering chip sends;
Second deciphering chip is positioned at described second fire compartment wall, is used for according to the default IPSEC decruption key of described message described encryption message being decrypted, and decrypted message is sent to described test cell.
Preferably, described system also comprises:
CPU0 in first fire compartment wall is positioned at described first fire compartment wall, and binds with the first fire compartment wall ingress port, is used for the default IPSEC encryption key of described message and described message is sent to described first deciphering chip; The described first fire compartment wall ingress port is the port that described first fire compartment wall links to each other with test cell;
Described first deciphering chip also is used for described encryption message is sent to CPU1 in first fire compartment wall;
CPU1 in described first fire compartment wall is positioned at described first fire compartment wall, and exports port binding with first fire compartment wall, is used to receive described encryption message, and described encryption message is sent to second protecting wall; Described first fire compartment wall outlet port is the port that described first fire compartment wall links to each other with vpn tunneling.
Preferably, described system also comprises:
CPU2 in first fire compartment wall is with described first fire compartment wall ingress port binding;
CPU3 in first fire compartment wall is with described first fire compartment wall outlet port binding.
Preferably, described system also comprises:
CPU3 in second fire compartment wall, be positioned at described second fire compartment wall, and bind with the second fire compartment wall ingress port, be used for the default IPSEC decruption key of described encryption message is sent to described second deciphering chip, the described second fire compartment wall ingress port is the port that described second fire compartment wall links to each other with vpn tunneling;
Described second deciphering chip also is used for described decrypted message is sent to CPU2 in second fire compartment wall;
CPU2 in described second fire compartment wall, be positioned at described second fire compartment wall, and with second fire compartment wall outlet port binding, be used for described decrypted message is sent to described test cell, described second fire compartment wall outlet port is the port that described second fire compartment wall links to each other with test cell.
Preferably, described system also comprises:
CPU1 in second fire compartment wall is with described second fire compartment wall ingress port binding;
CPU0 in second fire compartment wall is with described second protecting wall outlet port binding.
(3) beneficial effect
The method and system of the present invention by providing a kind of CPU to E-Packet fast, the speed that makes CPU E-Packet is handled the speed of message faster than deciphering chip.
Description of drawings
Fig. 1 is the CPU provided by the invention process schematic diagram that E-Packets fast;
Fig. 2 is a method flow diagram provided by the invention;
Fig. 3 is a system construction drawing provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described.
Embodiment one
The invention provides the method that a kind of CPU E-Packets fast, by deciphering chip and CPU are divided the work to optimize to the message processing procedure, the speed that makes CPU E-Packet is handled the speed of message faster than deciphering chip.2,4 and 8 hardware enciphering and deciphering chips are arranged respectively in basic, normal, high three product for deciphering chip, are example with the low-end product, only use 4 CPU and 2 deciphering chips.
As shown in Figure 1, for CPU carries out message repeating process schematic diagram, on fire compartment wall fwa, the ingress port g0/0/0 of CPU0 and CPU2 and fwa binding, the outlet port g0/0/1 binding of CPU1 and CPU3 and fwa; On fire compartment wall fwb, the ingress port g0/0/1 of CPU1 and CPU3 and fwb binding, the outlet port g0/0/0 binding of CPU0 and CPU2 and fwb.From the tester to fwa to fwb again to test cell, be a cyclic process.
As shown in Figure 2, the method that E-Packets fast of CPU comprises:
S1: test cell sends message to first fire compartment wall;
S2: first deciphering chip in described first fire compartment wall is encrypted described message according to the default IPSEC encryption key of described message, and will encrypt message and send to second fire compartment wall;
S3: second deciphering chip in described second fire compartment wall is decrypted described encryption message according to the default IPSEC decruption key of described message, and decrypted message is sent to described test cell.
Step S2 specifically comprises:
S21: the CPU0 in first fire compartment wall sends to described first deciphering chip with the default IPSEC encryption key of described message and described message; CPU0 in described first fire compartment wall and the binding of the first fire compartment wall ingress port; The described first fire compartment wall ingress port is the port that described first fire compartment wall links to each other with test cell;
S22: described first deciphering chip is encrypted described message according to the IPSEC encryption key of described message, and described encryption message is sent to CPU1 in first fire compartment wall;
S23: the CPU1 in described first fire compartment wall receives described encryption message, and described encryption message is sent to second fire compartment wall; CPU1 in described first fire compartment wall and described first fire compartment wall outlet port binding; Described first fire compartment wall outlet port is the port that described first fire compartment wall links to each other with vpn tunneling.
CPU2 in first fire compartment wall and the binding of the described first fire compartment wall ingress port;
CPU3 in first fire compartment wall and described first fire compartment wall outlet port binding.
Step S3 specifically comprises:
S31: the CPU3 in second fire compartment wall sends to described second deciphering chip with the default IPSEC decruption key of described encryption message and described encryption message; CPU3 in described second fire compartment wall and the binding of the second fire compartment wall ingress port; The described second fire compartment wall ingress port is the port that described second fire compartment wall links to each other with vpn tunneling;
S32: described second deciphering chip is decrypted described encryption message according to the IPSEC decruption key of described encryption message, and described decrypted message is sent to CPU2 in second fire compartment wall;
S33: the CPU2 in described second fire compartment wall sends to described test cell with described decrypted message; CPU2 in described second fire compartment wall and second fire compartment wall outlet port binding; Described second fire compartment wall outlet port is the port that described second fire compartment wall links to each other with test cell.
CPU1 in second fire compartment wall and the binding of the described second fire compartment wall ingress port;
CPU0 in second fire compartment wall and described second protecting wall outlet port binding.
By the method that adopts CPU to E-Packet fast, CPU1 and CPU3 bind with the outlet port of encryption chip and the outlet port of deciphering chip respectively, saved the process of searching route, and directly message is transmitted, the speed that makes CPU E-Packet is lower than the speed that deciphering chip is handled message.
Embodiment two
The present invention also proposes the system that a kind of CPU E-Packets fast, and as shown in Figure 2, described system comprises:
Test cell is used for sending message to first fire compartment wall;
Described first fire compartment wall is used to receive the message that described test cell sends;
First deciphering chip is positioned at described first fire compartment wall, is used for according to the default IPSEC encryption key of described message described message being encrypted, and will encrypts message and send to second fire compartment wall;
Described second fire compartment wall is used to receive the described encryption message that first deciphering chip sends;
Second deciphering chip is positioned at described second fire compartment wall, is used for according to the default IPSEC decruption key of described message described encryption message being decrypted, and decrypted message is sent to described test cell.
Preferably, described system also comprises:
CPU0 in first fire compartment wall is positioned at described first fire compartment wall, and binds with the first fire compartment wall ingress port, is used for the default IPSEC encryption key of described message and described message is sent to described first deciphering chip; The described first fire compartment wall ingress port is the port that described first fire compartment wall links to each other with test cell;
Described first deciphering chip also is used for described encryption message is sent to CPU1 in first fire compartment wall;
CPU1 in described first fire compartment wall is positioned at described first fire compartment wall, and exports port binding with first fire compartment wall, is used to receive described encryption message, and described encryption message is sent to second protecting wall; Described first fire compartment wall outlet port is the port that described first fire compartment wall links to each other with vpn tunneling.
Preferably, described system also comprises:
CPU2 in first fire compartment wall is with described first fire compartment wall ingress port binding;
CPU3 in first fire compartment wall is with described first fire compartment wall outlet port binding.
Preferably, described system also comprises:
CPU3 in second fire compartment wall, be positioned at described second fire compartment wall, and bind with the second fire compartment wall ingress port, be used for the default IPSEC decruption key of described encryption message is sent to described second deciphering chip, the described second fire compartment wall ingress port is the port that described second fire compartment wall links to each other with vpn tunneling;
Described second deciphering chip also is used for described decrypted message is sent to CPU2 in second fire compartment wall;
CPU2 in described second fire compartment wall, be positioned at described second fire compartment wall, and with second fire compartment wall outlet port binding, be used for described decrypted message is sent to described test cell, described second fire compartment wall outlet port is the port that described second fire compartment wall links to each other with test cell.
Preferably, described system also comprises:
CPU1 in second fire compartment wall is with described second fire compartment wall ingress port binding;
CPU0 in second fire compartment wall is with described second protecting wall outlet port binding.
Above execution mode only is used to illustrate the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1. the method that CPU E-Packets fast is characterized in that, described method comprises:
S1: test cell sends message to first fire compartment wall;
S2: first deciphering chip in described first fire compartment wall is encrypted described message according to the default IPSEC encryption key of described message, and will encrypt message and send to second fire compartment wall;
S3: second deciphering chip in described second fire compartment wall is decrypted described encryption message according to the default IPSEC decruption key of described message, and decrypted message is sent to described test cell.
2. method according to claim 1 is characterized in that step S2 specifically comprises:
S21: the CPU0 in first fire compartment wall sends to described first deciphering chip with the default IPSEC encryption key of described message and described message; CPU0 in described first fire compartment wall and the binding of the first fire compartment wall ingress port; The described first fire compartment wall ingress port is the port that described first fire compartment wall links to each other with test cell;
S22: described first deciphering chip is encrypted described message according to the IPSEC encryption key of described message, and described encryption message is sent to CPU1 in first fire compartment wall;
S23: the CPU1 in described first fire compartment wall receives described encryption message, and described encryption message is sent to second fire compartment wall; CPU1 in described first fire compartment wall and described first fire compartment wall outlet port binding; Described first fire compartment wall outlet port is the port that described first fire compartment wall links to each other with vpn tunneling.
3. method according to claim 2 is characterized in that, CPU2 in first fire compartment wall and the binding of the described first fire compartment wall ingress port;
CPU3 in first fire compartment wall and described first fire compartment wall outlet port binding.
4. method according to claim 1 is characterized in that step S3 specifically comprises:
S31: the CPU3 in second fire compartment wall sends to described second deciphering chip with the default IPSEC decruption key of described encryption message and described encryption message; CPU3 in described second fire compartment wall and the binding of the second fire compartment wall ingress port; The described second fire compartment wall ingress port is the port that described second fire compartment wall links to each other with vpn tunneling;
S32: described second deciphering chip is decrypted described encryption message according to the IPSEC decruption key of described encryption message, and described decrypted message is sent to CPU2 in second fire compartment wall;
S33: the CPU2 in described second fire compartment wall sends to described test cell with described decrypted message; CPU2 in described second fire compartment wall and second fire compartment wall outlet port binding; Described second fire compartment wall outlet port is the port that described second fire compartment wall links to each other with test cell.
5. method according to claim 4 is characterized in that, CPU1 in second fire compartment wall and the binding of the described second fire compartment wall ingress port;
CPU0 in second fire compartment wall and described second protecting wall outlet port binding.
6. the system that CPU E-Packets fast is characterized in that, described system comprises:
Test cell is used for sending message to first fire compartment wall;
Described first fire compartment wall is used to receive the message that described test cell sends;
First deciphering chip is positioned at described first fire compartment wall, is used for according to the default IPSEC encryption key of described message described message being encrypted, and will encrypts message and send to second fire compartment wall;
Described second fire compartment wall is used to receive the described encryption message that first deciphering chip sends;
Second deciphering chip is positioned at described second fire compartment wall, is used for according to the default IPSEC decruption key of described message described encryption message being decrypted, and decrypted message is sent to described test cell.
7. system according to claim 6 is characterized in that, described system also comprises:
CPU0 in first fire compartment wall is positioned at described first fire compartment wall, and binds with the first fire compartment wall ingress port, is used for the default IPSEC encryption key of described message and described message is sent to described first deciphering chip; The described first fire compartment wall ingress port is the port that described first fire compartment wall links to each other with test cell;
Described first deciphering chip also is used for described encryption message is sent to CPU1 in first fire compartment wall;
CPU1 in described first fire compartment wall is positioned at described first fire compartment wall, and exports port binding with first fire compartment wall, is used to receive described encryption message, and described encryption message is sent to second protecting wall; Described first fire compartment wall outlet port is the port that described first fire compartment wall links to each other with vpn tunneling.
8. system according to claim 7 is characterized in that, described system also comprises:
CPU2 in first fire compartment wall is with described first fire compartment wall ingress port binding;
CPU3 in first fire compartment wall is with described first fire compartment wall outlet port binding.
9. system according to claim 6 is characterized in that, described system also comprises:
CPU3 in second fire compartment wall, be positioned at described second fire compartment wall, and bind with the second fire compartment wall ingress port, be used for the default IPSEC decruption key of described encryption message is sent to described second deciphering chip, the described second fire compartment wall ingress port is the port that described second fire compartment wall links to each other with vpn tunneling;
Described second deciphering chip also is used for described decrypted message is sent to CPU2 in second fire compartment wall;
CPU2 in described second fire compartment wall, be positioned at described second fire compartment wall, and with second fire compartment wall outlet port binding, be used for described decrypted message is sent to described test cell, described second fire compartment wall outlet port is the port that described second fire compartment wall links to each other with test cell.
10. system according to claim 9 is characterized in that, described system also comprises:
CPU1 in second fire compartment wall is with described second fire compartment wall ingress port binding;
CPU0 in second fire compartment wall is with described second protecting wall outlet port binding.
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| CN201310088057.7A CN103220273B (en) | 2013-03-19 | 2013-03-19 | A kind of method and system of CPU fast-forwarding message |
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| CN201310088057.7A CN103220273B (en) | 2013-03-19 | 2013-03-19 | A kind of method and system of CPU fast-forwarding message |
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Cited By (2)
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| CN107204965A (en) * | 2016-03-18 | 2017-09-26 | 阿里巴巴集团控股有限公司 | The hold-up interception method and system of a kind of password cracking behavior |
| CN109639721A (en) * | 2019-01-08 | 2019-04-16 | 郑州云海信息技术有限公司 | IPsec message format processing method, device, equipment and storage medium |
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| CN102404339A (en) * | 2011-12-16 | 2012-04-04 | 山石网科通信技术（北京）有限公司 | Fire wall system and data processing method based on fire wall system |
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| CN102891848A (en) * | 2012-09-25 | 2013-01-23 | 汉柏科技有限公司 | Method for carrying out encryption and decryption by using IPSec security association |
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| US20100191958A1 (en) * | 2006-09-29 | 2010-07-29 | Panasonic Corporation | Method and network device for processing nested internet protocol security tunnels |
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