CN103219882A - CTS2 charge pump - Google Patents

Abstract

The invention discloses a CTS2 charge pump. An NMOS pipe of a last-stage conveying pipe of the CTS2 charge pump is replaced by a PMOS pipe. Switching of control voltage of the PMOS pipe between zero and output voltage is achieved through strength changes of clock signals. Conveying pipes at various stages, particularly the last-stage conveying pipe can be connected when needed and therefore influences of a threshold voltage bulk effect are completely eliminated.

Description

A kind of CTS2 charge pump

Technical field

The present invention relates to the electron trade power technique fields, relate in particular to a kind of second generation charge transfer switch (Charge Transfer Switch 2 is called for short CTS2) charge pump.

Background technology

For many nonvolatile memories, its read-write operation needs high voltage (also may be negative high-voltage), so charge pump is widely used in the memory, is used to provide the high voltage or the negative voltage that are higher than outer power voltage.Simultaneously, along with the increase of complex circuit designs, various hybrid circuits arise at the historic moment, the simple voltage that relies on external power source to provide can not meet the demands far away, it can address this problem the decision of electric charge pump characteristics, and particularly along with the decline of supply voltage, charge pump applications more and more widely.

Fig. 1 is the structural representation of prior art Dixon (Dickson) charge pump.All metal-oxide-semiconductor among the figure (MD1～all are NMOS pipes, and be to link together MDn+1) with the diode form.Wherein, grid end and the source end of MD1 are connected to supply voltage VDD, and its drain terminal is connected to source end and the grid end of MD2; The drain terminal of MD2 is connected to grid end and the source end of MD3 again, and the like, the grid end of MDn and source end are connected to the drain terminal of MDn-1, the drain terminal of MDn is connected to source end and the grid end of MDn+1, the drain terminal of MDn+1 meets load resistance RL and load capacitance Cout, and the junction between MD1 and the MD2 is a node 1, and the junction between MD2 and the MD3 is a node 2, and the like, junction between MDn and the MDn+1 is node n, and (1～n) passes through capacitor C p (pumping electric capacity is got identical value Cp) is connected to two-phase non-overlapping clock CLK and CLKB to node m, wherein the odd number node (1,3,5...) be connected to same road clock CLK, even number node (2,4,6...) be connected to another road clock CLKB.Each node all has a parasitic capacitance between low, be worth to be Cs.

For Dickson charge pump as shown in Figure 1, wherein Cp represents pumping electric capacity, for identical value, represents with Cpump, and Cs is a parasitic capacitance, and Cload is a load capacitance.Voltage difference expression formula between the adjacent two-stage is as follows:

ΔV＝V _n+1-V _n＝V _Φ′-V _T，

Wherein, V _ΦWhen the each clock signal high level of ' representative arrives, the added value of the voltage magnitude between the each point, expression formula is as follows:

$V_{\mathrm{\Φ}}^{\′}=\left(\frac{C_{\mathrm{pump}}}{C_{\mathrm{pump}}+C_S}\right)*\mathrm{VDD}.$

Because the existence of load current, so still there is a voltage drop in every grade of charge pump, the relation of this voltage drop and load is as follows:

I _Out=f* (C _Pump+ C _S) * V _LThereby, as can be known,

By above expression formula as can be known, output voltage expression formula is as follows

$\mathrm{Vout}=\mathrm{VDD}+N\·(\frac{\mathrm{Cpump}}{\mathrm{Cpump}+\mathrm{Cs}}\mathrm{VDD}-\mathrm{Vt}-\frac{\mathrm{Iload}}{f(\mathrm{Cpump}+\mathrm{Cs})})-\mathrm{Vt}$

$=\mathrm{Vo}\max -N\frac{\mathrm{Ilod}}{f(\mathrm{Cpump}+\mathrm{Cs})}$

$=\mathrm{Vo}\max -\mathrm{Rout}\·\mathrm{Iload}$

Wherein, $\mathrm{Vo}\max =\mathrm{VDD}+N\·(\frac{\mathrm{Cpump}}{\mathrm{Cpump}+\mathrm{Cs}}\mathrm{VDD}-\mathrm{Vt})-\mathrm{Vt}$

Obviously, because the afterbody amplifying unit is the form of a diode, the source end and the voltage difference between the substrate of transfer tubes at different levels are not 0, have the influence of threshold voltage and bulk effect.Because the influence of threshold voltage and bulk effect has limited being extensive use of of Dickson charge pump.

After Dixon (Dickson) charge pump occurred, various charge pump improvement technology emerged in an endless stream, and wherein a kind of is exactly the CTS2 charge pump construction.This CTS2 charge pump section has solved the influence of above-mentioned threshold voltage and bulk effect.Fig. 2 is the structural representation of prior art CTS2 charge pump.As shown in Figure 2, MD1～MD4 all is NMOS pipes, and is that the diode form links together.MD1 source end and grid end are connected to supply voltage VDD, and the drain terminal of MD1 is connected to source end and the grid end of MD2, and the drain terminal of MD2 is connected to source end and the grid end of MD3, and the drain terminal of MD3 is connected to source end and the grid end of MD4, and the drain terminal of MD4 is connected to output.Junction between MD1 and the MD2 is a node 1, and the junction between MD2 and the MD3 is a node 2, and the junction between MD3 and the MD4 is a node 3.Node 1 and node 3 are connected to clock CLK by capacitor C 1 and C3 respectively, and node 2 is connected to clock CLKB by capacitor C 2, and clock CLK and CLKB are the two-phase non-overlapping clocks.

MS1～MS4 all is NMOS pipes, and the source end of MSm (m=1～3) is connected to the source end of MDm, and drain terminal is connected to the drain terminal of MDm.Source end and the grid end of MS4 are connected to node 3, and the drain terminal of MS4 is connected to clock signal clk B by capacitor C 4.

MN1～MN3 all is NMOS pipes, and MP1～MP3 all is PMOS pipes, and MN1 and MP1 form inverter structure, the source end of MN1 is connected to supply voltage VDD, the source end of MP1 is connected to node 2, and the grid end of MN1 and MP1 is connected to node 1, and the drain terminal of MN1 and the drain terminal of MP1 are linked the grid end of MS1 together again.MN2 and MP2 form inverter structure, and the source end of MN2 is connected to node 1, and the source end of MP2 is connected to node 3, and the grid end of MN2 and MP2 is linked node 2, and the drain terminal of MN2 and the drain terminal of MP2 are linked the grid end of linking MS2 together again.MN3 and MP3 form inverter structure, and the source end of MN3 is connected to the source end of MS4, and the source end of MP3 is connected to node 2, and the grid end of MN3 and MP3 is linked node 3, and the drain terminal of MN3 and the drain terminal of MP3 are linked and linked node 3 together again.

Observe among Fig. 2 by MD2 MS2, MN2, the little module that MP2 forms, when clock signal clk is a high level, when clock signal clk B was low level, node 1 and node 3 were high level, node 2 is a low level, and wish that MS2 can all open this moment, and the high level of node 1 is passed to node 2.Under the effect of node 2 low levels and node 3 high level, MS2 can all open, the level of node 1,2 and 3 is all passed to the grid end of NMOS pipe MS2, thus this moment MS2 gate source voltage very big (ideally being 2VDD), thereby MS2 can thoroughly open with transmission current; When clock signal clk is a low level, when clock signal clk B was high level, node 1 and node 3 were low level, and node 2 is a high level, and wish that MS2 can thoroughly close this moment, to stop from node 2 to node the generation of 1 current reflux.Under node 2 high level and node 1 low level effect, MN2 can all open, and the low level of node 1 is transferred to the grid end of MS2, and this moment, the gate source voltage of MS2 was 0, thereby MS2 can thoroughly close to stop to reflux and takes place.So, by the grid terminal voltage of control transmission pipe, it can be opened and turn-off completely in needs, thereby part is eliminated the threshold voltage influence, also can eliminate the generation that reversed charge refluxes simultaneously.At this moment, it is as follows that output voltage is expressed formula

$\mathrm{Vout}=\mathrm{VDD}+N\·(\frac{\mathrm{Cpump}}{\mathrm{Cpump}+\mathrm{Cs}}\mathrm{VDD}-\frac{\mathrm{Iload}}{f(\mathrm{Cpump}+\mathrm{Cs})})-\mathrm{Vt}.$

But, in existing CTS2 charge pump,, remain the form of a diode, thereby the influence of threshold voltage and bulk effect is not eliminated thoroughly still because the afterbody amplifying unit is still the same with the Dickson structure.

Summary of the invention

(1) technical problem that will solve

For solving above-mentioned one or more problems, the invention provides a kind of follow-on CTS2 charge pump, to eliminate the influence of threshold voltage and bulk effect more completely.

(2) technical scheme

According to an aspect of the present invention, provide a kind of CTS2 charge pump.This charge pump comprises: the N level amplifying unit of cascade, N 〉=2.Wherein, the N level amplifying unit in the N level amplifying unit comprises: N level transfer tube (MD4), be the PMOS pipe, and its source end is connected to the drain terminal of the N-1 level transfer tube (MD3) in the N-1 level amplifying unit in the N level amplifying unit, and its drain terminal is connected to output; The 12 NMOS manages (MS4), and its source end and grid end are connected to the drain terminal of the N-1 level transfer tube (MD3) in the N-1 level amplifying unit, and its drain terminal is connected to the clock signal of CTS2 charge pump by the 4th electric capacity (C4); Control module, its input is connected with the clock signal of CTS2 charge pump, and its output is connected to the grid end of N level transfer tube (MD4), is used for when the clock signal is low level, output low level controls signal to the grid end of N level transfer tube (MD4), and it is opened; When the clock signal was high level, output low level controlled signal to the grid end of N level transfer tube (MD4), and it is closed.

(3) beneficial effect

From technique scheme as can be seen, the present invention has following beneficial effect:

1, transfer tubes at different levels among the present invention, especially afterbody transfer tube can thorough conductings in needs, thereby thoroughly eliminate the influence of threshold voltage and bulk effect, by computing formula as can be known output voltage can access increase;

2, compare with the CTS2 charge pump of prior art, under the input voltage situation consistent with input current, the present invention can access higher output voltage and output current, thereby has proved the lifting of power-conversion efficiencies.

Description of drawings

Fig. 1 is the structural representation of prior art Dixon (Dickson) charge pump;

Fig. 2 is the structural representation of prior art CTS2 charge pump;

Fig. 3 is the structural representation of the CTS2 charge pump of the embodiment of the invention;

Fig. 4 a is for working as supply voltage under the 3.3V situation, the oscillogram that the output voltage of Dixon (Dickson) charge pump, prior art CTS2 charge pump and embodiment of the invention CTS2 charge pump changes with different progression;

Fig. 4 b works as supply voltage under the 3.3V situation, the oscillogram that the output voltage of Dixon (Dickson) charge pump, prior art CTS2 charge pump and embodiment of the invention CTS2 charge pump changes with the different loads electric current.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.Though this paper can provide the demonstration of the parameter that comprises particular value, should be appreciated that parameter need not definitely to equal corresponding value, but can in acceptable error margin or design constraint, be similar to described value.

The charge pump of the elimination threshold voltage influence that the embodiment of the invention provides, be that the CTS2 charge pump construction is improved, replace in the CTS2 charge pump construction NMOS pipe with PMOS pipe as the afterbody transfer tube, and with the height variation of this control pmos system voltage by clock signal be implemented in 0 and output voltage between switching.Those skilled in the art are to be understood that; though be that example describes with the level Four amplifying unit herein; but in fact the technology of amplifying unit can freely be selected as required; as long as the transfer tube of its afterbody amplifying unit is replaced by the NMOS pipe in order to the PMOS pipe, should be included within protection scope of the present invention equally.

Fig. 3 is the structural representation of the CTS2 charge pump of the embodiment of the invention.As shown in Figure 3, what amplifying unit of front still adopts CTS2 charge pump construction shown in Figure 2, fourth stage amplifying unit adopts improved structure, and its transfer tube has changed the PMOS pipe into by the NMOS pipe, and purpose is to eliminate threshold voltage and the bulk effect that this grade use NMOS pipe causes.Specifically, fourth stage amplifying unit comprises: the 4th grade of transfer tube (MD4), the 12 NMOS manage (MS4) and control module.Below each several part is elaborated.

The 4th grade of transfer tube (MD4) is the PMOS pipe, and its source end is connected to the drain terminal of the 3rd level transfer tube (MD3) in the 3rd level amplifying unit, and its drain terminal is connected to output.The grid terminal voltage of PMOS pipe MD4 derives from control module (Control Module is called for short CM).Obviously, when CLK is a high level, when CLKB was low level, MD4 needed conducting to carry out transmission charge.

The 12 NMOS manages (MS4), and its source end and grid end are connected to the drain terminal of the 3rd level transfer tube (MD3) in the described 3rd level amplifying unit, i.e. the 3rd node (node 3), and its drain terminal is connected to the clock signal of described CTS2 charge pump by the 4th electric capacity (C4).The purpose that connects MS4 is to improve the control unit MN3 and the needed control high pressure of MP3 of upper level.

Control module, its input is connected with the clock signal of described CTS2 charge pump, and its output is connected to the grid end of described N level transfer tube (MD4), is used for when described clock signal is low level, output low level controls signal to the grid end of described N level transfer tube (MD4), and it is opened; When described clock signal was high level, output low level controlled signal to the grid end of described N level transfer tube (MD4), and it is closed.Below provide a concrete control module structure, those skilled in the art should design according to its explanation and realize the identical function control module, equally should be within the protection range of claim of the present invention.

For control module, because second clock signal (CLKB) is a low level, thereby at the 4th NMOS pipe (MN4), the 5th NMOS pipe (MN5) and the 5th PMOS pipe (MP4), under (MP5) four the pipe effects of the 6th PMOS pipe, the voltage of B node (Node B) is pulled to ground, then because the grid terminal voltage of MN6 and MP6 is that B node (Node B) voltage is low level, thereby C node (node C) voltage is OUT, under the effect of MN7 and MP7, D node (node D) voltage is low level, thereby thoroughly opens afterbody transfer tube (MD4), better to the output voltage charging, this just in time satisfies the requirement of the thorough conducting of MD4 needs; Yet when first clock signal (CLK) is a low level, second clock signal (CLKB) is between high period, MD4 need turn-off to stop electric charge to reflux, obviously at the 4th NMOS pipe (MN4), the 5th NMOS pipe (MN5) and the 5th PMOS pipe (MP4), under (MP5) four the pipe effects of the 6th PMOS pipe, the voltage of B node (Node B) is OUT, then because the grid terminal voltage of MN6 and MP6 is that B node (Node B) voltage is high level, thereby C node (node C) voltage is low level, under the effect of MN7 and MP7, D node (node D) voltage is high level, thereby turn-off afterbody transfer tube (MD4), stop current reflux, just in time satisfy the MD4 needs and turn-off to stop the requirement of electric charge backflow.

Junction between MD1 and the MD2 is first node (node 1), and the junction between MD2 and the MD3 is Section Point (node 2), and the junction between MD3 and the MD4 is the 3rd node (node 3).First node (node 1) and the 3rd node (node 3) are linked first clock signal clk by capacitor C 1 and C3 respectively, Section Point (node 2) is linked second clock signal CLKB by capacitor C 2, and first clock signal clk and second clock signal CLKB are two-phase non-overlapping clock signals.MS1～MS4 all is NMOS pipes, and the source end of MSm (m=1～3) is connected to the source end of MDm, and drain terminal is connected to the drain terminal of MDm.The source end of MS4 and grid end are connected to the 3rd node (node 3), and the drain terminal of MS4 is linked clock signal clk B by capacitor C 4.

MN1～MN3 all is NMOS pipes, MP1～MP3 all is PMOS pipes, MN1 and MP1 form inverter structure, the source end of MN1 is connected to supply voltage VCC, the source end of MP1 is connected to Section Point (node 2), the grid end of MN1 and MP1 is linked first node (node 1), and the drain terminal of MN1 and the drain terminal of MP1 are linked the grid end of linking MS1 together again.MN2 and MP2 form inverter structure, the source end of MN2 is connected to first node (node 1), the source end of MP2 is connected to the 3rd node (node 3), and the grid end of MN2 and MP2 is linked Section Point (node 2), and the drain terminal of MN2 and the drain terminal of MP2 are linked the grid end of linking MS2 together again.MN3 and MP3 form inverter structure, the source end of MN3 is connected to the source end of MS4, the source end of MP3 is connected to Section Point (node 2), and the grid end of MN3 and MP3 is linked the 3rd node (node 3), and the drain terminal of MN3 and the drain terminal of MP3 are linked and linked the 3rd node (node 3) together again.

Observe among Fig. 3 now by MD2, MS2, MN2, the one-level amplifying unit that MP2 forms is when first clock signal clk is a high level, when second clock signal CLKB is low level, first node (node 1) and the 3rd node (node 3) are high level, Section Point (node 2) is a low level, and wish that MS2 can all open this moment, and the high level of first node (node 1) is passed to Section Point (node 2).Under the effect of Section Point (node 2) low level and the 3rd node (node 3) high level, MS2 can all open, the 3rd node (node 3) level is all passed to the grid end of NMOS pipe MS2, so this moment MS2 gate source voltage very big (ideally being 2VDD), thereby MS2 can thoroughly open with transmission current; When first clock signal clk is a low level, when second clock signal CLKB is high level, first node (node 1) and the 3rd node (node 3) are low level, Section Point (node 2) is a high level, wish that MS2 can thoroughly close this moment, to stop the generation of the current reflux from Section Point (node 2) to first node (node 1).Under Section Point (node 2) high level and the low level effect of first node (node 1), MN2 can all open, the low level of first node (node 1) is transferred to the grid end of MS2, and this moment, the gate source voltage of MS2 was 0, thereby MS2 can thoroughly close to stop to reflux and takes place.So, by the grid terminal voltage of control transmission pipe, it can be opened and turn-off completely in needs, thereby eliminate the threshold voltage influence, also can eliminate the generation that reversed charge refluxes simultaneously.

Obviously, when first clock signal clk is a high level, second clock signal CLKB is between low period, first node (node 1) is relative high level with the 3rd node (node 3), Section Point (node 2) is relative low level, obviously by the control of MN1 and MP1, MS1 turn-offs, thereby first node (node 1) electric current can not reflux left; By the interaction of MN2 and MP2, thoroughly open the MS2 conduction pipe, thereby the voltage of first node (node 1) charges to Section Point (node 2); Analyze successively and obtain the MS3 shutoff, MS4 opens, because first clock signal clk is a high level, thereby under the control module effect, D voltage is pulled to ground, thereby thoroughly opens MD4, better output voltage is charged.When first clock signal clk is a low level, second clock signal CLKB is between high period, first node (node 1) is relative low level with the 3rd node (node 3), Section Point (node 2) is relative high level, control MS1 and MS3 open, thereby VCC and Section Point (node 2) charge to first node (node 1) and the 3rd node (node 3) respectively; MS4 turn-offs, and first clock signal clk is a low level, and obviously under Control Module (CM) effect, D voltage equals output voltage, thereby turn-offs MD4, stops current reflux.By above analysis as can be known, all transmitting stages of front and afterbody have all been eliminated the influence that threshold voltage and bulk effect are brought, so the present invention can greatly improve output voltage.

Fig. 4 a works as supply voltage under the 3.3V situation, the oscillogram that the output voltage of Dixon (Dickson) charge pump, prior art CTS2 charge pump and embodiment of the invention CTS2 charge pump changes with different progression.By Fig. 4 a as can be known, embodiment of the invention CTS2 charge pump all has two kinds of output voltages that structure is higher than other on any progression.

Fig. 4 b works as supply voltage under the 3.3V situation, the oscillogram that the output voltage of Dixon (Dickson) charge pump, prior art CTS2 charge pump and embodiment of the invention CTS2 charge pump changes with the different loads electric current.By Fig. 4 b as can be known, embodiment of the invention CTS2 charge pump all has two kinds of output voltages that structure is higher than other under any load current.

In sum, from technique scheme as can be seen, the present invention has following beneficial effect:

1, utilize the present invention, transfer tubes at different levels, especially afterbody transfer tube can thorough conductings in needs, thereby eliminate the influence of threshold voltage and bulk effect, by computing formula as can be known output voltage can access increase;

2, utilize the present invention, under the input voltage situation consistent, can access higher output voltage and output current, thereby prove the lifting of power-conversion efficiencies with input current.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (8)

1. a CTS2 charge pump is characterized in that, comprising: the N level amplifying unit of cascade, and described N 〉=2, the N level amplifying unit in the wherein said N level amplifying unit comprises:

N level transfer tube (MD4) is the PMOS pipe, and its source end is connected to the drain terminal of the N-1 level transfer tube (MD3) in the N-1 level amplifying unit in the described N level amplifying unit, and its drain terminal is connected to output;

The 12 NMOS manages (MS4), and its source end and grid end are connected to the drain terminal of described N-1 level transfer tube (MD3), and its drain terminal is connected to the clock signal of described CTS2 charge pump by the 4th electric capacity (C4);

Control module, its input is connected with the clock signal of described CTS2 charge pump, and its output is connected to the grid end of described N level transfer tube (MD4), is used for when described clock signal is low level, output low level controls signal to the grid end of described N level transfer tube (MD4), and it is opened; When described clock signal was high level, output low level controlled signal to the grid end of described N level transfer tube (MD4), and it is closed.

2. CTS2 charge pump according to claim 1 is characterized in that, manages the drain terminal of (MS4) for described the 12 NMOS: when N is odd number, be connected to first clock signal (CLK) by described the 4th electric capacity (C4); When N is even number, be connected to second clock signal (CLKB) by described the 4th electric capacity (C4).

3. CTS2 charge pump according to claim 1, it is characterized in that, described control module comprises: the 4th NMOS pipe (MN4), the 5th NMOS pipe (MN5), the 6th NMOS pipe (MN6) and the 7th NMOS pipe (MN7), and the 5th PMOS pipe (MP4), the 6th PMOS pipe (MP5), the 7th PMOS pipe (MP6) and the 8th PMOS pipe (MP7);

The 4th NMOS pipe (MN4), the 5th NMOS pipe (MN5), the 5th PMOS pipe (MP4) and the 6th PMOS pipe (MP5) are connected with the cross-couplings form, the source end ground connection of the 4th NMOS pipe (MN4) and the 5th NMOS pipe (N5), the source end of the 5th PMOS pipe (MP4) and the 6th PMOS pipe (MP5) is connected to the output of described control module, the grid end of the 4th NMOS pipe (MN4) is connected to described clock signal, and described clock signal is through being connected to the grid end of the 5th NMOS pipe (MN5) after the inverter.

4. CTS2 charge pump according to claim 3 is characterized in that, the drain terminal intersection point of described the 4th NMOS pipe (MN4) and the 5th PMOS pipe (MP4) is A node (node A), and A node (node A) is connected to the 6th PMOS pipe (MP5) grid end;

The drain terminal intersection point of the 5th NMOS pipe (MN5) and the 6th PMOS pipe (MP5) is a B node (Node B), B node (Node B) is connected to the grid end of the 5th PMOS pipe (MP4), the 6th NMOS pipe (MN6) is connected for inverter with the 7th PMOS pipe (MP6), the two grid end is connected to B node (Node B), and the source end of the 7th PMOS pipe (MP6) is connected to ground;

The source end of the 7th PMOS pipe (MP6) is connected to the output of described control module, the drain terminal of the two is connected to C node (node C), the 7th NMOS pipe (MN7) is connected for inverter with the 8th PMOS pipe (MP7), the two grid end is connected to C node (node C), and the source end of the 7th NMOS pipe (MN7) is connected to ground;

The source end of the 8th PMOS pipe (MP7) is connected to the output of described control module, and the drain terminal contact of the two is D node (node D); D node (node D) is connected to the grid end of N level transfer tube (MD4).

5. CTS2 charge pump according to claim 1 is characterized in that, the I level amplifying unit in the N level amplifying unit of described cascade except that described N level amplifying unit comprises:

I level transfer tube (MD2) is the NMOS pipe, and its drain terminal is connected to I node (node 2), and its source end and grid end are connected to I-1 node (node 1);

The tenth NMOS manages (MS2), and its source end is connected to described I node (node 2), and its drain terminal is connected to I-1 node (node 1);

The 14 NMOS manages (MN2), and its grid end is connected to I node (node 2), and its source end is connected to I-1 node (node 1), and its drain terminal is connected to the grid end of described the tenth NMOS pipe (MS2);

The 2nd PMOS manages (MP2), and its grid end is connected to I node (node 2), and its source end is connected to I-1 node (node 1), and its drain terminal is connected to the grid end of described the tenth NMOS pipe (MS2);

Wherein, for described I node, when I=0, it is connected to supply voltage, and when I＞0, it is connected to the drain terminal of I level transfer tube and the source end of I+1 level transfer tube.

6. CTS2 charge pump according to claim 5 is characterized in that, for described I node (node 2),

When I is odd number, be connected to first clock signal (CLK) by I electric capacity (C2);

When I is even number, be connected to second clock signal (CLKB) by I electric capacity (C2).

7. CTS2 charge pump according to claim 6 is characterized in that, described first clock signal (CLK) and second clock signal (CLKB) are anti-phase.

8. according to each described CTS2 charge pump in the claim 1 to 7, it is characterized in that, be used to non-volatility memorizer that read/write operation voltage is provided.

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