CN103218246A - Binary tool generating method based on graph description language - Google Patents
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Abstract
The invention provides a binary tool generating method based on a graph description language. According to the graph description language, grammar and encoding of an instruction set are specified through a mixed mode of a centralizing definition mode and a distribution definition mode. The graph description language includes two basic language elements, namely nodes and edges. The nodes are used for describing partial attributes of an instruction set architecture, and each node can be provided with a plurality of sub nodes which can be used for describing the attributes of the instruction set architecture more meticulously. Through the binary tool generating method based on the graph description language, after a graph description model of the instruction set architecture of a processor is obtained, a binary tool generator generates an assembler, a disassembler, a linker and other binary tools according to related descriptions in the model.
Description
Technical field
The invention belongs to the processor design field, be specifically related to a kind of based on the figure descriptive language with scale-of-two instrument generation method.
Background technology
In the modern processors design cycle, processor architecture descriptive language (ADL, Architecture Description Language) is used for the modeling of abstraction hierarchy such as accurately of behavioral scaling that processor is instructed and cycle.Also be used for the automatic generation of processor programming tool simultaneously based on the processor model of ADL.These programming tools comprise higher level lanquage (C/C++, the Fortran etc.) compiler of retargetable, and various scale-of-two instrument (binary utility) is as assembler, disassembler, linker etc.Adopt ADL to processor architecture modeling and the greatly design in early stage of simplified processor prototype of the way of the various programming tools of generation automatically on the ADL model based, particularly the source code of having avoided loaded down with trivial details is managed, renewal and synchronous because every characteristic of processor is described by unification, concentrated area, and has reduced the difficulty that subsequent document is safeguarded.Guaranteed the consistance of processor model and its programming tool based on the processor modeling method of ADL.
The ADL that is used for the processor architecture modeling is described processor from two broad aspect:
1. calculating resource of processor.These resources are general only need comprise the programmer visible, with the direct relevant computational resource of its instruction set, as register, storer, streamline, calculating unit etc.
2. the instruction set architecture of processor.Instruction set architecture has been stipulated arithmetic type (showing as some concrete instructions), the various restriction relations between the instruction and the mapping between computing and the calculating unit etc. that processor is supported.
When instruction set architecture was described, ADL defined instruction from following several aspects:
1. Zhi Ling the syntax.As " add r1, r2r3 ".The instruction syntax are convenient to people's reading comprehension.It has stipulated text formatting that processor is programmed, is the input content of assembler, is the output content of disassembler simultaneously.
2. Zhi Ling binary coding.Binary coding is the equivalent form of value that the instruction syntax are described.It is unfavorable for people's direct reading understanding, only reads in translation for machine.It is the output content of assembler, the input content of disassembler.
3. Zhi Ling semanteme.The behavior of processor when execution command stipulated in the semanteme of instruction.Instruction semantic is described difference according to abstraction hierarchy and is divided into that behavioral scaling is described and the cycle accurately describes, and it is the standard of behaviour of processor simulation device.Instruction semantic according to different abstraction hierarchies is described processor simulation device and the accurate processor simulation device of cycle that generates behavioral scaling respectively.
The instruction set architecture of modern processors has shown certain hierarchical structure.Such instruction set can be regarded general programming language as, and the Partial Feature in the type of service language description instruction set.
Based on BNF (Backus-Naur Form) though formal language the grammatical feature of instruction set architecture can be described, and can realize order number (function promptly collects) in principle, it can't be described the scale-of-two of instruction be translated as text instruction.Decode procedure is the BFS (Breadth First Search) to the instruction set encoding tree in essence.Simultaneously, also can portray its logical organization based on the formal language of BNF with figure.Thus, the syntax are being described and coding is described when being integrated into a kind of unified domain-specific language, the figure descriptive language is a kind ofly to select very easily.
Summary of the invention
(1) technical matters that will solve
The language of description instruction set and the scale-of-two instrument that compiling means accordingly generate processor are provided in the current processor design platform based on ADL.But as previously mentioned, this class instruction set descriptive language adopts the mode of simply enumerating that the instruction in the instruction set is defined one by one, so can't know instruction set architecture by inference from final command collection description document, perhaps there is a large amount of redundancies in instruction set in describing.And day by day abundant along with modern processors instruction set content, the homogeneity content in the instruction set is accumulation thereupon also, and traditional instruction set describing mode has not been suitable for such instruction set modeling.
Technical matters to be solved by this invention is to propose a kind of scale-of-two instrument generation method based on the figure descriptive language, to solve the above problems.
(2) technical scheme
The present invention propose a kind of based on the figure descriptive language with scale-of-two instrument generation method, comprise the steps: step S1: use figure descriptive language is described the instruction set of target processor, obtains the instruction set model; Step S2: use the instruction set model compiler that the instruction set model is compiled, obtain the scale-of-two instrument of processor.
According to a kind of embodiment of the present invention, described step S2 comprises: step S2.1: model compiler is carried out morphology and grammatical analysis to the instruction set model, makes up the instruction set cut-away view, the relational structure between portrayal instruction and the instruction fragment; Step S2.2: model compiler is collected the instruction syntax definition on the basis of instruction set cut-away view, merge into unified instruction set syntactic definition then.
According to a kind of embodiment of the present invention, described step S2 also comprises step S2.3: in step S2.2, model compiler is collected order number information on the basis of instruction set cut-away view, merge into unified instruction set encoding mode then.
According to a kind of embodiment of the present invention, described step S2 also comprises step S2.5: the instruction set encoding information that obtains according to step S2.3 generates instruction set encoding device and demoder.
According to a kind of embodiment of the present invention, described step S2 also comprises step S2.4: the instruction set syntactic definition that obtains according to step S2.2 generates instruction set syntax analyzer and printer.
According to a kind of embodiment of the present invention, described step S2 also comprises step S2.6: instruction set syntax analyzer and scrambler merge formation instruction set assembler; Instruction set demoder and printer merge formation instruction set disassembler.
(3) beneficial effect
Scale-of-two instrument generation method of the present invention is carried out modeling by use figure descriptive language to the modern processors instruction set, can express the instruction set inner structure intuitively on the one hand, avoids redundant instruction description; Can automatically generate programming on bottom layer instruments such as assembler/disassembler on the other hand.
Description of drawings
Fig. 1 is the schematic flow sheet of the scale-of-two instrument generation method of target processor instruction set;
Show to Fig. 2 example the internal logical structure of instruction set architecture.
Embodiment
The figure descriptive language is the general term of a class domain-specific language, is applicable to describe the object that inner element has related nested structure, is used to describe processor instruction set in the present invention.In the figure descriptive language, the relation between two language elements is with " limit (edge) " portrayal.Thereby related language element can constitute the logical organization that new language element forms language.
The mode that this figure descriptive language mixes with the centralized definition and the definition that distributes has been stipulated the syntax and the coding of instruction set.Figure descriptive language of the present invention has comprised node (node) and limit (edge) two kinds of basic language elements.Node is described the part attribute of instruction set architecture, and a node can have the experimental process node.Child node has been portrayed the attribute of instruction set architecture more meticulously.With the frontier juncture connection, portrayed the relation of node in the definition on limit between node and its child node with its related child node.
Scale-of-two instrument generation method based on the figure descriptive language of the present invention comprises the steps:
Step S1: use figure descriptive language is described the instruction set of target processor, obtains the instruction set model.In following example, use figure descriptive language carries out modeling to target instruction set.
Step S2: use instruction set model compiler (as the MADL compiler in the example) that the instruction set model is compiled, obtain the scale-of-two instrument of processor.Comprise following substep:
Step S2.1: model compiler is carried out morphology and grammatical analysis to the instruction set model, makes up the instruction set cut-away view, the relational structure between portrayal instruction and the instruction fragment.
Step S2.2: model compiler is collected the instruction syntax definition on the basis of instruction set cut-away view, merge into unified instruction set syntactic definition then.
Step S2.3: with the S2.2 while, model compiler is collected order number information on the basis of instruction set cut-away view, merge into unified instruction set encoding mode then.
Step S2.4: the instruction set syntactic definition that obtains according to S2.2 generates instruction set syntax analyzer and printer.
Step S2.5: the instruction set encoding information that obtains according to S2.3 generates instruction set encoding device and demoder.
Step S2.6: instruction set syntax analyzer and scrambler merge formation instruction set assembler; Instruction set demoder and printer merge formation instruction set disassembler.
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
Fig. 1 is the schematic flow sheet of the scale-of-two instrument generation method of target processor instruction set.As shown in Figure 1:
The mode that the centralized definition and the definition that distributes mix is described the instruction set of processor.It comprises node (node) and limit (edge) two kinds of fundamentals.The node correspondence the description of the some characteristics of instruction.Intra-node can comprise several territories (field), is the description carrier of instruction characteristic.Relation between the territory of node and its child node is represented with the limit.Child node is related with its father node by the territory, and each child node integrates intactly describes father node.
A node is overseas except comprising several, also comprises the syntax that two built-in attribute: asm and code.asm are used to specify instruction, and code is used to specify the coding of instruction.Intranodal can also comprise Custom Attributes.
Can comprise in the node and assert that (predicate) is to make constraint to node residing state when moving.Assert that the special circumstances that are used for instruction set simulate.
Having comprised class and group in the figure descriptive language facilitates for the processor instruction set modeling.Class is used to the definition of node that template is provided.Group is one group of set with node of certain similarity, and it is just the same with node in the use.
The part syntax that figure describes:
1.Node：node_n?Def
Field：field_n?Def
2.Edge：_n1-＞_n2Def
3.Group：group_g?Gdef
4.Def：；|{Statement}
5.Gdef：；|{MemberList[Statement]}
6.Statement：...
7.MemberList：member_n1[，_n2]；
8.Predicate：predicate[_name]{[C/C++source?codes]}
The instruction set architectural framework modeling example that comprises arithmetic logical operation commonly used:
Table 1 computational resource
Table 2 instruction set
Fragment 1 has defined first node i sa, and it is as the root node of figure.
Fragment 2 has defined 4 nodes, and register is carried out modeling.
Fragment 3 has defined a registers group.
The logic class instruction ﹠ that the node of fragment 4 definition is used for organizing above-mentioned example instruction set to mention, |, △
Fragment 5 has defined a limit from node i sa to node logic, has stipulated the relation of two nodes in the definition on limit.
Fragment 6 has defined from the lhs territory of node logic to the limit of groups of nodes reg.
Fragment 7 has defined a node template bina and has been used for facilitating to node definition.This template has been described a dyadic operation.
Fragment 8 has defined a node lbina on the basis of node template, the logical operation of expression binary.
Fragment 9 has defined from the rhs territory of node logic to the limit of node lbina.
Fragment 10 has defined 3 dyadic symbols.
Fragment 11 has defined a groups of nodes lop and has been used for putting in order the node of fragment 10 definition.
Fragment 12 has defined from the op territory of node lbina to the limit of groups of nodes lop.
Fragment 13 is pointed to groups of nodes reg with r1 territory and the r2 territory of node lbina.
Fragment 14 defined in a similar fashion arithmetic instruction+,-, *.
Show to Fig. 2 example the internal logical structure of instruction set architecture.
The figure of table 3 instruction set describes
Also comprising group and class in the figure descriptive language of the present invention facilitates for the instruction set architecture modeling.
The place that figure descriptive language of the present invention is different from common ADL is:
1. it regards instruction set a kind of programming language of low level as, rather than the serializing of all instructions is enumerated.
2. in defined instruction, constitute a complete instruction by some instruction fragments.
3. language inside is with the logical organization of the form organization instruction that schemes.
Behind the figure descriptive model that obtains the processor instruction set architecture, scale-of-two instrument maker generates scale-of-two instruments such as assembler, disassembler and linker according to the associated description in the model.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; be understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
- One kind based on the figure descriptive language with scale-of-two instrument generation method, it is characterized in that, comprise the steps:Step S1: use figure descriptive language is described the instruction set of target processor, obtains the instruction set model;Step S2: use the instruction set model compiler that the instruction set model is compiled, obtain the scale-of-two instrument of processor.
- 2. as claimed in claim 1 based on the figure descriptive language with scale-of-two instrument generation method, it is characterized in that described step S2 comprises:Step S2.1: model compiler is carried out morphology and grammatical analysis to the instruction set model, makes up the instruction set cut-away view, the relational structure between portrayal instruction and the instruction fragment;Step S2.2: model compiler is collected the instruction syntax definition on the basis of instruction set cut-away view, merge into unified instruction set syntactic definition then.
- 3. as claimed in claim 2 based on the figure descriptive language with scale-of-two instrument generation method, it is characterized in that, described step S2 also comprises step S2.3: in step S2.2, model compiler is collected order number information on the basis of instruction set cut-away view, merge into unified instruction set encoding mode then.
- 4. as claimed in claim 3 based on the figure descriptive language with scale-of-two instrument generation method, it is characterized in that described step S2 also comprises step S2.5: the instruction set encoding information that obtains according to step S2.3 generates instruction set encoding device and demoder.
- 5. as claimed in claim 2 based on the figure descriptive language with scale-of-two instrument generation method, it is characterized in that described step S2 also comprises step S2.4: the instruction set syntactic definition that obtains according to step S2.2 generates instruction set syntax analyzer and printer.
- 6. as claimed in claim 2 based on the figure descriptive language with scale-of-two instrument generation method, it is characterized in that described step S2 also comprises step S2.6: instruction set syntax analyzer and scrambler merge and constitute the instruction set assembler; Instruction set demoder and printer merge formation instruction set disassembler.
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Cited By (3)
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| CN106055343A (en) * | 2016-06-22 | 2016-10-26 | 华东师范大学 | Program evolution model-based object code reverse engineering system |
| CN106126225A (en) * | 2016-06-22 | 2016-11-16 | 华东师范大学 | A kind of object code reverse engineering approach based on program evolution model |
| CN111512307A (en) * | 2017-12-20 | 2020-08-07 | 皇家飞利浦有限公司 | Compiling apparatus and method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106055343A (en) * | 2016-06-22 | 2016-10-26 | 华东师范大学 | Program evolution model-based object code reverse engineering system |
| CN106126225A (en) * | 2016-06-22 | 2016-11-16 | 华东师范大学 | A kind of object code reverse engineering approach based on program evolution model |
| CN106055343B (en) * | 2016-06-22 | 2019-01-18 | 华东师范大学 | A kind of object code reverse-engineering system based on program evolution model |
| CN106126225B (en) * | 2016-06-22 | 2019-02-12 | 华东师范大学 | A kind of object code reverse engineering approach based on program evolution model |
| CN111512307A (en) * | 2017-12-20 | 2020-08-07 | 皇家飞利浦有限公司 | Compiling apparatus and method |
| CN111512307B (en) * | 2017-12-20 | 2023-10-13 | 皇家飞利浦有限公司 | Compiling apparatus and method |
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Application publication date: 20130724 |