CN103216547B - Pneumatic clutch anti-slip protective system - Google Patents
Pneumatic clutch anti-slip protective system Download PDFInfo
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- CN103216547B CN103216547B CN201310163970.9A CN201310163970A CN103216547B CN 103216547 B CN103216547 B CN 103216547B CN 201310163970 A CN201310163970 A CN 201310163970A CN 103216547 B CN103216547 B CN 103216547B
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Abstract
The invention relates to a pneumatic clutch anti-slip protective system. The pneumatic clutch anti-slip protective system comprises a main rotating speed sensor, an auxiliary driven rotating speed sensor used for detecting the rotating speed of a driven wheel of a clutch, and a pressure sensor used for detecting pressure values corresponding to air source pressure. The main rotating speed sensor is connected with a first counter circuit through a first signal processing circuit, the auxiliary rotating speed sensor is connected with a second counter circuit through a second signal processing circuit, and the pressure sensor is connected with a logical or control circuit through a third signal processing circuit. An output end of the first counter circuit is connected with the second counter circuit and a logic comparison circuit, the second counter circuit is connected with the logic comparison circuit through a rotating difference gear selecting circuit, an output end of the logic comparison circuit is connected with the logical or control circuit, and the logic or control circuit is connected with a switch circuit. The pneumatic clutch anti-slip protective system is compact in structure, can effectively protect a pneumatic clutch, prolongs service life of the pneumatic clutch, and is safe and reliable.
Description
Technical field
The present invention relates to a kind of control system, especially a kind of pneumatic clutch anti-slip protective system, belongs to the technical field of Clutch Control.
Background technology
Clutch is mechanically common mechanism, and its function whether exporting from incompatible control mechanokinetic mainly by friction plate, can be divided into hand-operated lever-type, hydrodynamic and pneumatic type by the form of the axial force acted on friction plate usually.Pneumatic clutch be exactly utilize fluid by vapour, utilize compressed air to realize friction plate as the mode of power axial engagement be separated.
Pneumatic clutch there will be skidding when transshipping and using, and clutch friction part now can be caused to generate heat and damage, cause whole transmission system to be paralysed.
Summary of the invention
The object of the invention is to the shortcoming for the easy pneumatic clutch damaged that skids of pneumatic clutch overload; a kind of pneumatic clutch anti-slip protective system is provided; its compact conformation; can effectively protect clutch, extend the service life of pneumatic clutch, safe and reliable; friction clutch can be used as overload-release clutch; adjustable and the accurate control of nominal torque can be realized by this system, lose efficacy after also preventing overload-release clutch from skidding for a long time, extend the life-span of overload-release clutch.
According to technical scheme provided by the invention, described pneumatic clutch anti-slip protective system, comprise the main speed probe for detecting clutch driving wheel rotating speed, for detect clutch secondary speed from speed probe and the baroceptor for detecting bleed pressure corresponding pressure value; Described main speed probe is connected with the first counter circuit by the first signal conditioning circuit, be connected with the second counter circuit from speed probe by secondary signal modulate circuit, baroceptor is connected with logic OR control circuit by the 3rd signal conditioning circuit; The output of the first counter circuit is connected with the second counter circuit and logic comparator circuit, second counter circuit is connected with logic comparator circuit by slip gear selection circuit, and the carry signal of the first counter is as the clearing reset signal of the second counter, the output of described logic comparator circuit is connected with logic OR control circuit, and logic OR control circuit is connected with on-off circuit;
The main tach signal that first counter circuit detects according to main speed probe obtains the first counting accumulated value to the driving wheel rotational speed counting of clutch is cumulative; second counter circuit obtains second counting accumulated value from tach signal to the secondary speed of clutch counting is cumulative according to what detect from speed probe; when the first counter counts spill-over goes out; second counting accumulated value and setting value are carried out detection and judge by logic comparator circuit; when the second counting accumulated value is less than setting value, logic comparator circuit exports slip protection signal transmission to logic OR control circuit.By introducing the setting value that slip gear selection circuit can set logic comparator circuit between the second counter circuit and logic comparator circuit, dissimilar to adapt to, the pneumatic clutch of different operating state;
3rd signal conditioning circuit receives the bleed pressure value that baroceptor detects, when 3rd signal conditioning circuit determines whether as under-voltage condition according to the bleed pressure value of described detection, when 3rd signal conditioning circuit is defined as under-voltage condition according to the bleed pressure value of described detection, the 3rd signal conditioning circuit exports under-voltage protection signal to logic OR control circuit;
Logic OR control circuit to on-off circuit output protection control signal, makes by on-off circuit the closed electromagnetic valve controlling bleed pressure break-make in pneumatic clutch according to described slip guard signal or under-voltage protection signal.
Described first signal conditioning circuit, secondary signal modulate circuit and the 3rd signal conditioning circuit are all connected with power module by starting delay circuit, described on-off circuit comprises the second relay and the 3rd relay, the coil of the 3rd relay is connected with power module, and the coil of the second relay is connected with the output of logic OR control circuit.
Described logic comparator circuit is connected with the 3rd counter circuit, and described 3rd counter circuit is connected with logic OR control circuit by anti-interference selection of times circuit.Work as slipping of clutch; logic comparator circuit exports slip guard signal; this signal will make the 3rd counter circuit count; when this signal sustainable existence will make the 3rd counter circuit constantly count; finally when the quantity Matching of count value and anti-interference selection of times circuit configuration; anti-interference selection of times circuit exports anti-interference slip guard signal to logic OR control circuit; if the 3rd rolling counters forward is counting interrupt before reaching anti-interference selection of times circuit configuration value; then the 3rd counter will be cleared, and avoid the disturbance that the factors such as the fluctuation of load cause.Logic OR control circuit according to anti-interference slip guard signal or under-voltage protection signal to on-off circuit output protection control signal.
Described logic OR control circuit is connected with the 3rd counter circuit; logic OR control circuit while on-off circuit output protection control signal to the 3rd counter circuit output action locking signal, utilize described action locking signal to avoid the clearing of the 3rd counter circuit under logic comparator circuit exports the effect of slip guard signal.
Described first signal conditioning circuit comprises the first triode, the collector terminal of described first triode is connected with power supply VCC, the base terminal of the first triode is connected with one end of one end of the first resistance and the second resistance, the other end of the first resistance is connected with the other end of the second resistance by the 4th electric capacity, and one end ground connection that the second resistance is connected with the 4th electric capacity; The emitter terminal of the first triode and one end of the 3rd resistance and the first input end of the second NAND gate and the second input are connected, the other end ground connection of the 3rd resistance; First input end and second output of the output of the second NAND gate and the first input end of the first NAND gate, the 3rd NAND gate are connected, the output of the 3rd NAND gate is connected with the first input end of the 4th NAND gate, second input of the 4th NAND gate is connected with the output of the first NAND gate, the output of the 4th NAND gate is connected with the second input of the first NAND gate, and the output of the first NAND gate is connected with the first counter circuit.
Described secondary signal modulate circuit comprises the second triode, the collector terminal of described second triode is connected with power supply VCC, the base terminal of the second triode is connected with one end of one end of the 4th resistance and the 5th resistance, the other end of the 4th resistance is connected with the other end of the 5th resistance by the 5th electric capacity, one end ground connection that the 5th resistance is connected with the 5th electric capacity; The emitter terminal of the second triode is connected with the second input with the first input end of one end of the 6th resistance and the 6th NAND gate, the other end ground connection of the 6th resistance; First input end and second input of the output of the 6th NAND gate and the first input end of the 5th NAND gate, the 7th NAND gate are connected, the output of the 7th NAND gate is connected with the first input end of the 8th NAND gate, second input of the 8th NAND gate is connected with the output of the 5th NAND gate, the output of the 8th NAND gate is connected with the second input of the 5th NAND gate, and the output of the 5th NAND gate is connected with the second counter circuit.
Described starting delay circuit comprises time-delay relay, one end ground connection of described time-delay relay coil, the other end of time-delay relay coil is connected by one end of the moving contact of the tenth resistance and time-delay relay, fuse, one end of the 100 resistance and the cathode terminal of the first diode, the other end of fuse is connected with power module, the other end of the 100 resistance is connected with one end of the 3rd relay coil, the other end of the 3rd relay is connected with the anode tap of the first diode, and the anode tap ground connection of the first diode; The input of one end voltage-stablizer of time-delay relay first static contact connects, and the input of voltage-stablizer is connected with the earth terminal of voltage-stablizer by the first electric capacity, the earth terminal ground connection of voltage-stablizer, and the two ends of the first electric capacity are parallel with the 6th electric capacity; One end of the output of voltage-stablizer and the anode tap of the first light emitting diode and the second electric capacity and being connected, the other end ground connection of the second electric capacity, the two ends of the second electric capacity are parallel with the 3rd electric capacity, and the cathode terminal of the first light emitting diode is by the 20 resistance eutral grounding, and the output of voltage-stablizer obtains VCC voltage.
First counter circuit comprises the first counter, described first counter adopts 74LS161 counter, the Q0 end of described first counter, Q1 holds, Q2 holds, Q3 end and TC end are all connected with the input of the first nor gate, the output of the first nor gate and the first input end of the 13 NAND gate, second input connects, and the output of the first nor gate is connected with the anode tap of the second light emitting diode, the cathode terminal of the second light emitting diode is by the 7th resistance eutral grounding, the output of the 13 NAND gate exports MR1 signal, the TC end of the first timer exports MR3 signal, CEP end and the CET end of the first counter are connected with MR5 signal, the CLK end of the first counter is connected with the output of the first signal conditioning circuit, the PE end of the first counter is connected with power supply VCC, the MR end of the first counter is connected with MR2 signal.
Described second counter circuit comprises the second counter, described second counter adopts 74LS161 counter, the Q0 end of described second counter, Q1 end, Q2 end, Q3 hold and TC end is connected with the input of the second nor gate respectively, second nor gate is connected with the anode tap of the 3rd light emitting diode, and the cathode terminal of the 3rd light emitting diode is by the 8th diode ground connection, CEP end and the CET end of the second counter are connected with MR5 signal, the CLK end of the second counter is connected with secondary signal modulate circuit, the PE end of the second counter is connected with power supply VCC, the MR end of the second counter is connected with MR1 signal, the TC end of the second counter is connected with the first input end of the tenth NAND gate and the second input respectively, the output of the tenth NAND gate exports MR2 signal, the Q1 end of the second counter is connected with the first input end of the 11 NAND gate, second input of the 11 NAND gate is connected with the output of the 12 NAND gate, the output of the 11 NAND gate is connected with slip gear selection circuit, described slip gear selection circuit comprises jumper switch, the output of the 11 NAND gate is connected with the first input end of jumper switch, the Q2 end of the second counter is connected with the first input end of the 9th NAND gate, second input of the 9th NAND gate is held with the Q3 of the second counter and is connected, the output of the 9th NAND gate is connected with the second input of the first input end of the 12 NAND gate, the second input and jumper switch, the Q3 end of the second counter is also connected with the first input end of the 16 NAND gate and the second input, and the output of the 16 NAND gate is connected with the 3rd input of jumper switch,
First input end and second input of the first output of described jumper switch, the second output and the 3rd output and the 14 NAND gate in logic comparator circuit are connected, the output of the 14 NAND gate is connected with the first input end of the 15 NAND gate, second input of the 15 NAND gate is connected with MR3 signal, and the output of the 15 NAND gate exports MR5 signal;
First output of jumper switch, the second output and the 3rd output are also connected with the first input end of the 18 NAND gate in logic comparator circuit, second input of the 18 NAND gate is connected with MR3 signal, the output of the 18 NAND gate is connected with the first input end of the 19 NAND gate and the second input, and the output of the 19 NAND gate exports MR4 signal;
Described 3rd counter circuit comprises the 3rd counter, described 3rd counter adopts 74LS161 counter, CEP end and the CET end of described 3rd counter are connected with MR5 signal, the CLK end of the 3rd counter is connected with MR4 signal, the Q0 end of the 3rd counter, Q1 holds, Q2, Q3 end and TC end are connected with anti-interference selection of times circuit, described anti-interference selection of times circuit comprises jumper switch, wherein, Q0 end is connected with the four-input terminal of jumper switch, Q1 end is connected with the 5th input of jumper switch, Q2 end is connected with the 6th input of jumper switch, Q3 end is connected with the 7th input of jumper switch, TC end is connected with the 8th input of jumper switch, 4th output of jumper switch, 5th output, 6th output, 7th output and the 8th output are all connected with the first input end of the 17 NAND gate and the second input, the output of the 17 NAND gate exports sz signal.
Described logic OR control circuit comprises the 20 NAND gate, and the first input end of described 20 NAND gate is connected with sz signal, and the second input of the 20 NAND gate is connected with the collector terminal of the 3rd triode in the 3rd signal conditioning circuit; The collector terminal of the 3rd triode is also connected with power supply VCC by the 11 resistance, the emitter terminal ground connection of the 3rd triode, the colelctor electrode of the 3rd triode is connected with one end of one end of the 9th resistance and the tenth resistance, the other end ground connection of the tenth resistance, the other end of the 9th resistance is connected with the cathode terminal of the 4th light emitting diode, and the anode tap of the 4th light emitting diode is connected with the output of baroceptor;
The output of the 20 NAND gate is connected with the base terminal of the 4th triode by the 12 resistance, the emitter terminal ground connection of the 4th triode, the collector terminal of the 4th triode is connected with the anode tap of one end of the second relay coil, the second diode and one end of the 13 resistance, the other end of the second relay coil is connected with the anode tap of the 5th light emitting diode and the cathode terminal of the second diode by the 102 resistance, the cathode terminal of the 5th light emitting diode is connected with the other end of the 13 resistance, and the cathode terminal of the second diode is also connected with power supply VCC.
Advantage of the present invention: 1), do not need to measure concrete rotating speed, in one-period, the number of revolutions of driving wheel only need be measured by main speed probe, by measuring the number of revolutions of driven pulley from speed probe, when the number of revolutions difference of driving wheel and driven pulley exceed set limit time, automatic disconnection electromagnetic valve, prevents clutch damage.2), the cycle is not depend on the time, but rotate 16 circles for one-period with driving wheel, and the strict guarantee corresponding relation of number of revolutions difference and speed discrepancy, makes number of revolutions difference just represent speed discrepancy.3), when the air pressure that baroceptor detects is lower than setting value, directly excises air pump by disconnecting magnetic valve, preventing clutch damage.4), by circuit wire jumper, realize different setting of adjusting speed discrepancy protection, adapt to dissimilar load request, compact conformation.5), by circuit wire jumper, realize the selection of multiple antijamming capability, adapt to different working condition requirement, compact conformation.6), the present invention adopts pure circuit to build, and do not adopt single-chip microcomputer etc. to comprise the computing chip of cpu, and therefore its circuit is simple, and antijamming capability is strong, and caloric value is low.Therefore the present invention can effectively protect pneumatic clutch, extends service life of pneumatic clutch, economical and reliable.
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present invention.
Fig. 2 is the circuit theory diagrams comprising the first signal conditioning circuit, secondary signal modulate circuit and the first counter circuit part in Fig. 1 of the present invention.
Fig. 3 is the circuit theory diagrams comprising the second counter circuit, logic comparator circuit, slip gear selection circuit, anti-interference selection of times circuit and logic OR control circuit part in Fig. 1 of the present invention.
Detailed description of the invention
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Figure 1: in order to realize controling effectively to the skidding of pneumatic clutch, namely between driving wheel and driven pulley, speed discrepancy is had at pneumatic clutch, or bleed pressure is protected pneumatic clutch when there is under-voltage condition, avoid the damage of pneumatic clutch, the present invention includes the main speed probe for detecting clutch driving wheel rotating speed, for detect clutch secondary speed from speed probe and the baroceptor for detecting bleed pressure corresponding pressure value; Described main speed probe is connected with the first counter circuit by the first signal conditioning circuit, be connected with the second counter circuit from speed probe by secondary signal modulate circuit, baroceptor is connected with logic OR control circuit by the 3rd signal conditioning circuit; The output of the first counter circuit is connected with the second counter circuit and logic comparator circuit, second counter circuit is connected with logic comparator circuit by slip gear selection circuit, and the carry signal of the first counter is as the clearing reset signal of the second counter, the output of described logic comparator circuit is connected with logic OR control circuit, and logic OR control circuit is connected with on-off circuit;
The main tach signal that first counter circuit detects according to main speed probe obtains the first counting accumulated value to the driving wheel rotational speed counting of clutch is cumulative, and the second counter circuit obtains the second counting accumulated value according to the secondary speed counting of the main tach signal detected from speed probe to clutch is cumulative.By slip gear selection circuit, logic comparator circuit to the first counter circuit export first counting accumulated value and and the second counter circuit export second counting accumulated value compare, when the first counter circuit meter spill-over goes out, second counting accumulated value and setting value are carried out detection and judge by logic comparator circuit, when the second count value is greater than setting value, system is normal, protection is failure to actuate, when the second count value is less than setting value, system is skidded, protection act, the slip guard signal of whether action is protected in the expression that logic comparator circuit exports, slip guard signal is exported to logic OR control circuit by the 3rd counter circuit and anti-interference selection of times circuit,
3rd signal conditioning circuit receives the bleed pressure value that baroceptor detects, and when the 3rd signal conditioning circuit is defined as under-voltage condition according to the bleed pressure value of described detection, the 3rd signal conditioning circuit exports under-voltage protection signal to logic OR control circuit;
Logic OR control circuit to on-off circuit output protection control signal, makes by on-off circuit the closed electromagnetic valve controlling bleed pressure break-make in pneumatic clutch according to described slip guard signal or under-voltage protection signal.
Particularly, main speed probe and be arranged on the medial plane of clutch driving wheel and secondary part respectively from speed probe inductive magnetic steel, and the induced magnet of described correspondence and main speed probe, position from speed probe, must in same in the heart, spacing is no more than 12mm.Main speed probe and be fixed on the frame of pneumatic clutch by sensor stand from speed probe, corresponding with inductive magnetic steel.Baroceptor adopts switching mode detecting sensor.
The driving wheel rotating speed of main speed probe to pneumatic clutch detects, and the driven pulley of secondary speed sensor to pneumatic clutch detects.In order to carry out starting protection to pneumatic clutch; in the embodiment of the present invention; first signal conditioning circuit, secondary signal modulate circuit and the 3rd signal conditioning circuit are all connected with power module by starting delay circuit; power module is connected with external power source by gauge tap, and the alternating current of outside 220V can be converted to 12V direct current by power module.Starting delay circuit comprises time-delay relay RLY1, carries out delayed startup by time-delay relay RLY1.Meanwhile, in the embodiment of the present invention, utilize voltage-stablizer U0 that 12V direct current is converted to 5V voltage, for subsequent conditioning circuit chip uses.Described on-off circuit comprises the second relay R LY2 and the 3rd relay R LY3, the coil of the 3rd relay R LY3 is directly connected with power module, and the coil of the second relay R LY2 controls the break-make between itself and power module by the output end signal of logic OR control circuit.
In order to avoid the speed discrepancy signal disturbance caused due to load disturbance, described logic comparator circuit is connected with the 3rd counter circuit, described 3rd counter circuit is connected with logic OR control circuit by anti-interference selection of times circuit, work as slipping of clutch, logic comparator circuit represents the slip guard signal of protection act by exporting, described slip guard signal will make the 3rd counter circuit count, when described slip guard signal sustainable existence will make the 3rd counter circuit constantly count, finally when the quantity Matching of count value and anti-interference selection of times circuit configuration, anti-interference selection of times circuit exports anti-interference slip guard signal to logic OR control circuit, if the 3rd rolling counters forward is counting interrupt before reaching anti-interference selection of times circuit configuration value, then the 3rd counter will be cleared, avoid the disturbance that the factors such as the fluctuation of load cause.Logic OR control circuit according to anti-interference slip guard signal or under-voltage protection signal to on-off circuit output protection control signal.
Described logic OR control circuit is connected with the 3rd counter circuit; logic OR control circuit while on-off circuit output protection control signal to the 3rd counter circuit output action locking signal, utilize described action locking signal to avoid the clearing of the 3rd counter circuit under logic comparator circuit exports the effect of slip guard signal.In the embodiment of the present invention, starting delay circuit, first signal conditioning circuit, secondary signal modulate circuit, 3rd signal conditioning circuit, first counter circuit, second counter circuit, slip gear selection circuit, logic comparator circuit, 3rd counter circuit, anti-interference selection of times circuit, logic OR control circuit and on-off circuit are positioned on a circuit board, 1 end pin of circuit board, 2 end pin are used for the connection with power module, 3 end pin, 4 end pin and 5 end pin are used for the connection with main speed probe, 6 end pin, 7 end pin and 8 end pin are used for and the connection from speed probe, 9 end pin, 10 end pin are used for the connection with baroceptor, 12 end pin, 13 end pin are used for the connection with external electromagnetic valve.
As shown in Figures 2 and 3: described starting delay circuit comprises time-delay relay RLY1, one end ground connection of described time-delay relay RLY1 coil, the other end of time-delay relay RLY1 coil passes through the moving contact of the tenth resistance R10 and time-delay relay RLY1, one end of fuse F1, one end of 100 resistance R100 and the cathode terminal of the first diode D1 connect, the other end of fuse F1 is connected with power module, the other end of the 100 resistance R10 is connected with one end of the 3rd relay R LY3 coil, the other end of the 3rd relay R LY3 is connected with the anode tap of the first diode D1, and the anode tap ground connection of the first diode D1, the input of one end voltage-stablizer U0 of time-delay relay RLY1 first static contact connects, and the input of voltage-stablizer U0 is connected with the earth terminal of voltage-stablizer U0 by the first electric capacity C1, the earth terminal ground connection of voltage-stablizer U0, and the two ends of the first electric capacity C1 are parallel with the 6th electric capacity C0, one end of the output of voltage-stablizer U0 and the anode tap of the first LED 1 and the second electric capacity C2 and being connected, the other end ground connection of the second electric capacity C2, the two ends of the second electric capacity C2 are parallel with the 3rd electric capacity C3, the cathode terminal of the first LED 1 is by the 20 resistance R0 ground connection, and the output of voltage-stablizer U0 obtains VCC voltage.
Wherein, voltage-stablizer U0 adopts 7805 chips, and the direct current of 12V is converted to the direct current of 5V by voltage-stablizer U0, the direct current of described 5V as the operating voltage of subsequent conditioning circuit chip, i.e. VCC voltage.A static contact of the 3rd relay R LY3, as output, is connected with 12 ends in Fig. 1, and the moving contact of the 3rd relay R LY3 is connected with MR7 signal.Joint I1 is the joint be connected with power module.After power module powers on, after the time-delay relay RLY1 delay adjustments time, power module provides the operating voltage of subsequent conditioning circuit by voltage-stablizer U0, realizes the object of delayed firing.
Described first signal conditioning circuit comprises the first triode VT1, the collector terminal of described first triode VT1 is connected with power supply VCC, the base terminal of the first triode VT1 is connected with one end of one end of the first resistance R1 and the second resistance R2, the other end of the first resistance R1 is connected with the other end of the second resistance R2 by the 4th electric capacity C4, and one end ground connection that the second resistance R2 is connected with the 4th electric capacity C4; The emitter terminal of the first triode VT1 and one end of the 3rd resistance R3 and the first input end of the second NAND gate U1B and the second input are connected, the other end ground connection of the 3rd resistance R3; First input end and second output of the output of the second NAND gate U1B and the first input end of the first NAND gate U1A, the 3rd NAND gate U1C are connected, the output of the 3rd NAND gate U1C is connected with the first input end of the 4th NAND gate U1D, second input of the 4th NAND gate U1D is connected with the output of the first NAND gate U1A, the output of the 4th NAND gate U1D is connected with second input of the first NAND gate U1A, and the output of the first NAND gate U1A is connected with the first counter circuit.
Wherein, SI1 is the joint be connected with main speed probe, and the first signal conditioning circuit have employed electric capacity and digital circuit double-smoothing mode, ensure that the accuracy read main speed probe output signal.
Described secondary signal modulate circuit comprises the second triode VT2, the collector terminal of described second triode VT2 is connected with power supply VCC, the base terminal of the second triode VT2 is connected with one end of one end of the 4th resistance R4 and the 5th resistance R5, the other end of the 4th resistance R4 is connected with the other end of the 5th resistance R5 by the 5th electric capacity C5, one end ground connection that the 5th resistance R5 is connected with the 5th electric capacity C5; The emitter terminal of the second triode VT2 is connected with the second input with the first input end of one end of the 6th resistance R6 and the 6th NAND gate U2B, the other end ground connection of the 6th resistance R6; First input end and second input of the output of the 6th NAND gate U2B and the first input end of the 5th NAND gate U2A, the 7th NAND gate U2C are connected, the output of the 7th NAND gate U2C is connected with the first input end of the 8th NAND gate U2D, second input of the 8th NAND gate U2D is connected with the output of the 5th NAND gate U2A, the output of the 8th NAND gate U2D is connected with second input of the 5th NAND gate U2A, and the output of the 5th NAND gate U2A is connected with the second counter circuit.
Wherein, SI2 is the joint be connected with from speed probe, and the effect that secondary signal modulate circuit is identical with the first signal conditioning circuit effect and similar implementation, guarantee the accuracy to reading from signals of rotational speed sensor; 5th NAND gate U2A exports SIGB signal, and described SIGB signal is connected with the second counter circuit.
First counter circuit comprises the first counter U3, described first counter U3 adopts 74LS161 counter, the Q0 end of described first counter U3, Q1 holds, Q2 holds, Q3 end and TC end are all connected with the input of the first nor gate U6A, the output of the first nor gate U6A and the first input end of the 13 NAND gate U8A, second input connects, and the output of the first nor gate U6A is connected with the anode tap of the second LED 2, the cathode terminal of the second LED 2 is by the 7th resistance R7 ground connection, the output of the 13 NAND gate U8A exports MR1 signal, the TC end of the first timer U3 exports MR3 signal, CEP end and the CET end of the first counter U3 are connected with MR5 signal, the CLK end of the first counter U3 is connected with the output of the first signal conditioning circuit, the PE end of the first counter U3 is connected with power supply VCC, the MR end of the first counter U3 is connected with MR2 signal.
Wherein, the output of the first NAND gate U1A is held with the CLK of the first counter U3 and is connected, thus the first counter U3 processes the main tach signal obtaining correspondence according to the detection signal of the output of the first signal conditioning circuit to main speed probe; Described MR2 signal and MR5 signal export by follow-up circuit, for controlling the duty of the first counter U3.
Described second counter circuit comprises the second counter U4, described second counter U4 adopts 74LS161 counter, the Q0 end of described second counter U4, Q1 end, Q2 end, Q3 hold and TC end is connected with the input of the second nor gate U6B respectively, second nor gate U6B is connected with the anode tap of the 3rd LED 3, and the cathode terminal of the 3rd LED 3 is by the 8th diode R8 ground connection, CEP end and the CET end of the second counter U4 are connected with MR5 signal, the CLK end of the second counter U4 is connected with secondary signal modulate circuit, the PE end of the second counter U4 is connected with power supply VCC, the MR end of the second counter U4 is connected with MR1 signal, the TC end of the second counter U4 is connected with the first input end of the tenth NAND gate U7B and the second input respectively, the output of the tenth NAND gate U7B exports MR2 signal, the Q1 end of the second counter U4 is connected with the first input end of the 11 NAND gate U7C, second input of the 11 NAND gate U7C is connected with the output of the 12 NAND gate U7D, the output of the 11 NAND gate U7C is connected with slip gear selection circuit, described slip gear selection circuit comprises jumper switch S1, the output of the 11 NAND gate U7C is connected with the first input end of jumper switch S1, the Q2 end of the second counter U4 is connected with the first input end of the 9th NAND gate U7A, second input of the 9th NAND gate U7A is held with the Q3 of the second counter U4 and is connected, the output of the 9th NAND gate U7A is connected with second input of the first input end of the 12 NAND gate U7D, the second input and jumper switch S1, the Q3 end of the second counter U4 is also connected with the first input end of the 16 NAND gate U8D and the second input, and the output of the 16 NAND gate U8D is connected with the 3rd input of jumper switch S1,
First input end and second input of first output of described jumper switch S1, the second output and the 3rd output and the 14 NAND gate U8B in logic comparator circuit are connected, the output of the 14 NAND gate U8B is connected with the first input end of the 15 NAND gate U8C, second input of the 15 NAND gate U8C is connected with MR3 signal, and the output of the 15 NAND gate U8C exports MR5 signal;
First output of jumper switch S1, the second output and the 3rd output are also connected with the first input end of the 18 NAND gate U9B in logic comparator circuit, second input of the 18 NAND gate U9B is connected with MR3 signal, the output of the 18 NAND gate U9B is connected with the first input end of the 19 NAND gate U9C and the second input, and the output of the 19 NAND gate U9C exports MR4 signal;
Described 3rd counter circuit comprises the 3rd counter U5, described 3rd counter U5 adopts 74LS161 counter, CEP end and the CET end of described 3rd counter U5 are connected with MR5 signal, the CLK end of the 3rd counter U5 is connected with MR4 signal, the Q0 end of the 3rd counter U5, Q1 holds, Q2, Q3 end and TC end are connected with anti-interference selection of times circuit, described anti-interference selection of times circuit comprises jumper switch S1, wherein, Q0 end is connected with the four-input terminal of jumper switch S1, Q1 end is connected with the 5th input of jumper switch S1, Q2 end is connected with the 6th input of jumper switch S1, Q3 end is connected with the 7th input of jumper switch S1, TC end is connected with the 8th input of jumper switch S1, 4th output of jumper switch S1, 5th output, 6th output, 7th output and the 8th output are all connected with the first input end of the 17 NAND gate U9A and the second input, the output of the 17 NAND gate U9A exports sz signal.In the embodiment of the present invention, MR5 is locking signal, and SZ and MR6 is identical, and logic OR control circuit is made up of the 3rd triode VT3 and the 17 NAND gate U9A and the 20 NAND gate U9D.
Wherein, jumper switch S1 adopts SW DIP-8, in the embodiment of the present invention, slip gear selection circuit and anti-interference selection of times circuit are all by the jumper switch S1(embodiment of the present invention, jumper switch S1 is a jumper wire plug, in order to circuit board making is convenient, selected SW DIP-8 encapsulate) difference end pin realize selecting input to export with selection.In the embodiment of the present invention, the output of gear Selection utilization second counter U4; Wherein, when first input end and the first output connection (1 end in first input end corresponding diagram of jumper switch S1,16 ends in first output corresponding diagram), slip gear now between driving wheel and driven pulley is 87.5%, it utilizes the output Q1Q2Q3 of the second counter U4 as judging, when the Q1 output of the second counter U4, Q2 output, Q3 output are zero, the output of the second counter U4 is 1.
When the second input and the second output connection (2 ends in the second output corresponding diagram of jumper switch S1,15 ends in second output corresponding diagram), the slip gear that now jumper switch S1 exports is 72.5%, it utilizes the output Q2Q3 of the second counter U4 as judging, when the Q2 output of the second counter U4, Q3 output are zero, the output of the second counter U4 is 1.
When the 3rd input of jumper switch S1 and the 3rd output are connected, (the 3rd input is corresponding with 3 ends in figure, 3rd output is connected with 14 ends in figure), the slip gear that now jumper switch S1 exports is 50%, it utilizes the output Q3 of the second counter U4 as judging, when the Q3 output of the second counter U4 is zero, the output of the second counter is 1.
Note: can not simultaneously connect for above-mentioned three groups, when chosen output is 1, and when the first counter U3 overflows (or reset), then represents this action of protection.When the first counter U3 overflows (or reset), and if that group output chosen in above-mentioned three groups is 0, then protection is failure to actuate.
3rd counter U5 selects with helping to realize anti-interference gear.Q0 ~ TC pin of the 3rd counter U5 connects (four-input terminal ~ the 8th input is corresponding with 4 ~ 8 ends respectively) with the four-input terminal of jumper switch S1 ~ the 8th input end, four-input terminal (4 ends in four output corresponding diagram corresponding to the 4th output, 13 ends in 4th output corresponding diagram), 5th input is corresponding with the 5th output, and (the 5th input is corresponding with 5 ends in figure, 5th output is corresponding with 12 ends in figure), 6th input is corresponding with the 6th output, and (the 6th input is corresponding with 6 ends in figure, 6th output is corresponding with 11 ends in figure), 7th input is corresponding with the 7th input, and (the 7th input is corresponding with 7 ends in figure, 7th output is corresponding with 10 ends in figure), 8th input is corresponding with the 8th output, and (the 8th input is corresponding with 8 ends in figure, 8th output is corresponding with 9 ends in figure), whenever also can only one group of connection.
Described logic OR control circuit comprises the 20 NAND gate U9D, and the first input end of described 20 NAND gate U9D is connected with sz signal, and second input of the 20 NAND gate U9D is connected with the collector terminal of the 3rd triode VT3 in the 3rd signal conditioning circuit; The collector terminal of the 3rd triode VT3 is also connected with power supply VCC by the 11 resistance R11, the emitter terminal ground connection of the 3rd triode VT3, the colelctor electrode of the 3rd triode VT3 is connected with one end of one end of the 9th resistance R9 and the tenth resistance R10, the other end ground connection of the tenth resistance R10, the other end of the 9th resistance R9 is connected with the cathode terminal of the 4th LED 4, and the anode tap of the 4th LED 4 is connected with the output of baroceptor;
The output of the 20 NAND gate U9D is connected with the base terminal of the 4th triode VT4 by the 12 resistance R12, the emitter terminal ground connection of the 4th triode VT4, the collector terminal of the 4th triode VT4 and one end of the second relay R LY2 coil, the anode tap of the second diode D2 and one end of the 13 resistance R13 connect, the other end of the second relay R LY2 coil is connected with the anode tap of the 5th LED 5 and the cathode terminal of the second diode D2 by the 102 resistance R102, the cathode terminal of the 5th LED 5 is connected with the other end of the 13 resistance R13, the cathode terminal of the second diode D2 is also connected with power supply VCC.
Wherein, 20 NAND gate U9D receives the air pressure signal that sz signal and baroceptor export through the 3rd signal conditioning circuit simultaneously, when there is the under-voltage or anti-interference slip signal of air pressure, all realize the adjustment to the second relay R LY2 coil state by the 4th triode VT4, namely can realize the adjustment to the second relay R LY2 contacts status; Namely the control to magnetic valve state in pneumatic clutch can be realized.
As shown in Fig. 1 ~ Fig. 3: during work, the first counter U3 and the second counter U4 receives main speed probe and respectively from signals of rotational speed sensor.Driving wheel and driven pulley often turn around, and main speed probe just sends (also can be multiple, depend on that number installed by a magnet steel) signal, and each signal adds 1 by making corresponding counter.First counter U3 and the second counter U4 receiving driving wheel, the tach signal of driven pulley adds up simultaneously, the progressive rate of general first counter U3 can be more than or equal to the second counter U4.Expire when the first counter U4 counts (or overflow reset, it is 16 times for 74ls61, namely driving wheel turns 16 circles), judge the second counter U4 count value, when the second counter U4 value is less than setting value (represent for 50%, Q3=1 and be greater than 50% this setting value, Q3=0 represent be less than 50% this setting value), the speed discrepancy then sent between driving wheel and driven pulley transfinites signal 1, otherwise sends slip normal signal 0.This some work is realized according to the first counter circuit with through the second counter circuit output signal of slip gear selection circuit process by logic comparator circuit.
3rd counter U5 records the signal that transfinites and also helps to realize anti-interference selection of times.When transfiniting, signal occurs continuously, then the 3rd counter U5 is just cumulative, and when slip normal signal occurs, the 3rd counter U5 just resets.If the 3rd counter U5 accumulated value exceedes anti-interference number of times, protect with regard to action.When accumulated value is lower than anti-interference number of times, just wait for that the next slip signal that transfinites continues cumulative, or slip normal signal resets.Pressure sensor detects that signal also directly can make protection act.
After action; after sending to prevent protection act signal; under extreme case, (such as clutch fails to disconnect; rotating speed intermittently recovers normal) occur that slip normal signal resets the sight of the 3rd counter U5; utilize protection act signal by the 3rd counter U5 locking; i.e. the 3rd counter U5 no longer write input, and maintenance exports as fixed value is constant.
After circuit board energising, the 3rd relay R LY3 closes, and the moving contact of the 3rd relay R LY3 is connected with 12 ends.If protection is failure to actuate, the second relay R LY2 power-off, now 12 pin of circuit board and 13 pin connect, and clutch normally works.After circuit board energising, when protection act, the second relay R LY2 energising, 13 ends and 12 ends just disconnect, and now magnetic valve is in closed condition, and the pressure of source of the gas can not remake for pneumatic clutch.During circuit board power-off, the 3rd relay R LY3 and the equal power-off of the second relay R LY2, now, the connection of 13 ends and 12 ends also disconnects.
The present invention will be counted by the first counter circuit, the rotary rpm of the second counter circuit to clutch driving wheel, driven pulley, some (accompanying drawing is for 16) circle is rotated as sense cycle using driving wheel, by driven pulley rotating cycle and driving wheel in one-period being compared, the slip relation between driving wheel, driven pulley can be obtained.Utilize the 3rd counter circuit to carry out anti-interference process to slip relation, and the air pressure signal detected with baroceptor is jointly as the signal of protection system, by the air pump of relay circuit solenoidoperated cluthes.Adopt pure circuit to build, do not adopt single-chip microcomputer etc. to comprise the computing chip of cpu, circuit is simple, and antijamming capability is strong, and caloric value is low.Utilize simple wire jumper simultaneously, achieve the selection of slip gear and anti-interference number of times easily, to adapt to different loads, the requirement of different operating mode.
The present invention measures the rotating speed of driving wheel by main speed probe, by measuring the rotating speed of driven pulley from speed probe, when the speed discrepancy of driving wheel and driven pulley exceed set limit time, automatically disconnect electromagnetic valve, prevent clutch damage.When the air pressure of baroceptor detection air pump is lower than setting; directly air pump is excised by disconnecting magnetic valve; prevent clutch damage; the flexible setting of different rotating speeds difference limit value, by circuit wire jumper, realizes the setting with multiple adjustable speed discrepancy; compact conformation; can effectively protect starting clutch, extend the service life of pneumatic clutch, safe and reliable.
Claims (10)
1. a pneumatic clutch anti-slip protective system, is characterized in that: comprise the main speed probe for detecting clutch driving wheel rotating speed, for detect clutch secondary speed from speed probe and the baroceptor for detecting bleed pressure corresponding pressure value; Described main speed probe is connected with the first counter circuit by the first signal conditioning circuit, be connected with the second counter circuit from speed probe by secondary signal modulate circuit, baroceptor is connected with logic OR control circuit by the 3rd signal conditioning circuit; The output of the first counter circuit is connected with the second counter circuit and logic comparator circuit, second counter circuit is connected with logic comparator circuit by slip gear selection circuit, and the carry signal of the first counter is as the clearing reset signal of the second counter, the output of described logic comparator circuit is connected with logic OR control circuit, and logic OR control circuit is connected with on-off circuit;
The main tach signal that first counter circuit detects according to main speed probe obtains the first counting accumulated value to the driving wheel rotational speed counting of clutch is cumulative, second counter circuit obtains second counting accumulated value from tach signal to the secondary speed of clutch counting is cumulative according to what detect from speed probe, when the first counter counts spill-over goes out, second counting accumulated value and setting value are carried out detection and judge by logic comparator circuit, when the second counting accumulated value is less than setting value, logic comparator circuit exports slip protection signal transmission to logic OR control circuit;
By introducing the setting value that slip gear selection circuit can set logic comparator circuit between the second counter circuit and logic comparator circuit, dissimilar to adapt to, the pneumatic clutch of different operating state;
3rd signal conditioning circuit receives the bleed pressure value that baroceptor detects, when 3rd signal conditioning circuit determines whether as under-voltage condition according to the bleed pressure value of described detection, when 3rd signal conditioning circuit is defined as under-voltage condition according to the bleed pressure value of described detection, the 3rd signal conditioning circuit exports under-voltage protection signal to logic OR control circuit;
Logic OR control circuit to on-off circuit output protection control signal, makes by on-off circuit the closed electromagnetic valve controlling bleed pressure break-make in pneumatic clutch according to described slip guard signal or under-voltage protection signal.
2. pneumatic clutch anti-slip protective system according to claim 1; it is characterized in that: described first signal conditioning circuit, secondary signal modulate circuit and the 3rd signal conditioning circuit are all connected with power module by starting delay circuit; described on-off circuit comprises the second relay (RLY2) and the 3rd relay (RLY3); the coil of the 3rd relay (RLY3) is connected with power module, and the coil of the second relay (RLY2) is connected with the output of logic OR control circuit.
3. pneumatic clutch anti-slip protective system according to claim 1, is characterized in that: described logic comparator circuit is connected with the 3rd counter circuit, and described 3rd counter circuit is connected with logic OR control circuit by anti-interference selection of times circuit; When logic comparator circuit exports slip guard signal, described slip guard signal will make the 3rd counter circuit count, and when described slip guard signal sustainable existence will make the 3rd counter circuit constantly count, during the final quantity Matching when count value and anti-interference selection of times circuit configuration, anti-interference selection of times circuit is to logic OR control circuit output anti-interference slip guard signal;
When the 3rd counter circuit counting interrupt before counting reaches anti-interference selection of times circuit configuration value, then the 3rd counter will be cleared; Logic OR control circuit according to anti-interference slip guard signal or under-voltage protection signal to on-off circuit output protection control signal.
4. pneumatic clutch anti-slip protective system according to claim 3; it is characterized in that: described logic OR control circuit is connected with the 3rd counter circuit; logic OR control circuit while on-off circuit output protection control signal to the 3rd counter circuit output action locking signal, utilize described action locking signal to avoid the clearing of the 3rd counter circuit under logic comparator circuit exports the effect of slip guard signal.
5. pneumatic clutch anti-slip protective system according to claim 1, it is characterized in that: described first signal conditioning circuit comprises the first triode (VT1), the collector terminal of described first triode (VT1) is connected with power supply VCC, the base terminal of the first triode (VT1) is connected with one end of one end of the first resistance (R1) and the second resistance (R2), the other end of the first resistance (R1) is connected with the other end of the second resistance (R2) by the 4th electric capacity (C4), and one end ground connection that the second resistance (R2) is connected with the 4th electric capacity (C4); The emitter terminal of the first triode (VT1) and one end of the 3rd resistance (R3) and the first input end of the second NAND gate (U1B) and the second input are connected, the other end ground connection of the 3rd resistance (R3); First input end and second output of the output of the second NAND gate (U1B) and the first input end of the first NAND gate (U1A), the 3rd NAND gate (U1C) are connected, the output of the 3rd NAND gate (U1C) is connected with the first input end of the 4th NAND gate (U1D), second input of the 4th NAND gate (U1D) is connected with the output of the first NAND gate (U1A), the output of the 4th NAND gate (U1D) is connected with the second input of the first NAND gate (U1A), and the output of the first NAND gate (U1A) is connected with the first counter circuit.
6. pneumatic clutch anti-slip protective system according to claim 1, it is characterized in that: described secondary signal modulate circuit comprises the second triode (VT2), the collector terminal of described second triode (VT2) is connected with power supply VCC, the base terminal of the second triode (VT2) is connected with one end of one end of the 4th resistance (R4) and the 5th resistance (R5), the other end of the 4th resistance (R4) is connected with the other end of the 5th resistance (R5) by the 5th electric capacity (C5), one end ground connection that the 5th resistance (R5) is connected with the 5th electric capacity (C5); The emitter terminal of the second triode (VT2) is connected with the second input with the first input end of one end of the 6th resistance (R6) and the 6th NAND gate (U2B), the other end ground connection of the 6th resistance (R6); First input end and second input of the output of the 6th NAND gate (U2B) and the first input end of the 5th NAND gate (U2A), the 7th NAND gate (U2C) are connected, the output of the 7th NAND gate (U2C) is connected with the first input end of the 8th NAND gate (U2D), second input of the 8th NAND gate (U2D) is connected with the output of the 5th NAND gate (U2A), the output of the 8th NAND gate (U2D) is connected with the second input of the 5th NAND gate (U2A), and the output of the 5th NAND gate (U2A) is connected with the second counter circuit.
7. pneumatic clutch anti-slip protective system according to claim 2, it is characterized in that: described starting delay circuit comprises time-delay relay (RLY1), one end ground connection of described time-delay relay (RLY1) coil, the other end of time-delay relay (RLY1) coil is by the moving contact of the tenth resistance (R10) with time-delay relay (RLY1), one end of fuse (F1), one end of 100 resistance (R100) and the cathode terminal of the first diode (D1) connect, the other end of fuse (F1) is connected with power module, the other end of the 100 resistance (R100) is connected with one end of the 3rd relay (RLY3) coil, the other end of the 3rd relay (RLY3) is connected with the anode tap of the first diode (D1), and the anode tap ground connection of the first diode (D1), one end of time-delay relay (RLY1) first static contact is connected with the input of voltage-stablizer (U0), the input of voltage-stablizer (U0) is connected with the earth terminal of voltage-stablizer (U0) by the first electric capacity (C1), the earth terminal ground connection of voltage-stablizer (U0), the two ends of the first electric capacity (C1) are parallel with the 6th electric capacity (C0), one end of the output of voltage-stablizer (U0) and the anode tap of the first light emitting diode (LED1) and the second electric capacity (C2) and being connected, the other end ground connection of the second electric capacity (C2), the two ends of the second electric capacity (C2) are parallel with the 3rd electric capacity (C3), the cathode terminal of the first light emitting diode (LED1) is by the 20 resistance (R0) ground connection, and the output of voltage-stablizer (U0) obtains VCC voltage.
8. pneumatic clutch anti-slip protective system according to claim 4, it is characterized in that: the first counter circuit comprises the first counter (U3), described first counter (U3) adopts 74LS161 counter, the Q0 end of described first counter (U3), Q1 holds, Q2 holds, Q3 end and TC end are all connected with the input of the first nor gate (U6A), the output of the first nor gate (U6A) and the first input end of the 13 NAND gate (U8A), second input connects, and the output of the first nor gate (U6A) is connected with the anode tap of the second light emitting diode (LED2), the cathode terminal of the second light emitting diode (LED2) is by the 7th resistance (R7) ground connection, the output of the 13 NAND gate (U8A) exports MR1 signal, the TC end of the first counter (U3) exports MR3 signal, CEP end and the CET end of the first counter (U3) are connected with MR5 signal, the CLK end of the first counter (U3) is connected with the output of the first signal conditioning circuit, the PE end of the first counter (U3) is connected with power supply VCC, the MR end of the first counter (U3) is connected with MR2 signal.
9. pneumatic clutch anti-slip protective system according to claim 8, it is characterized in that: described second counter circuit comprises the second counter (U4), described second counter (U4) adopts 74LS161 counter, the Q0 end of described second counter (U4), Q1 end, Q2 end, Q3 hold and TC end is connected with the input of the second nor gate (U6B) respectively, second nor gate (U6B) is connected with the anode tap of the 3rd light emitting diode (LED3), and the cathode terminal of the 3rd light emitting diode (LED3) is by the 8th diode (R8) ground connection, CEP end and the CET end of the second counter (U4) are connected with MR5 signal, the CLK end of the second counter (U4) is connected with secondary signal modulate circuit, the PE end of the second counter (U4) is connected with power supply VCC, the MR end of the second counter (U4) is connected with MR1 signal, the TC end of the second counter (U4) is connected with the first input end of the tenth NAND gate (U7B) and the second input respectively, the output of the tenth NAND gate (U7B) exports MR2 signal, the Q1 end of the second counter (U4) is connected with the first input end of the 11 NAND gate (U7C), second input of the 11 NAND gate (U7C) is connected with the output of the 12 NAND gate (U7D), the output of the 11 NAND gate (U7C) is connected with slip gear selection circuit, described slip gear selection circuit comprises jumper switch (S1), the output of the 11 NAND gate (U7C) is connected with the first input end of jumper switch (S1), the Q2 end of the second counter (U4) is connected with the first input end of the 9th NAND gate (U7A), second input of the 9th NAND gate (U7A) is held with the Q3 of the second counter (U4) and is connected, the output of the 9th NAND gate (U7A) and the first input end of the 12 NAND gate (U7D), second input of the second input and jumper switch (S1) connects, the Q3 end of the second counter (U4) is also connected with the first input end of the 16 NAND gate (U8D) and the second input, the output of the 16 NAND gate (U8D) is connected with the 3rd input of jumper switch (S1),
First input end and second input of the first output of described jumper switch (S1), the second output and the 3rd output and the 14 NAND gate (U8B) in logic comparator circuit are connected, the output of the 14 NAND gate (U8B) is connected with the first input end of the 15 NAND gate (U8C), second input of the 15 NAND gate (U8C) is connected with MR3 signal, and the output of the 15 NAND gate (U8C) exports MR5 signal;
First output of jumper switch (S1), the second output and the 3rd output are also connected with the first input end of the 18 NAND gate (U9B) in logic comparator circuit, second input of the 18 NAND gate (U9B) is connected with MR3 signal, the output of the 18 NAND gate (U9B) is connected with the first input end of the 19 NAND gate (U9C) and the second input, and the output of the 19 NAND gate (U9C) exports MR4 signal;
Described 3rd counter circuit comprises the 3rd counter (U5), described 3rd counter (U5) adopts 74LS161 counter, CEP end and the CET end of described 3rd counter (U5) are connected with MR5 signal, the CLK end of the 3rd counter (U5) is connected with MR4 signal, the Q0 end of the 3rd counter (U5), Q1 holds, Q2, Q3 end and TC end are connected with anti-interference selection of times circuit, described anti-interference selection of times circuit comprises jumper switch (S1), wherein, Q0 end is connected with the four-input terminal of jumper switch (S1), Q1 end is connected with the 5th input of jumper switch (S1), Q2 end is connected with the 6th input of jumper switch (S1), Q3 end is connected with the 7th input of jumper switch (S1), TC end is connected with the 8th input of jumper switch (S1), 4th output of jumper switch (S1), 5th output, 6th output, 7th output and the 8th output are all connected with the first input end of the 17 NAND gate (U9A) and the second input, the output of the 17 NAND gate (U9A) exports sz signal.
10. pneumatic clutch anti-slip protective system according to claim 9, it is characterized in that: described logic OR control circuit comprises the 20 NAND gate (U9D), the first input end of described 20 NAND gate (U9D) is connected with sz signal, and the second input of the 20 NAND gate (U9D) is connected with the collector terminal of the 3rd triode (VT3) in the 3rd signal conditioning circuit; The collector terminal of the 3rd triode (VT3) is also connected with power supply VCC by the 11 resistance (R11), the emitter terminal ground connection of the 3rd triode (VT3), the colelctor electrode of the 3rd triode (VT3) is connected with one end of one end of the 9th resistance (R9) and the tenth resistance (R10), the other end ground connection of the tenth resistance (R10), the other end of the 9th resistance (R9) is connected with the cathode terminal of the 4th light emitting diode (LED4), and the anode tap of the 4th light emitting diode (LED4) is connected with the output of baroceptor;
The output of the 20 NAND gate (U9D) is connected with the base terminal of the 4th triode (VT4) by the 12 resistance (R12), the emitter terminal ground connection of the 4th triode (VT4), the collector terminal of the 4th triode (VT4) and one end of the second relay (RLY2) coil, the anode tap of the second diode (D2) and one end of the 13 resistance (R13) connect, the other end of the second relay (RLY2) coil is connected with the anode tap of the 5th light emitting diode (LED5) and the cathode terminal of the second diode (D2) by the 102 resistance (R102), the cathode terminal of the 5th light emitting diode (LED5) is connected with the other end of the 13 resistance (R13), the cathode terminal of the second diode (D2) is also connected with power supply VCC.
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|---|---|---|---|---|
| GB1341071A (en) * | 1970-01-12 | 1973-12-19 | Xerox Corp | Article stacking apparatus |
| US4023660A (en) * | 1973-09-29 | 1977-05-17 | Ferranti, Limited | Follow-up servo systems for clutches |
| CN1113194A (en) * | 1994-02-22 | 1995-12-13 | 易通公司 | Method and apparatus for robust automatic clutch control with PID regulation |
| CN1165099A (en) * | 1996-02-02 | 1997-11-19 | 易通公司 | Method and apparatus for slip mode control of automatic clutch |
| EP1093986A2 (en) * | 1999-10-18 | 2001-04-25 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Driving control apparatus for industrial vehicle |
| US7669393B2 (en) * | 2008-05-08 | 2010-03-02 | Deere & Company | Stall detection system for mower blade clutch engagement |
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2013
- 2013-05-06 CN CN201310163970.9A patent/CN103216547B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1341071A (en) * | 1970-01-12 | 1973-12-19 | Xerox Corp | Article stacking apparatus |
| US4023660A (en) * | 1973-09-29 | 1977-05-17 | Ferranti, Limited | Follow-up servo systems for clutches |
| CN1113194A (en) * | 1994-02-22 | 1995-12-13 | 易通公司 | Method and apparatus for robust automatic clutch control with PID regulation |
| CN1165099A (en) * | 1996-02-02 | 1997-11-19 | 易通公司 | Method and apparatus for slip mode control of automatic clutch |
| EP1093986A2 (en) * | 1999-10-18 | 2001-04-25 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Driving control apparatus for industrial vehicle |
| US7669393B2 (en) * | 2008-05-08 | 2010-03-02 | Deere & Company | Stall detection system for mower blade clutch engagement |
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