CN103208301B - Dosage adapt device followed by a kind of Flouride-resistani acid phesphatase memorizer - Google Patents
Dosage adapt device followed by a kind of Flouride-resistani acid phesphatase memorizer Download PDFInfo
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- CN103208301B CN103208301B CN201310098852.4A CN201310098852A CN103208301B CN 103208301 B CN103208301 B CN 103208301B CN 201310098852 A CN201310098852 A CN 201310098852A CN 103208301 B CN103208301 B CN 103208301B
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- 239000002253 acid Substances 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 43
- 230000001105 regulatory effect Effects 0.000 claims abstract description 19
- 238000001514 detection method Methods 0.000 abstract description 6
- 230000005855 radiation Effects 0.000 abstract description 5
- 238000013461 design Methods 0.000 description 7
- 230000003014 reinforcing effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003471 anti-radiation Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Abstract
The present invention is applicable to Flouride-resistani acid phesphatase memorizer, it is provided that dosage adapt device followed by a kind of Flouride-resistani acid phesphatase memorizer, including reference voltage regulating circuit, is connected with sense amplifier, adjusts the size of sense amplifier reference voltage, thus changes sense amplifier gain；Bias current adjusts circuit, is connected with described sense amplifier, adjusts the size of sense amplifier bias current；Irradiation testing circuit, for detecting the change of irradiation dose and the control signal produced being sent to described reference voltage regulating circuit and described bias current adjustment circuit.Described Flouride-resistani acid phesphatase memorizer is followed dosage adapt device and is used detection in real time and dynamic adjustment mode to reinforce memory circuitry, can be according to the irradiation dose size detected in real time, sense amplifier threshold value is adjusted correspondingly, can either ensure that circuit remains able to normally work under radiation parameter, memorizer will be caused to read error in data because of crossing adjustment again.
Description
Technical field
The invention belongs to IC design field, particularly relate to a kind of Flouride-resistani acid phesphatase memorizer and follow dosage adapt device.
Background technology
Along with the fast development of aerospace industry, memorizer is more and more extensive in the application of space industry.Meanwhile, the anti-radiation performance to memorizer it is also proposed higher requirement.The module reading sense amplifier reading is one of circuit module of most critical in memorizer, also it is most sensitive circuit unit, reading speed, the reading data reliability of memorizer is all had a major impact, the irradiation behaviour optimizing sense amplifier can improve reliability when memorizer works in cosmic space, improves the safety of spacecraft flight.In order to promote the performance of device under radiation environment, need to be designed memorizer and other electronic devices and components reinforcing.The method reinforced mainly has the means such as technique reinforcing, layout design reinforcing, circuit design reinforcing.A kind of design that can detect space total dose effect size and adjust memorizer relevant parameter is also needed on the basis of Design of Reinforcement, to make up the shortcomings and limitations that existing integrated circuit radiation hardened method exists, anti-radiation performance during improving to greatest extent.
Summary of the invention
The technical problem to be solved is to provide a kind of Flouride-resistani acid phesphatase memorizer to follow dosage adapt device, use dose measurement sensor or detector unit that irradiation dose is detected, and irradiation dose change is converted into change in voltage control signal, change according to irradiation dose, control sense amplifier the threshold value read is adjusted accordingly, thus ensure that circuit also can be read correctly data when irradiation.
The present invention is achieved in that dosage adapt device followed by a kind of Flouride-resistani acid phesphatase memorizer, including: irradiation testing circuit, sense amplifier, at least one reference voltage regulating circuit or bias current adjust circuit；
Described irradiation testing circuit is for detecting the change of irradiation dose, and the control signal produced is sent to described reference voltage regulating circuit and described bias current adjustment circuit；
Described reference voltage regulating circuit is connected with described sense amplifier, adjusts the size of sense amplifier reference voltage, thus changes sense amplifier gain, is adjusted the read threshold of sense amplifier；
Described bias current adjusts circuit and is connected with described sense amplifier, adjusts the size of sense amplifier bias current, thus is adjusted the read threshold of sense amplifier；
Described irradiation testing circuit includes that detecting threshold value different irradiation dose testing circuit 1 to irradiation dose testing circuit n, described irradiation dose testing circuit 1 to irradiation dose testing circuit n has two control signal outputs, respectively reference voltage control signal T respectively1To Tn, bias current control signal TN1To TNn；
The reference voltage of described sense amplifier, according to the reference voltage control signal received, is carried out the adjustment of respective degrees by described reference voltage regulating circuit；
The bias current of described sense amplifier, according to the bias current control signal received, is carried out the adjustment of respective degrees by described bias current adjustment circuit；
Described irradiation dose testing circuit includes: comparator, resistance R1, resistance R2, resistance R3, resistance R4, electric capacity C1, electric capacity C2, NMOS tube Q0；
One end of resistance R1 is connected with running voltage, and the other end of resistance R1 is connected in series with one end of resistance R2, the other end ground connection of resistance R2, and electric capacity C1 is connected in parallel with resistance R2；
One end of resistance R3 is connected with running voltage, the other end of resistance R3 is connected in series with one end of resistance R4, the other end ground connection of resistance R4, and electric capacity C2 is connected in parallel with resistance R4, the drain electrode of NMOS tube Q0 is connected with one end of resistance R4, the grid of NMOS tube Q0 and source ground；
Being connected in series of resistance R1 and resistance R2 is a little connected with the in-phase input end of comparator, and being connected in series of resistance R3 and resistance R4 is a little connected with the inverting input of comparator.
Further, the outfan of described comparator is divided into two circuits, and wherein a circuit exports directly as reference voltage control signal, and another circuit exports as bias current control signal after connecing a phase inverter again.
Further, described bias current adjustment circuit includes: PMOS Q01, PMOS Q02, NMOS tube Q03, NMOS tube Q04, switch SN1To SNn, current source I0, current source I1To In；
The drain electrode of described PMOS Q01 is connected with the drain electrode of described PMOS Q02, the grid of described PMOS Q01 is connected with the grid of described PMOS Q02, the grid of described PMOS Q01, the grid of described PMOS Q02 are connected with the source electrode of the drain electrode of described NMOS tube Q03, described PMOS Q01, and the source electrode of described PMOS Q02 is connected with the drain electrode of described NMOS tube Q04；
The grid of described NMOS tube Q03 adjusts the voltage input end of circuit as bias current, and the source electrode of described NMOS tube Q03 is connected with the source electrode of described NMOS tube Q04 and exports electric current Ibias, the grid of described NMOS tube Q04 adjusts the reference voltage output terminal of circuit as bias current；
Described switch SN1To SNnIt is connected in parallel, switchs SN1To SNnOne termination electric current Ibias, the other end passes through current source I1To InGround connection again, described current source I0One termination output electric current Ibias, the other end is directly grounded.
Further, described reference voltage regulating circuit includes: PMOS Q05, NMOS tube Q06, PMOS Q1 to Qn, switch S1To Sn；
The drain electrode of PMOS Q05 connects running voltage, and the grid of PMOS Q05 is connected with its source electrode, and the source electrode of PMOS Q05 is connected with the drain electrode of NMOS tube Q06；
The grid of NMOS tube Q06 drains with it and is connected, and the drain electrode of NMOS tube Q06, the source electrode of PMOS Q05 meet reference voltage Vref, the source ground of NMOS tube Q06；
The drain electrode of PMOS Q1 to Qn connects running voltage, and grid is connected with source electrode, and source electrode meets switch S1To SnOne end, switch S1To SnThe other end all be connected and access reference voltage output terminal.
Further, described reference voltage control signal T1To TnControl switch S respectively1To SnGuan Bi or disconnection.
Further, described bias current control signal TN1To TNnControl switch SN respectively1To SNnGuan Bi or disconnection.
The present invention is compared with prior art, have the beneficial effects that employing detection in real time and dynamic adjustment mode carry out radiation hardened to memory circuitry, compared with reinforcing with traditional technique and layout design, reinforcing mode in the present invention can be according to the irradiation dose size detected in real time, sense amplifier threshold value is adjusted correspondingly, when irradiation dose reduces or disappears, circuit also can adjust corresponding sense amplifier threshold value, carry out following change, can either ensure that circuit remains able to normally work under radiation parameter, memorizer will be caused to read error in data because of crossing adjustment again.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that dosage adapt device followed by the Flouride-resistani acid phesphatase memorizer of the present invention；
Fig. 2 is the circuit diagram of irradiation dose testing circuit of the present invention；
Fig. 3 is the circuit diagram that sense amplifier bias current of the present invention adjusts circuit；
Fig. 4 is the circuit diagram of sense amplifier reference voltage regulating circuit of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
As it is shown in figure 1, dosage adapt device followed by a kind of Flouride-resistani acid phesphatase memorizer, adjust circuit 104 including irradiation testing circuit 101, sense amplifier 103, an at least reference voltage regulating circuit 102 or bias current.Described irradiation testing circuit 101 is for detecting the change of irradiation dose, and the control signal produced is sent to described reference voltage regulating circuit 102 and described bias current adjustment circuit 104；Described reference voltage regulating circuit 102 is connected with described sense amplifier 103, for adjusting the size of sense amplifier 103 reference voltage, thus changes sense amplifier 103 gain, is adjusted the read threshold of sense amplifier 103；Described bias current adjusts circuit 104 and is connected with described sense amplifier 103, for adjusting the size of sense amplifier 103 bias current, thus is adjusted the read threshold of sense amplifier 103.In actual use, described reference voltage regulating circuit and described bias current adjust circuit and can individually use or be used in combination with, and adjust the most respectively when being adjusted or adjust simultaneously.
Irradiation testing circuit 101 includes the irradiation dose testing circuit that n detection threshold value is different, is respectively as follows: irradiation dose testing circuit 1, irradiation dose testing circuit 2, irradiation dose testing circuit 3, irradiation dose testing circuit 4 ... irradiation dose testing circuit n.Each single irradiation dose testing circuit has two control signal outputs, respectively reference voltage control signal T and bias current control signal TN, and such as, two of irradiation dose testing circuit 1 export voltage control signal T on the basis of control signals1, bias current control signal TN1, voltage control signal T on the basis of two output control signals of irradiation dose testing circuit 22, bias current control signal TN2, voltage control signal T on the basis of two output control signals of irradiation dose testing circuit 33, bias current control signal TN3, voltage control signal T on the basis of two output control signals of irradiation dose testing circuit nn, bias current control signal TNnDeng.Described reference voltage regulating circuit 102 is according to reference voltage control signal T received1To Tn, the reference voltage of described sense amplifier 103 is carried out the adjustment of respective degrees.Described bias current adjusts circuit 104 according to the bias current control signal TN received1To TNn, the bias current of described sense amplifier 103 is carried out the adjustment of respective degrees.
During memory circuitry design, it is placed around irradiation dose testing circuit at Sensitive Apparatus and circuit module, such as, near memory element and sense amplifier.Irradiation dose testing circuit 1 to n arranges different detection dose threshold value, such as 50K to 300Krad (Si), and the sensitivity of irradiation effect selects the testing circuit of respective threshold according to side circuit.Output reference voltage control signal T of irradiation dose testing circuit1To TnControl the reference voltage of sense amplifier 103, bias current control signal TN1To TNnControl the bias current of sense amplifier 103, size according to irradiation dose, adjust in real time the benchmark of sense amplifier 103 and bias voltage and electric current, and the threshold value of sense amplifier 103 is adjusted, make circuit be maintained to correct duty when irradiation.
The internal circuit configuration of irradiation dose testing circuit 1 to n is the most identical, as in figure 2 it is shown, an irradiation dose testing circuit in described irradiation testing circuit 101 includes: comparator, resistance R1, resistance R2, resistance R3, resistance R4, electric capacity C1, electric capacity C2, NMOS tube Q0.Described NMOS tube Q0 uses Mn to carry out irradiation dose detection.One end of resistance R1 is connected with running voltage VDD, and the other end of resistance R1 is connected in series with one end of resistance R2, the other end ground connection of resistance R2, and electric capacity C1 is connected in parallel with resistance R2.One end of resistance R3 is connected with running voltage VDD, the other end of resistance R3 is connected in series with one end of resistance R4, the other end ground connection of resistance R4, and electric capacity C2 is connected in parallel with resistance R4, the drain electrode of NMOS tube Q0 is connected with one end of resistance R4, the grid of NMOS tube Q0 and source grounding.Being connected in series of resistance R1 and resistance R2 is a little connected with the in-phase input end Vp of comparator, and being connected in series of resistance R3 and resistance R4 is a little connected with the inverting input Vn of comparator.The outfan of comparator is divided into two circuits, and wherein a circuit is directly as reference voltage control signal output reference voltage control signal T, and another circuit exports bias current control signal TN again as bias current control signal after connecing a phase inverter.Electric capacity C1, C2 are filter capacitor, and at the two ends of resistance R2 and resistance R4, shunt capacitance C1, C2 is used to the impact eliminating supply voltage VDD shake to voltage Vp and Vn respectively.Comparator input terminal voltage Vp and Vn is obtained by resistance R1, R2, R3 and R4 dividing potential drop, and the difference of Vp and Vn is differential-mode input voltage Vd.As Vd > 0 time, comparator output high level；Vd < when 0, comparator output low level.
Include as it is shown on figure 3, bias current adjusts circuit: PMOS Q01, PMOS Q02, NMOS tube Q03, NMOS tube Q04, switch SN1To SNn, current source I0, current source I1To In.The drain electrode of described PMOS Q01 is connected with the drain electrode of described PMOS Q02, the grid of described PMOS Q01 is connected with the grid of described PMOS Q02, the grid of described PMOS Q01, the grid of described PMOS Q02 are connected with the source electrode of the drain electrode of described NMOS tube Q03, described PMOS Q01, the source electrode of described PMOS Q01 is connected with the drain electrode of described NMOS tube Q03, and the source electrode of described PMOS Q02 is connected with the drain electrode of described NMOS tube Q04.The grid of described NMOS tube Q03 adjusts the voltage input end V of circuit as bias currentin, the source electrode of described NMOS tube Q03 is connected with the source electrode of described NMOS tube Q04 and exports electric current Ibias, the grid of described NMOS tube Q04 adjusts the reference voltage output terminal V of circuit as bias currentref.Described switch SN1To SNnIt is connected in parallel, switchs SN1To SNnOne end access electric current Ibias, the other end passes through current source I1To InGround connection again.Described current source I0One termination output electric current Ibias, the other end is directly grounded.Described current source I0, current source I1To InThe bias current that sense amplifier needs when normally working is provided.By bias current control signal TN1To TNnChange, respectively control switch SN1To SNnDisconnection or Guan Bi, adjust sense amplifier bias current size, thus change sense amplifier gain, sense amplifier threshold value is adjusted.Such as, bias current control signal TN1Control switch SN1Disconnection Guan Bi, bias current control signal TN2Control switch SN2Disconnection Guan Bi, irradiation dose testing circuit output bias current control signal TNnControl switch SNnDisconnection Guan Bi etc..
As shown in Figure 4, reference voltage regulating circuit includes: PMOS Q05, NMOS tube Q06, PMOS Q1 to Qn, switch S1To Sn.The drain electrode of PMOS Q05 connects running voltage VDD, and the grid of PMOS Q05 is connected with its source electrode, and the source electrode of PMOS Q05 is connected with its drain electrode of NMOS tube Q06.The grid of NMOS tube Q06 is connected with drain electrode, and the drain electrode of NMOS tube Q06, the source electrode of PMOS Q05 meet reference voltage output terminal Vref, the source ground of NMOS tube Q06.The drain electrode of PMOS Q1 to Qn connects running voltage VDD, and grid is connected with source electrode, and source electrode meets switch S respectively1To SnOne end, switch S1To SnThe other end all be connected and access reference voltage output terminal Vref.Reference voltage control signal T of irradiation dose testing circuit output1To TnControl switch S respectively1To SnWork, pass through T1To TnSignal intensity, controls switch S1To SnDisconnection and Guan Bi, adjust sense amplifier reference voltage size, thus sense amplifier read threshold be adjusted.Such as, reference voltage control signal T1Control switch S1Disconnection Guan Bi, reference voltage control signal T2Control switch S2Disconnection Guan Bi, reference voltage control signal TnControl switch SnDisconnection Guan Bi etc..
Predose, by arranging resistance R1, resistance R2, resistance R3 and the value of resistance R4, makes Vn>voltage Vd that Vp, i.e. Vd<0, and irradiation dose testing circuit 1 to n are corresponding1To VdnDifferent values is set, for detecting different irradiation doses.Such as, Vd is worked as1>Vd2>……>VdnTime, corresponding detection dosage is exactly 50K to 300Krad (Si).Time non-irradiated, flow through the electric current I of NMOS tube Q0dsBeing 0, the voltage of Vp and Vn node is only determined by electric resistance partial pressure.Due to Vd < 0, so T signal is low level, TN signal is high level.Therefore, switch S1To SnDisconnect, VrefLevel is relatively low.Meanwhile, switch SN1To SNnGuan Bi, IbiasFor maximum.Now, sense amplifier read threshold is minimum.
When circuit is by irradiation, the threshold value of NMOS tube Q0 is drifted about, and flows through the electric current I of NMOS tube Q0dsAlong with the increase of irradiation dose is gradually increased, thus Vn point voltage is gradually reduced along with the increase of irradiation dose, and Vp point voltage keeps constant, and therefore, differential-mode input voltage Vd is gradually increased.When irradiation dose reaches 50K, Vd1> 0, Vd2～Vdn<0.So, T1High level, TN is become from low level1Low level is become from high level.Meanwhile, T1Control switch S1Guan Bi, VrefIncrease；TN1Control switch SN1Disconnect, IbiasReduce.Sense amplifier reads threshold value and increases.Now, even if cell leakage current increases, circuit also will not readout error data.
When irradiation dose continuation increase reaches 100K, Vd2> 0, Vd3～Vdn< 0, T2High level, TN is become from low level2Low level is become from high level.Meanwhile, switch S2Guan Bi, SN2Disconnect.Now, switch S1、S2It is in closure state, switchs S3To SnIt is off；Switch SN1、SN2Disconnect, switch SN3To SNnGuan Bi.So, VrefIncrease further, IbiasReduce further, cause sense amplifier to read threshold value and increase further.
In like manner, irradiation dose continues to increase, and dosage reaches 150K, 200K ... during 300K, control signal T3To TnBecome high level, TN successively3To TNnBecome low level successively.Thus, switch S3To SnGuan Bi number be gradually increased along with the increase of irradiation dose, VrefVoltage gradually rises；Meanwhile, switch SN3To SNnThe number disconnected also is gradually increased along with the increase of irradiation dose, sense amplifier bias current IbiasIt is gradually reduced.So sense amplifier read threshold gradually steps up along with the increase of irradiation dose.
When irradiation dose is gradually reduced or irradiation effect fades away, irradiation testing circuit remains able to the reduction speed according to irradiation dose or effect, controls switch S1To SnWith switch SN1To SNnThe number of closed and disconnected, is adjusted correspondingly the read threshold of sense amplifier.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent and improvement etc. made within the spirit and principles in the present invention, should be included within the scope of the present invention.
Claims (6)
1. dosage adapt device followed by a Flouride-resistani acid phesphatase memorizer, it is characterised in that including: irradiation testing circuit, sense amplifier, also includes that a reference voltage regulating circuit or bias current adjust circuit；
Described irradiation testing circuit is for detecting the change of irradiation dose, and the control signal produced is sent to described reference voltage regulating circuit and described bias current adjustment circuit；
Described reference voltage regulating circuit is connected with described sense amplifier, adjusts the size of sense amplifier reference voltage, thus changes sense amplifier gain, is adjusted the read threshold of sense amplifier；
Described bias current adjusts circuit and is connected with described sense amplifier, adjusts the size of sense amplifier bias current, thus is adjusted the read threshold of sense amplifier；
Described irradiation testing circuit includes that detecting threshold value different irradiation dose testing circuit 1 to irradiation dose testing circuit n, described irradiation dose testing circuit 1 to irradiation dose testing circuit n has two control signal outputs, respectively reference voltage control signal T respectively1To Tn, bias current control signal TN1To TNn；
The reference voltage of described sense amplifier, according to the reference voltage control signal received, is carried out the adjustment of respective degrees by described reference voltage regulating circuit；
The bias current of described sense amplifier, according to the bias current control signal received, is carried out the adjustment of respective degrees by described bias current adjustment circuit；
Described irradiation dose testing circuit includes: comparator, resistance R1, resistance R2, resistance R3, resistance R4, electric capacity C1, electric capacity C2, NMOS tube Q0；
One end of resistance R1 is connected with running voltage, and the other end of resistance R1 is connected in series with one end of resistance R2, the other end ground connection of resistance R2, and electric capacity C1 is connected in parallel with resistance R2；
One end of resistance R3 is connected with running voltage, the other end of resistance R3 is connected in series with one end of resistance R4, the other end ground connection of resistance R4, and electric capacity C2 is connected in parallel with resistance R4, the drain electrode of NMOS tube Q0 is connected with one end of resistance R4, the grid of NMOS tube Q0 and source ground；
Being connected in series of resistance R1 and resistance R2 is a little connected with the in-phase input end of comparator, and being connected in series of resistance R3 and resistance R4 is a little connected with the inverting input of comparator.
Dosage adapt device followed by Flouride-resistani acid phesphatase memorizer the most according to claim 1, it is characterized in that, the outfan of described comparator is divided into two circuits, wherein a circuit exports directly as reference voltage control signal, and another circuit exports as bias current control signal after connecing a phase inverter again.
Dosage adapt device followed by Flouride-resistani acid phesphatase memorizer the most according to claim 1, it is characterised in that described bias current adjusts circuit and includes: PMOS Q01, PMOS Q02, NMOS tube Q03, NMOS tube Q04, switch SN1To SNn, current source I0, current source I1To In；
The drain electrode of described PMOS Q01 is connected with the drain electrode of described PMOS Q02, the grid of described PMOS Q01 is connected with the grid of described PMOS Q02, the grid of described PMOS Q01, the grid of described PMOS Q02 are connected with the source electrode of the drain electrode of described NMOS tube Q03, described PMOS Q01, and the source electrode of described PMOS Q02 is connected with the drain electrode of described NMOS tube Q04；
The grid of described NMOS tube Q03 adjusts the voltage input end of circuit as bias current, and the source electrode of described NMOS tube Q03 is connected with the source electrode of described NMOS tube Q04 and exports electric current Ibias, the grid of described NMOS tube Q04 adjusts the reference voltage output terminal of circuit as bias current；
Described switch SN1To SNnIt is connected in parallel, switchs SN1To SNnOne termination electric current Ibias, the other end passes through current source I1To InGround connection again, described current source I0One termination output electric current Ibias, the other end is directly grounded.
Dosage adapt device followed by Flouride-resistani acid phesphatase memorizer the most according to claim 1, it is characterised in that described reference voltage regulating circuit includes: PMOS Q05, NMOS tube Q06, PMOS Q1 to Qn, switch S1To Sn；
The drain electrode of PMOS Q05 connects running voltage, and the grid of PMOS Q05 is connected with its source electrode, and the source electrode of PMOS Q05 is connected with the drain electrode of NMOS tube Q06；
The grid of NMOS tube Q06 drains with it and is connected, and the drain electrode of NMOS tube Q06, the source electrode of PMOS Q05 meet reference voltage Vref, the source ground of NMOS tube Q06；
The drain electrode of PMOS Q1 to Qn connects running voltage, and grid is connected with source electrode, and source electrode meets switch S1To SnOne end, switch S1To SnThe other end all be connected and access reference voltage output terminal.
Dosage adapt device followed by Flouride-resistani acid phesphatase memorizer the most according to claim 4, it is characterised in that described reference voltage control signal T1To TnControl switch S respectively1To SnGuan Bi or disconnection.
Dosage adapt device followed by Flouride-resistani acid phesphatase memorizer the most according to claim 3, it is characterised in that described bias current control signal TN1To TNnControl switch SN respectively1To SNnGuan Bi or disconnection.
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| CN104953988B (en) * | 2015-06-19 | 2019-05-17 | 西安紫光国芯半导体有限公司 | The memory construction of anti-interference comparator and the methods and applications comparator in high precision |
| CN109917271B (en) * | 2019-03-13 | 2021-04-02 | 电子科技大学 | Total dose effect detection circuit |
| CN109947695A (en) * | 2019-04-24 | 2019-06-28 | 北京锐达芯集成电路设计有限责任公司 | It is a kind of for protecting anti-radiation controller chip, controller and the method for component |
| CN110471485B (en) * | 2019-08-30 | 2020-09-15 | 电子科技大学 | Total dose effect reinforcing circuit based on segmented current compensation |
| CN111697934B (en) * | 2020-06-18 | 2023-08-08 | 北京时代民芯科技有限公司 | Anti-radiation reinforcement comparator circuit with low detuning characteristic |
| EP4210061A4 (en) * | 2020-10-26 | 2023-10-18 | Huawei Technologies Co., Ltd. | Data reading circuit and control method therefor |
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| US6324102B1 (en) * | 2000-12-14 | 2001-11-27 | Actel Corporation | Radiation tolerant flash FPGA |
| CN102169711A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | Single chip structured programmable logic device with resistance random access memory (RAM) module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6324102B1 (en) * | 2000-12-14 | 2001-11-27 | Actel Corporation | Radiation tolerant flash FPGA |
| CN102169711A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | Single chip structured programmable logic device with resistance random access memory (RAM) module |
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