CN103199876B - Realize the method and device of soft-decision FEC decoding - Google Patents
Realize the method and device of soft-decision FEC decoding Download PDFInfo
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Abstract
The invention discloses a kind of method and device realizing soft-decision FEC decoding, relate to the communications field, for solving the problem that in prior art, the error correcting capability of FEC decoder is poor.The method include that data receiver receives multiple fec frames, and each fec frame received is decomposed into n subframe, subframe decomposition obtained is sent to decoder group successively according to the decoding cycle；If the subframe in a FEC decoder reach n, by described n subframe composition fec frame to be decoded, and described fec frame to be decoded is carried out soft-decision FEC decoding；If the subframe in a FEC decoder reach n+1, first the subframe arrived at first in a described FEC decoder is sent to the 2nd coupled FEC decoder by the most described FEC decoder, then remaining n subframe is formed fec frame to be decoded, and described fec frame to be decoded is carried out Soft decision decoding.The present invention is applicable to the communications field, is used for realizing soft-decision FEC decoding.
Description
Technical field
The present invention relates to the communications field, particularly relate to one and realize soft-decision FEC (Forward Error
Correct, forward error correction) method and device that decodes.
Background technology
In current digital communication system, FEC technology is widely used.FEC is a kind of data
Coding techniques, data sending terminal adds the error correcting code of certain redundancy in needing the data message sent, receives
End carries out error detection according to error correcting code.In FEC mode, receiving terminal not only can find mistake, and can determine that
The position that binary element makes a mistake, thus corrected.
In 100G optical communication system, except using FEC technology, it is additionally added soft-decision (Soft-Decision)
To obtain higher transmission performance, reduce optical channel OSNR (Optical Signal Noise Ratio, light letter
Make an uproar ratio) requirement.Concrete, soft-decision FEC decoding is the Soft Inform ation (ratio utilizing error correcting code at receiving terminal
As having the probit of certain decimal place) calculate through successive ignition, to promote the error correcting capability of receiving terminal,
Iterations is the most, and error correcting capability is the strongest.At present, the soft-decision FEC decoding side used in 100G optic communication
Case is full parellel decoding scheme: after system receiving terminal receives the fec frame of an independent completion every time, by this FEC
Frame sends and decodes to FEC decoder, and this fec frame is carried out error correction, obtains decoding result；Complete one
After secondary decoding, the decoding result obtained is sent again to this FEC decoder and decode；Repeatedly translate
Data are exported by hard decision after code process.
During realizing the present invention, inventor finds that in prior art, at least there are the following problems:
Owing to existing full parellel decoding scheme is fec frame to be repeatedly sent to a FEC decoder be iterated
Decoding；When fec frame length is bigger, the iteration that FEC decoder can be carried out at a fec frame cycle time
Decoding number of times is limited, and the error correcting capability that can cause FEC decoder is poor.
Summary of the invention
Embodiments of the invention provide implementation method and the device of a kind of soft-decision FEC decoder, it is possible to solve
When in prior art, fec frame length is bigger, FEC decoder a fec frame can carry out cycle time repeatedly
Generation decoding number of times is limited, causes the problem that the error correcting capability of FEC decoder is poor.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
First aspect, embodiments provides a kind of method realizing soft-decision FEC decoding, the method
Be applied to a kind of code translator, described code translator include data receiver and by multiple be connected step by step translate
The decoder group that code device is constituted, the decoder in described decoder group has identical encoded control logic, institute
The method of stating includes:
Described data receiver receives multiple fec frames, and each fec frame received is decomposed into n son
Frame, subframe decomposition obtained is sent to described decoder group successively according to the decoding cycle, and described n is the most whole
Number；
In the kth decoding cycle, if after the FEC decoder in described decoder group receives subframe,
Subframe in a described FEC decoder reach n, the most described FEC decoder is by described n
Subframe forms fec frame to be decoded, and described fec frame to be decoded is carried out soft-decision FEC decoding；If
A described FEC decoder receives after subframe, the subframe in a described FEC decoder reach n+1,
The most described FEC decoder first the subframe arrived at first in a described FEC decoder is sent to
Its 2nd FEC decoder being connected, then forms fec frame to be decoded by remaining n subframe, and to institute
Stating fec frame to be decoded and carry out Soft decision decoding, wherein, described k is the positive integer more than or equal to n, described
Oneth FEC decoder is any decoder in described decoder group.
In the implementation that the first is possible, if a described FEC decoder decodes the cycle in kth
After receiving a subframe, the subframe in a described FEC decoder reaches n, the most described FEC
Decoder carries out inputting data bit width conversion process to the subframe received in the described kth decoding cycle, really
The Soft Inform ation figure place of fixed described subframe；By the subframe converted through data bit width and a described FEC decoder
In n-1 sub-frame level having deposited be unified into fec frame to be decoded, described fec frame to be decoded is sent to verifying joint
Point more new module carries out checking treatment and obtains check-node information, and described check-node information is used for characterizing described
The error of each data bit in complete fec frame；According to described check-node information to described fec frame to be decoded
Carry out variable process, each data bit in described fec frame to be decoded is carried out error correction to reduce error；
Or
If a described FEC decoder is after the kth decoding cycle receives a subframe, described first
Subframe in FEC decoder reaches n+1, and the most described FEC decoder is first by a described FEC
The subframe arrived at first in decoder is sent to the 2nd coupled FEC decoder, then to described
The subframe that k decoding cycle receives carries out inputting data bit width conversion process, determines the Soft Inform ation of described subframe
Figure place；By remaining n-1 subframe in the subframe converted through data bit width and a described FEC decoder
It is cascaded into fec frame to be decoded, the transmission of described fec frame to be decoded is verified to check-node more new module
Process obtains check-node information, and described check-node information is for characterizing each number in described complete fec frame
Error according to position；According to described check-node information, described fec frame to be decoded is carried out variable process, to institute
State each data bit in fec frame to be decoded and carry out error correction to reduce error.
In conjunction with the first possible implementation of first aspect, in the implementation that the second is possible, institute
State a FEC decoder first the subframe arrived at first in a described FEC decoder to be sent to and its phase
The 2nd FEC decoder even, including:
Each data bit in described fec frame to be decoded carried out error correction after reducing error described, the
In k+1 decoding cycle, the son being initially received in n subframe of described fec frame to be decoded will be formed
Frame carries out outputs data bits width conversion process, will be sent to through this subframe of described data bit width change process
The 2nd FEC decoder being connected with a described FEC decoder.
The first likely implementation or the of first aspect in conjunction with first aspect or first aspect
Two kinds of possible implementations, in the implementation that the third is possible, each in described decoder group translates
Code device is connected in series into mutually row iteration soft-decision FEC decoding；
After each FEC decoder completes soft-decision FEC decoding, also include:
Current error-correcting performance is added up.
The first possible implementation or the second of first aspect in conjunction with first aspect or first aspect
Plant possible implementation or the third possible implementation of first aspect, the 4th kind of possible reality
In existing mode, described method also includes: from described decoder group, the decoder at end receives subframe, and by n
Individual subframe is integrated into a fec frame.
Second aspect, the embodiment of the present invention additionally provides a kind of device realizing soft-decision FEC decoding, including
Data receiver and decoder group, wherein:
Described data receiver end is used for receiving multiple fec frame, and is decomposed into by each fec frame received
N subframe, subframe decomposition obtained sent to described decoder group, described n successively according to the decoding cycle
For positive integer；
Described decoder group includes decoder that is multiple that be connected step by step and that have identical encoded control logic,
Described encoded control logic includes: in the kth decoding cycle, if after receiving subframe, and described decoder
The subframe in a FEC decoder in group reach n, the most described FEC decoder is by described n
Individual subframe forms fec frame to be decoded, and described fec frame to be decoded is carried out soft-decision FEC decoding；As
Fruit is receiving after subframe, in a described FEC decoder subframe of storage reach n+1, the most described the
The subframe arrived at first in described FEC mono-decoder is sent to the decoding of next stage by one FEC decoder
Device, and a described FEC decoder is by remaining n subframe composition fec frame to be decoded, treats described
Decoding fec frame carries out Soft decision decoding, and wherein, k is the positive integer more than or equal to n, a described FEC
Decoder is any decoder in described decoder group.
In the implementation that the first is possible, a described FEC decoder includes: input data process mould
Block, variable node more new module and check-node more new module, wherein:
The subframe received, for receiving subframe one by one, is carried out inputting data by described input data processing module
Bit wide conversion process, determines the Soft Inform ation figure place of described subframe；
Described variable node more new module is for by the subframe processed through described input data processing module and institute
State n-1 the sub-frame level deposited in a FEC decoder and be unified into fec frame to be decoded, by described FEC to be decoded
Frame sends to described check-node more new module；
Described check-node more new module is for receiving described FEC to be decoded from described variable node more new module
Frame carries out checking treatment, obtains check-node information, and described check-node information is used for characterizing described to be decoded
The error of each data bit in fec frame；
Described check-node more new module is additionally operable to according to described check-node information described fec frame to be decoded
Carry out variable process, each data bit in described fec frame to be decoded is carried out error correction to reduce error.
In conjunction with the first possible implementation of second aspect or second aspect, in the realization that the second is possible
In mode, a described FEC decoder also includes export data processing module, for saving at described variable
Point more new module carries out error correction to reduce after error to each data bit in described fec frame to be decoded, under
One decoding cycle enters forming the subframe being initially received in n subframe of described fec frame to be decoded
Row outputs data bits width conversion process, is sent to this subframe through described data bit width change process and institute
State the 2nd FEC decoder that a FEC decoder is in series.
The first possible implementation or the second of second aspect in conjunction with second aspect or second aspect
Planting possible implementation, in the implementation that the third is possible, described device also includes performance statistics mould
Block, after completing soft-decision FEC decoding at every one-level FEC decoder, enters current error-correcting performance
Row statistics.
The first possible implementation or the second of second aspect in conjunction with second aspect or second aspect
Plant possible implementation or the third possible implementation of the third aspect, the 4th kind of possible reality
In existing mode, described device also includes integrating decoder, described integration decoder and end in described decoder group
The decoder of tail connects, and for receiving subframe from described decoder group, and n subframe is integrated into one
Fec frame.
What the embodiment of the present invention provided realizes the method and device of soft-decision FEC decoding, each by receive
Fec frame is decomposed into n subframe, each FEC decoder successively every n subframe is carried out once decoding
Reason, realizes the iterative decoding to every n subframe by multiple FEC decoders being serially connected.Use this
The method that bright embodiment provides, the number of times that fec frame is iterated decoding is not limited by fec frame length,
The error correcting capability of FEC decoder can be improved；On the other hand, fec frame is decomposed into n subframe, permissible
The timesharing dispatching cycle of computing circuit in frame length flexible design FEC decoder according to subframe, it is possible to reduce
The scale of computing circuit in FEC decoder, it is simple to realize and cost is relatively low.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement
In example or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, describe below
In accompanying drawing be only some embodiments of the present invention, for those of ordinary skill in the art, do not paying
On the premise of going out creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The method flow schematic diagram realizing soft-decision FEC decoding that Fig. 1 provides for the embodiment of the present invention one；
The method flow schematic diagram realizing soft-decision FEC decoding that Fig. 2 provides for the embodiment of the present invention two；
The knot of the device realizing soft-decision FEC decoding that Fig. 3, Fig. 4, Fig. 5 provide for the embodiment of the present invention three
Structure schematic diagram.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, be fully described by, it is clear that described embodiment be only a part of embodiment of the present invention rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creation
The every other embodiment obtained under property work premise, broadly falls into the scope of protection of the invention.
Embodiment one
Embodiments provide a kind of method realizing soft-decision FEC decoding, carry for a kind of present invention
In the code translator of confession, the code translator that the present invention provides includes data receiver and is connected step by step by multiple
Decoder constitute decoder group, the decoder in described decoder group has identical encoded control logic,
As it is shown in figure 1, described method includes:
101, data receiver receives multiple fec frames, and each fec frame received is decomposed into n
Subframe, subframe decomposition obtained was sent in described decoder group successively according to the decoding cycle, and described n is
Positive integer.
Concrete, in order to make it easy to understand, the present embodiment (is denoted as with any decoder in described decoder group
Oneth FEC decoder) as a example by illustrate, specific as follows:
In kth (k is more than or equal to n) in the individual decoding cycle, if a described FEC decoder receives subframe
After, the subframe in a described FEC decoder reach n, then perform 102；If a described FEC
Decoder receives after subframe, the subframe in a described FEC decoder reach n+1, then perform 103.
102, described n subframe is formed fec frame to be decoded by a described FEC decoder, and to described
Fec frame to be decoded carries out soft-decision FEC decoding.
103, the subframe that first a described FEC decoder will arrive in a described FEC decoder at first
It is sent to the 2nd coupled FEC decoder, then remaining n subframe is formed fec frame to be decoded,
And described fec frame to be decoded is carried out Soft decision decoding.
What deserves to be explained is, described decoder group includes multiple FEC decoder, and the plurality of FEC decodes
Device is serially connected, possesses identical encoded control logic, for carrying out iterative decoding repeatedly.
In the present embodiment, FEC decoder described fec frame to be decoded is carried out once decoding and process, pass through
Multiple FEC decoders being serially connected realize the successive ignition to fec frame and decode.Meanwhile, described FEC
Decoder often receives/sends a subframe and carries out once decoding process, i.e. completes within a period of sub-frame time
Fec frame decoding, it is possible to effectively reduce the circuit scale in FEC decoder.
What the embodiment of the present invention provided realizes the method that soft-decision FEC decodes, each fec frame that will receive
It is decomposed into n subframe, each FEC decoder successively every n subframe is carried out once decoding and processes, logical
Cross multiple FEC decoder being serially connected and realize the decoding of the successive ignition to every n subframe.Use the present invention
The method that embodiment provides, the number of times that fec frame is iterated decoding is not limited by fec frame length, energy
The high error correcting capability that FEC decoder is provided；On the other hand, fec frame is decomposed into n subframe, Ke Yigen
According to the timesharing dispatching cycle of computing circuit in the frame length flexible design FEC decoder of subframe, it is possible to reduce FEC
The scale of computing circuit in decoder, it is simple to realize and cost is relatively low.
Embodiment two
Embodiments provide a kind of method realizing soft-decision FEC decoding, the method is applied to one
Code translator, described code translator includes data receiver and is made up of multiple decoders being connected step by step
Decoder group, the decoder in described decoder group has identical encoded control logic, concrete, such as Fig. 2
Shown in, described method includes:
201, data receiver receives multiple fec frames, and each fec frame received is decomposed into n son
Frame, subframe decomposition obtained sent to described decoder group, wherein, described n successively according to the decoding cycle
For positive integer.
Wherein, described fec frame includes the FEC heading for error correction and data message, different agreement type
In communication system, the existence form of FEC heading can be different.Such as, in the communication system using IP agreement
In, data message can be carried out by FEC heading by increasing encapsulated layer (or using existing encapsulated layer)
Encapsulation is to increase FEC heading.The existence form of the FEC heading in the communication system of other protocol types
Here is omitted.
202, the FEC decoder in described decoder group receives described son one by one according to the described decoding cycle
Frame.
What deserves to be explained is, a described FEC decoder is any decoder in described decoder group.?
In the present embodiment, with a FEC decoder, the 2nd FEC decoder, the 3rd FEC decoder ... for
Illustrate as a example by multiple decoders being connected step by step.
Concrete, in kth (k is the positive integer more than or equal to n) in the individual decoding cycle, if described first
FEC decoder receives after subframe, the subframe in a described FEC decoder reach n, then perform 203；
If after a described FEC decoder receives subframe, reaching of the subframe in a described FEC decoder
N+1, then perform 204.
203, described n subframe is formed fec frame to be decoded by a described FEC decoder.
204, the subframe that first a described FEC decoder will arrive in a described FEC decoder at first
It is sent to the 2nd coupled FEC decoder, then remaining n subframe is formed fec frame to be decoded.
205, the subframe received in the described kth decoding cycle is inputted by a described FEC decoder
Data bit width conversion process, determines the Soft Inform ation figure place of described subframe.
For example, it is possible to be modulated by ADC (Analog-to-Digital Converter, analog-digital converter)
To realize input data bit width conversion process, wherein, the Soft Inform ation figure place of described subframe depends on the energy of ADC
Power.
206, the subframe converted through data bit width and a described FEC are translated by a described FEC decoder
N-1 the sub-frame level deposited in code device is unified into fec frame to be decoded, sends described fec frame to be decoded to school
Testing node updates module to carry out checking treatment and obtain check-node information, described check-node information is used for characterizing
The error of each data bit in described fec frame to be decoded.
What deserves to be explained is, described FEC decoder includes described check-node more new module and variable
More new module；Described check-node more new module, for fec frame is carried out checking treatment, determines check-node
Information；Described variable update module is for according to each to described fec frame to be decoded of described check-node information
Individual data bit carries out error correction.Concrete, described check-node more new module and variable update module can be by spies
Determine computing circuit to realize, and such as ASIC (Application Specific Integrated Circuit, special integrated
Circuit).
207, described fec frame to be decoded is become by described variable update module according to described check-node information
Amount processes, and each data bit in described fec frame to be decoded carries out error correction to reduce error.
By 203-207, i.e. achieve the decoding process to fec frame in the kth decoding cycle.
Optionally, in order to obtain fec frame complete after decoding processes, can increase in described code translator
Integrate decoder, connect with the decoder at end in described decoder group at described integration decoder for one, use
In receiving the subframe after decoding processes from described decoder group, and n the subframe received is integrated into one
Individual fec frame.
208, decoding the cycle kth+1, a described FEC decoder will form described FEC to be decoded
The subframe being initially received in n subframe of frame carries out outputs data bits width conversion process, will be through institute
State the 2nd FEC that this subframe of data bit width change process is sent to be in series with a described FEC decoder
Decoder.
209, described 2nd FEC decoder receive described oneth FEC decoder send subframe, according to
The method that a described FEC decoder is identical carries out decoding process.
What deserves to be explained is, the method that the present embodiment provides exists multiple FEC decoder, the plurality of FEC
Decoder and a described FEC decoder are in series and are iterated soft-decision FEC decoding, the plurality of FEC
Decoder is identical with a described FEC decoder function.One fec frame is carried out by each FEC decoder
Once decoding processes, and the FEC decoder quantity being serially connected is the most, and the iteration carrying out a fec frame is translated
Code number of times is the most, and error correcting capability is the strongest.
Preferably, in order to determine the quantity of the FEC decoder of the error correcting capability meeting different index, each
After individual FEC decoder completes soft-decision FEC decoding, it is also possible to current error-correcting performance is added up,
Determine the fec frame bit error rate after each FEC decoder.Such as, if to specifying message to carry out soft
Judgement FEC decoding, it is desirable to the bit error rate of this appointment message is less than predetermined threshold value A；So can add up this to refer to
Determine the message bit error rate after each FEC decoder processes；If after 10 FEC decoders
The bit error rate is less than predetermined threshold value A, then then sentenced by after 10 FEC decoders by this appointment message
Certainly output, it is not necessary to carry out more iterative decoding again, sets minimum number on the premise of meeting pre-set level
FEC decoder, save decoding time and decoding cost.
The present embodiment provide realize soft-decision FEC decoding method, can apply to all employing FEC
The communication system of technology, is particularly suitable for application to the optical communication system that transfer rate is big, such as 100G optic communication
System.Next as a example by 100G optical communication system, said method is described in detail:
As a example by business clock frequency 500Mhz, a complete fec frame are as 8000bit, then a business
Clock cycle is 2ns, and the bit wide of input interface is the 200bit (transfer rate due to 100G optical communication system
For 100Gbps, so each business clock periodic transfer 200bit).In 100G optical communication system, preferably
N=4, will be decomposed into 4 subframes by a fec frame, and the frame length of each subframe is 2000bit.
What the receiving terminal of S1,100G optical communication system was lasting receives complete fec frame successively, can be denoted as
Fec frame A, fec frame B, fec frame C ... wait multiple fec frame, and are transmitted to FEC decoder and enter
Row soft-decision FEC decodes.
The fec frame received is decomposed into 4 subframes by S2, FEC decoder, such as, by fec frame A
It is decomposed into subframe 0, subframe 1, subframe 2, subframe 3, by fec frame B according to the sequencing of the time of transmission
Being decomposed into subframe 4, subframe 5, subframe 6, subframe 7, wherein, the subframe that subframe number is little sends the time early,
The subframe that subframe number is big sends evening time.Using same method, FEC decoder can be to the institute received
Having fec frame to decompose, here is omitted.
S3, after completing fec frame to decompose, FEC decoder carries out inputting data to decomposing the subframe that obtains
Bit wide conversion process, a length of 200 × 6bit of sub-frame frame after process.Wherein, 6 for through input data bit width
The bit number of the Soft Inform ation of conversion process.For example, it is possible to the bit wide of subframe is converted by ADC, its
In, the bit number of Soft Inform ation depends on the ability of ADC.
What deserves to be explained is, the process that S2-S3 describes is to use the method first decomposed, carry out bit wide conversion again.
Optionally, it would however also be possible to employ advanced line position width conversion, the method decomposed again, do not limit.
S4, FEC decoder is received by internal variable node more new module and the docking of check-node more new module
To 4 subframes carry out decoding process.Such as, FEC decode receive subframe 0, subframe 1, subframe 2,
After subframe 3, above-mentioned 4 subframes can be carried out soft-decision FEC decoding and process；Then, subframe 0 is entered
Row outputs data bits width converts and sends to next FEC decoder, receives subframe 4 simultaneously, to subframe 1, son
Frame 2, subframe 3, subframe 4 carry out soft-decision FEC decoding and process.
It is to say, FEC decoder receives a new subframe in each business clock cycle, incite somebody to action this simultaneously
The oldest subframe of ground caching sends to next decoder；Meanwhile, FEC decoder can be successively to receiving
New subframe and 3 subframes of this locality carry out FEC decoding process.
Such as, in first business clock cycle, FEC decoder is to subframe 0, subframe 1, subframe 2, subframe
3 carry out soft-decision FEC decoding processes；
Second business clock cycle, subframe 1, subframe 2, subframe 3, subframe 4 are entered by FEC decoder
Row soft-decision FEC decoding processes；
The 3rd business clock cycle, subframe 2, subframe 3, subframe 4, subframe 5 are entered by FEC decoder
Row soft-decision FEC decoding processes, the like.
In sum, a subframe can carry out 4 iterative decodings in a FEC decoder and process, and passes through
Multiple FEC decoders of series connection, can effectively increase the iterations of FEC decoding.Such as, if had
N number of FEC decoder, then can realize the N × 4 time iterative decoding to each subframe, it is possible to carry greatly
High error correcting capability.
Meanwhile, according to said method, FEC decoder is complete to 4 subframes (i.e. one complete fec frame)
The time once decoded is become to be 10 business clock cycles to the maximum (because a subframe is 2000bit, FEC
The bit wide of decoder is 200bit).If using the FEC interpretation method of prior art, FEC decoder receives
One complete fec frame needs 10 × 4 business clock cycles, i.e. FEC decoder needs 40 industry
The decoding of the successive ignition to fec frame is completed in the business clock cycle.If prior art is 10 business clock weeks
Complete once to decode to fec frame in phase, then within 40 business clock cycles, fec frame can only be completed 4
Secondary iterative decoding, and the error correcting capability after 4 iterative decodings does not reaches far away the requirement of most of communication system.
So, prior art needs to improve the disposal ability of computing circuit in FEC decoder, fec frame is carried out
Parallel processing, to improve the iterations of FEC decoding.So, FEC is translated by the method that the present embodiment provides
In code device, the requirement of computing circuit is relatively low, it is simple to realize.
What the embodiment of the present invention provided realizes the method that soft-decision FEC decodes, each fec frame that will receive
It is decomposed into n subframe, each FEC decoder successively every n subframe is carried out once decoding and processes, logical
Cross multiple FEC decoder being serially connected and realize the decoding of the successive ignition to every n subframe.Use the present invention
The method that embodiment provides, the number of times that fec frame is iterated decoding is not limited by fec frame length, energy
Enough improve the error correcting capability of FEC decoder；On the other hand, fec frame is decomposed into n subframe, Ke Yigen
According to the timesharing dispatching cycle of computing circuit in the frame length flexible design FEC decoder of subframe, it is possible to reduce FEC
The scale of computing circuit in decoder, it is simple to realize and cost is relatively low.
Embodiment three
Embodiments provide a kind of device realizing soft-decision FEC decoding, it is possible to realize above-mentioned Fig. 1
With the embodiment of the method shown in Fig. 2, as it is shown on figure 3, described device includes data receiver 31 and decoder
Group 32, described decoder group 32 includes multiple that be connected step by step and translating of having identical encoded control logic
Code device, as illustrated in the drawing a FEC decoder 321, the 2nd FEC decoder 322 etc..
Described data receiver 31 is used for receiving multiple fec frame, and is decomposed by each fec frame received
For n subframe, subframe decomposition obtained sent to described decoder group 32, institute successively according to the decoding cycle
Stating n is positive integer；
Described decoder group 32 is for receiving described subframe successively according to the described decoding cycle, and to receiving
Subframe carries out decoding process；
Concrete, decoder in described decoder group is (such as the FEC decoder 321 in Fig. 3 and the
Two FEC decoders 322) encoded control logic be: in the kth decoding cycle, if receive subframe
After, the subframe in a FEC decoder 321 in described decoder group reach n, the most described first
Described n subframe is formed fec frame to be decoded by FEC decoder 321, and enters described fec frame to be decoded
Row soft-decision FEC decodes；If after receiving subframe, the son of storage in a described FEC decoder 321
Frame reach n+1, the most described FEC decoder 321 by described FEC mono-decoder 321
The subframe first arrived is sent to the decoder (the i.e. the 2nd FEC decoder 322) of next stage, and described first
Remaining n subframe is formed fec frame to be decoded by FEC decoder 321, enters described fec frame to be decoded
Row Soft decision decoding, wherein, k is the positive integer more than or equal to n, and a described FEC decoder is described
Any decoder in decoder group.
Concrete, multiple FEC decoders being serially connected in the device shown in Fig. 3 on receiving
After the subframe that FEC decoder sends, carry out repeatedly according to the method identical with a described FEC decoder 321
Process for soft-decision FEC decoding.
In order to make it easy to understand, the present embodiment illustrates as a example by a FEC decoder 321:
As shown in Figure 4, a described FEC decoder 321 includes: input data processing module 3211, change
Amount node updates module 3212 and check-node more new module 3213, wherein:
The subframe received, for receiving subframe one by one, is inputted by described input data processing module 3211
Data bit width conversion process, determines the Soft Inform ation figure place of described subframe；
Described variable node more new module 3212 will be for processing through described input data processing module 3211
Subframe and a described FEC decoder 321 in n-1 sub-frame level having deposited be unified into fec frame to be decoded,
Described fec frame to be decoded is sent to described check-node more new module 3213；
Described check-node more new module 3213 is described for receiving from described variable node more new module 3212
Complete fec frame carries out checking treatment, obtains check-node information, and described check-node information is used for characterizing
The error of each data bit in described complete fec frame；
Described check-node more new module 3213 is additionally operable to according to the check-node information obtained described to be decoded
Fec frame carries out variable process, each data bit in described fec frame to be decoded carries out error correction to reduce error.
As shown in Figure 4, a described FEC decoder 321 also includes exporting data processing module 3214, uses
In described variable node more new module 3212 each data bit in described fec frame to be decoded carried out error correction with
Reduce after error, will form in n subframe of described fec frame to be decoded at first in the next one decoding cycle
The subframe received carries out outputs data bits width conversion process, will be through described data bit width change process
This subframe be sent to the 2nd FEC decoder 322 that is in series with a described FEC decoder 321.
As shown in Figure 4, described device also includes performance statistic module 33, at every one-level FEC decoder
After completing soft-decision FEC decoding, current error-correcting performance is added up.
Further, as it is shown in figure 5, described device also includes integrating decoder 34, described integration decoder
34 connect with the decoder at end in described decoder group 32, for receiving son from described decoder group 32
Frame, and n subframe is integrated into a fec frame.
What the embodiment of the present invention provided realizes the device of soft-decision FEC decoding, is serially connected including multiple
FEC decoder, fec frame to be decoded was once decoded within a decoding cycle by each FEC decoder
Process, realize iterative decoding repeatedly by multiple FEC decoders being serially connected.The employing present invention implements
The device that example provides, the number of times that fec frame is iterated decoding is not limited by fec frame length, it is possible to carry
The error correcting capability of high FEC decoder；On the other hand, fec frame is decomposed into n subframe, can be according to son
The timesharing dispatching cycle of computing circuit in the frame length flexible design FEC decoder of frame, it is possible to reduce FEC decoding
The scale of computing circuit in device, it is simple to realize and cost is relatively low.
Through the above description of the embodiments, those skilled in the art is it can be understood that arrive this
Bright can add the mode of required common hardware by software and realize, naturally it is also possible to by hardware, but a lot
In the case of the former is more preferably embodiment.Based on such understanding, technical scheme substantially or
Person says that the part contributing prior art can embody with the form of software product, and this computer is soft
Part product is stored in the storage medium that can read, such as the floppy disk of computer, and hard disk or CD etc., if including
Dry instruction is with so that a computer equipment (can be personal computer, server, or the network equipment
Deng) perform the method described in each embodiment of the present invention.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited to
This, any those familiar with the art, in the technical scope that the invention discloses, can readily occur in
Change or replacement, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention should
It is as the criterion with described scope of the claims.
Claims (10)
1. the method realizing soft-decision forward error correction FEC decoding, it is characterised in that the method is applied to
A kind of code translator, described code translator includes data receiver and by multiple decoder structures being connected step by step
The decoder group become, the decoder in described decoder group has identical encoded control logic, described method
Including:
Described data receiver receives multiple fec frames, and each fec frame received is decomposed into n son
Frame, subframe decomposition obtained is sent to described decoder group successively according to the decoding cycle, and described n is the most whole
Number；
In the kth decoding cycle, if after the FEC decoder in described decoder group receives subframe,
Subframe in a described FEC decoder reach n, the most described FEC decoder is by described n
Subframe forms fec frame to be decoded, and described fec frame to be decoded is carried out soft-decision FEC decoding；If
A described FEC decoder receives after subframe, the subframe in a described FEC decoder reach n+1,
The most described FEC decoder first the subframe arrived at first in a described FEC decoder is sent to
Its 2nd FEC decoder being connected, then forms fec frame to be decoded by remaining n subframe, and to institute
Stating fec frame to be decoded and carry out Soft decision decoding, wherein, described k is the positive integer more than or equal to n, described
Oneth FEC decoder is any decoder in described decoder group.
Method the most according to claim 1, it is characterised in that described in the kth decoding cycle,
If after the FEC decoder in described decoder group receives subframe, in a described FEC decoder
Subframe reach n, the most described FEC decoder by described n subframe composition fec frame to be decoded,
And described fec frame to be decoded is carried out soft-decision FEC decoding；If a described FEC decoder receives
After subframe, the subframe in a described FEC decoder reach n+1, the most described FEC decoder
First the subframe arrived at first in a described FEC decoder is sent to the 2nd coupled FEC decoding
Device, then forms fec frame to be decoded by remaining n subframe, and carries out soft to described fec frame to be decoded
Judgement decoding, wherein, described k is the positive integer more than or equal to n, including:
If a described FEC decoder is after the kth decoding cycle receives a subframe, described first
Subframe in FEC decoder reaches n, and the most described FEC decoder is in described kth decoding week
The subframe that phase receives carries out inputting data bit width conversion process, determines the Soft Inform ation figure place of described subframe；Will
N-1 the sub-frame level deposited in the subframe and a described FEC decoder of data bit width conversion is unified into be treated
Decoding fec frame, carries out checking treatment by the transmission of described fec frame to be decoded to check-node more new module and obtains
Check-node information, described check-node information is for characterizing the error of each data bit in complete fec frame；
According to described check-node information, described fec frame to be decoded is carried out variable process, to described FEC to be decoded
Each data bit in frame carries out error correction to reduce error；
Or
If a described FEC decoder is after the kth decoding cycle receives a subframe, described first
Subframe in FEC decoder reaches n+1, and the most described FEC decoder is first by a described FEC
The subframe arrived at first in decoder is sent to the 2nd coupled FEC decoder, then to described
The subframe that k decoding cycle receives carries out inputting data bit width conversion process, determines the Soft Inform ation of described subframe
Figure place；By remaining n-1 subframe in the subframe converted through data bit width and a described FEC decoder
It is cascaded into fec frame to be decoded, the transmission of described fec frame to be decoded is verified to check-node more new module
Process obtains check-node information, and described check-node information is for characterizing each data bit in complete fec frame
Error；According to described check-node information, described fec frame to be decoded is carried out variable process, treat described
Each data bit in decoding fec frame carries out error correction to reduce error.
Method the most according to claim 2, it is characterised in that first a described FEC decoder will
The subframe arrived at first in a described FEC decoder is sent to the 2nd coupled FEC decoder, bag
Include:
Each data bit in described fec frame to be decoded carried out error correction after reducing error described, the
In k+1 decoding cycle, the son being initially received in n subframe of described fec frame to be decoded will be formed
Frame carries out outputs data bits width conversion process, will be sent to through this subframe of described data bit width change process
The 2nd FEC decoder being connected with a described FEC decoder.
4. according to the method according to any one of claim 1-3, it is characterised in that in described decoder group
Each decoder be connected in series into mutually row iteration soft-decision FEC decoding；
After each FEC decoder completes soft-decision FEC decoding, also include:
Current error-correcting performance is added up.
Method the most according to claim 4, it is characterised in that also include:
From described decoder group, the decoder at end receives subframe, and n subframe is integrated into a FEC
Frame.
6. the device realizing soft-decision forward error correction FEC decoding, it is characterised in that include data receiver
End and decoder group, wherein:
Described data receiver end is used for receiving multiple fec frame, and is decomposed into by each fec frame received
N subframe, subframe decomposition obtained sent to described decoder group, described n successively according to the decoding cycle
For positive integer；
Described decoder group includes decoder that is multiple that be connected step by step and that have identical encoded control logic,
Described encoded control logic includes: in the kth decoding cycle, if after receiving subframe, and described decoder
The subframe in a FEC decoder in group reach n, the most described FEC decoder is by described n
Individual subframe forms fec frame to be decoded, and described fec frame to be decoded is carried out soft-decision FEC decoding；As
Fruit is receiving after subframe, in a described FEC decoder subframe of storage reach n+1, the most described the
The subframe arrived at first in a described FEC decoder is sent to the decoding of next stage by one FEC decoder
Device, and a described FEC decoder is by remaining n subframe composition fec frame to be decoded, treats described
Decoding fec frame carries out Soft decision decoding, and wherein, k is the positive integer more than or equal to n, a described FEC
Decoder is any decoder in described decoder group.
Device the most according to claim 6, it is characterised in that a described FEC decoder includes:
Input data processing module, variable node more new module and check-node more new module, wherein:
The subframe received, for receiving subframe one by one, is carried out inputting data by described input data processing module
Bit wide conversion process, determines the Soft Inform ation figure place of described subframe；
Described variable node more new module is for by the subframe processed through described input data processing module and institute
State n-1 the sub-frame level deposited in a FEC decoder and be unified into fec frame to be decoded, by described FEC to be decoded
Frame sends to described check-node more new module；
Described check-node more new module is for receiving described FEC to be decoded from described variable node more new module
Frame carries out checking treatment, obtains check-node information, and described check-node information is used for characterizing described to be decoded
The error of each data bit in fec frame；
Described check-node more new module is additionally operable to according to described check-node information described fec frame to be decoded
Carry out variable process, each data bit in described fec frame to be decoded is carried out error correction to reduce error.
Device the most according to claim 7, it is characterised in that also wrap in a described FEC decoder
Include output data processing module, be used in described variable node more new module in described fec frame to be decoded
Each data bit carries out error correction to reduce after error, will form described FEC to be decoded in the next one decoding cycle
The subframe being initially received in n subframe of frame carries out outputs data bits width conversion process, will be through institute
State the 2nd FEC that this subframe of data bit width change process is sent to be in series with a described FEC decoder
Decoder.
9. according to the device according to any one of claim 6-8, it is characterised in that described device also includes
Performance statistic module, after completing soft-decision FEC decoding at every one-level FEC decoder, to current
Error-correcting performance is added up.
Device the most according to claim 9, it is characterised in that described device also includes integrating decoding
Device, described integration decoder connects with the decoder at end in described decoder group, for from described decoder
Group receives subframe, and n subframe is integrated into a fec frame.
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| CN106664154B (en) * | 2014-07-22 | 2019-10-22 | 华为技术有限公司 | Determine the method, apparatus and decoding system of forward error correction frame boundaries |
| WO2020257960A1 (en) * | 2019-06-24 | 2020-12-30 | Zte Corporation | Transceiver architectures for high-rate optical communication |
| CN110996309A (en) * | 2019-12-31 | 2020-04-10 | 大唐半导体科技有限公司 | Segmented decoding method of Bluetooth 5.0 protocol |
| CN111294061B (en) * | 2020-02-11 | 2021-01-05 | 上海威固信息技术股份有限公司 | Decoding soft decision delay reduction method for original bit error rate perception |
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| CN101436917A (en) * | 2007-11-12 | 2009-05-20 | 华为技术有限公司 | Method and apparatus for encoding and decoding data |
| CN101662335A (en) * | 2009-09-15 | 2010-03-03 | 中国人民解放军国防科学技术大学 | Forward error correction encoding method, forward error correction decoding method and devices thereof |
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| CN101662335A (en) * | 2009-09-15 | 2010-03-03 | 中国人民解放军国防科学技术大学 | Forward error correction encoding method, forward error correction decoding method and devices thereof |
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