CN103188027B - Frequency domain secondary synchronization code generation method and device thereof - Google Patents

Abstract

The present invention relates to the communications field, disclose a kind of frequency domain secondary synchronization code generation method and device thereof.In the present invention, in advance according to m ₀, m ₁with between specific corresponding relation, will span be divided into N section (namely 7 sections), when frequency domain secondary synchronization code need be generated, can directly according to m ₀, m ₁with between specific corresponding relation, by obtain rapidly corresponding m ₀, m ₁, and without the need to a series of multiplication by defining in standard, complementation with the arithmetic operation such as to round downwards and obtain required m ₀, m ₁.Thus greatly reduce the arithmetic operation generated needed for frequency domain secondary synchronization code, the generation of frequency domain secondary synchronization code is realized in the short period of time by less logic, effectively improves the formation efficiency of frequency domain secondary synchronization code.Preferably, utilize with or operate the multiplication replacing m sequence, further reducing the arithmetic operation generated needed for frequency domain secondary synchronization code, improve the formation efficiency of frequency domain secondary synchronization code.

Description

Frequency domain secondary synchronization code generation method and device thereof

Technical field

The present invention relates to the communications field, particularly the generation technique of secondary synchronization code.

Background technology

In long-term evolving network (LTE) system, the generative process of frequency domain secondary synchronization code is shown below:

$d_{Local}^{Fre}\left(2n\right)=\left\{\begin{array}{cc}{s}_0^{\left(m_0\right)}\left(n\right)c_0\left(n\right)& insubframe0\\ s_1^{\left(m_1\right)}\left(n\right)c_0\left(n\right)& insubframe5\end{array}\right.$

$d_{Local}^{Fre}(2n+1)=\left\{\begin{array}{cc}{s}_1^{\left(m_1\right)}\left(n\right)c_1\left(n\right)z_1^{\left(m_0\right)}\left(n\right)& insubframe0\\ s_0^{\left(m_0\right)}\left(n\right)c_1\left(n\right)z_1^{\left(m_0\right)}\left(n\right)& insubframe5\end{array}\right.$

$s_0^{\left(m_0\right)}\left(n\right)=\tilde{s}\left(\right(n+m_0\left)\mathrm{mod}31\right)$

$s_1^{\left(m_1\right)}\left(n\right)=\tilde{s}\left(\right(n+m_1\left)\mathrm{mod}31\right)$

$c_0\left(n\right)=\tilde{c}\left(\right(n+N_{ID}^{\left(2\right)}\left)\mathrm{mod}31\right)$

$c_1\left(n\right)=\tilde{c}\left(\right(n+N_{ID}^{\left(2\right)}+3\left)\mathrm{mod}31\right)$

$z_1^{\left(m_0\right)}\left(n\right)=\tilde{z}\left(\right(n+\left(m_0\mathrm{mod}8\right)\left)\mathrm{mod}31\right)$

$z_1^{\left(m_1\right)}\left(n\right)=\tilde{z}\left(\right(n+\left(m_1\mathrm{mod}8\right)\left)\mathrm{mod}31\right)$

n＝0,1,L,30

Wherein, in subframe 0 represents in subframe 0, and in subframe 5 represents in subframe 5, cell Identity CI in cell ID group, m ₀and m ₁by cell ID group number generate.

m ₀＝m′mod31

$\tilde{S}\left(i\right)=1-2x\left(i\right),0\≤i\≤30$

$x(\stackrel{\‾}{i}+5)=\left(x\right(\stackrel{\‾}{i}+2)+x\left(\stackrel{\‾}{i}\right))\mathrm{mod}2,0\≤\stackrel{\‾}{i}\≤25$

$\tilde{c}\left(i\right)=1-2x\left(i\right),0\≤i\≤30$

$x(\stackrel{\‾}{i}+5)=\left(x\right(\stackrel{\‾}{i}+3)+x\left(\stackrel{\‾}{i}\right))\mathrm{mod}2,0\≤\stackrel{\‾}{i}\≤25$

$\tilde{z}\left(i\right)=1-2x\left(i\right),0\≤i\≤30$

$x(\stackrel{\‾}{i}+5)=\left(x\right(\stackrel{\‾}{i}+4)+x(\stackrel{\‾}{i}+2)+x(\stackrel{\‾}{i}+1)+x\left(\stackrel{\‾}{i}\right))\mathrm{mod}2,0\≤\stackrel{\‾}{i}\≤25$

Wherein, the initial condition of sequence x is: x (0)=0, x (1)=0, x (2)=0, x (3)=0, x (4)=1.

Finally, be mapped to subcarrier, export and be ${\tilde{d}}_{Local}^{Fre}={\[{\tilde{d}}_{Local}^{Fre}\left(0\right),{\tilde{d}}_{Local}^{Fre}\left(1\right),...,{\tilde{d}}_{Local}^{Fre}\left(63\right)\]}^T.$

${\tilde{d}}_{Local}^{Fre}\left(n\right)=\left\{\begin{array}{cc}{d}_{Local}^{Fre}(n+30)& 1\≤n\≤31\\ d_{Local}^{Fre}(n-33)& 33\≤n\≤63\\ 0& n=0,n=32\end{array}\right.$

The present inventor finds, if directly produce secondary synchronization code according in standard to the definition of frequency domain secondary synchronization code, then needs a large amount of arithmetic operations, such as asks m ₀and m ₁process in the operation that has more multiplication, complementation and round downwards, therefore comparatively large to the consumption of system, the formation efficiency of frequency domain secondary synchronization code is lower.

Summary of the invention

The object of the present invention is to provide a kind of frequency domain secondary synchronization code generation method and device thereof, the arithmetic operation generated needed for frequency domain secondary synchronization code can be greatly reduced, thus the generation of frequency domain secondary synchronization code is realized in the short period of time by less logic, effectively improve the formation efficiency of frequency domain secondary synchronization code.

For solving the problems of the technologies described above, embodiments of the present invention provide a kind of frequency domain secondary synchronization code generation method, comprise following steps:

In advance according to cell ID group number with the corresponding relation of the generation parameter of frequency domain secondary synchronization code, described in inciting somebody to action span be divided into N section, described in same section with the generation parameter of described frequency domain secondary synchronization code, there is identical corresponding relation, described in different section from the generation parameter of described frequency domain secondary synchronization code, there is different corresponding relations; Wherein, the generation parameter of described frequency domain secondary synchronization code is m ₀and m ₁;

When frequency domain secondary synchronization code need be generated, according to current place section with the corresponding relation of the generation parameter of described frequency domain secondary synchronization code, obtain the generation parameter of described frequency domain secondary synchronization code;

According to the generation parameter of the described frequency domain secondary synchronization code obtained, generate described frequency domain secondary synchronization code.

Embodiments of the present invention additionally provide a kind of frequency domain secondary synchronization code generating apparatus, comprise:

Corresponding relation divides module, for according to cell ID group number with the corresponding relation of the generation parameter of frequency domain secondary synchronization code, described in inciting somebody to action span be divided into N section, described in same section with the generation parameter of described frequency domain secondary synchronization code, there is identical corresponding relation, described in different section from the generation parameter of described frequency domain secondary synchronization code, there is different corresponding relations; Wherein, the generation parameter of described frequency domain secondary synchronization code is m ₀and m ₁;

Generate parameter acquisition module, for when frequency domain secondary synchronization code need be generated, according to current place section with the corresponding relation of the generation parameter of described frequency domain secondary synchronization code, obtain the generation parameter of described frequency domain secondary synchronization code;

Secondary synchronization code generation module, for the generation parameter of described frequency domain secondary synchronization code obtained according to described generation parameter acquisition module, generates described frequency domain secondary synchronization code.

Embodiment of the present invention in terms of existing technologies, in advance according to m ₀, m ₁with between specific corresponding relation, will span be divided into N section (namely 7 sections), in same section with m ₀, m ₁there is identical corresponding relation, in different section with m ₀, m ₁there is different corresponding relations.Therefore, when frequency domain secondary synchronization code need be generated, can directly according to m ₀, m ₁with between specific corresponding relation, by obtain rapidly corresponding m ₀, m ₁, and without the need to a series of multiplication by defining in standard, complementation with the arithmetic operation such as to round downwards and obtain required m ₀, m ₁.Thus greatly reduce the arithmetic operation generated needed for frequency domain secondary synchronization code, the generation of frequency domain secondary synchronization code is realized in the short period of time by less logic, effectively improves the formation efficiency of frequency domain secondary synchronization code.

Preferably, according to current place section with the corresponding relation of the generation parameter of described frequency domain secondary synchronization code, when obtaining the generation parameter of described frequency domain secondary synchronization code, according to current the section at place, obtains in this section with m ₀between m in the first fixing difference pid_minus and this section ₀with m ₁between fixing the second difference m0_add; By current deduct the pid_minus of described acquisition, obtain described m ₀; By the described m obtained ₀add the m0_add of described acquisition, obtain described m ₁.Due in each divided section, with m ₀between difference, m ₀with m ₁between difference be all fixing, therefore utilize an adder and a subtracter to obtain m ₀and m ₁, realize rapidly simple, further increase the formation efficiency of frequency domain secondary synchronization code.

Preferably, will according to m ₀and m ₁c sequence needed for the local m sequence that cyclic shift obtains and frequency domain secondary synchronization code generate, z sequence are carried out with or are operated, and obtain the result that local m sequence is multiplied.Due in hardware implementing, by local m sequence and c sequence, z sequence being carried out with or operating, the result that local m sequence is multiplied with c sequence, z sequence can be obtained, therefore utilize with or operate the multiplication replacing m sequence, further reduce the arithmetic operation generated needed for frequency domain secondary synchronization code, improve the formation efficiency of frequency domain secondary synchronization code.

Accompanying drawing explanation

Fig. 1 generates method flow diagram according to the frequency domain secondary synchronization code of first embodiment of the invention;

Fig. 2 is according to asking for m by adder and subtracter in first embodiment of the invention ₀and m ₁schematic diagram;

Fig. 3 is the frequency domain secondary synchronization code generating apparatus structural representation according to third embodiment of the invention.

Embodiment

For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, persons of ordinary skill in the art may appreciate that in each execution mode of the present invention, proposing many ins and outs to make reader understand the application better.But, even without these ins and outs with based on the many variations of following execution mode and amendment, each claim of the application technical scheme required for protection also can be realized.

First execution mode of the present invention relates to a kind of frequency domain secondary synchronization code generation method.Frequency domain secondary synchronization code in present embodiment can be specially the frequency domain secondary synchronization code in time division duplex Long Term Evolution (TDD_LTE) system.

In the present embodiment, in advance according to cell ID group number with m ₀and m ₁corresponding relation, will described in span be divided into N section, described in same section with m ₀and m ₁there is identical corresponding relation, described in different section with m ₀and m ₁there is different corresponding relations.

Specifically, all possible value and corresponding m ₀and m ₁as shown in table 1:

Table 1

Can find from this table 1, with m ₀and m ₁there are 7 kinds of different corresponding relations, such as, time in [0,29] scope, always with m ₀it is identical, always than m ₁little by 1; time in [30,58] scope, always than m ₀large 30, always than m ₁large 28.Therefore, can in advance by span be divided into 7 sections, in same section with m ₀and m ₁there is identical corresponding relation, in different section with m ₀and m ₁there is different corresponding relations.As [0,29] are divided into one section, [30,58] are divided into another section, the rest may be inferred.

When frequency domain secondary synchronization code need be generated, generate frequency domain secondary synchronization code by flow process as shown in Figure 1.

In step 110, m is obtained ₀and m ₁.Specifically, according to current the section at place, obtains in this section with m ₀between m in the first fixing difference pid_minus and this section ₀with m ₁between fixing the second difference m0_add.By by current deduct the pid_minus of described acquisition, obtain m ₀; By the m that will obtain ₀add the m0_add of acquisition, obtain m ₁.

Due in the present embodiment, in advance will span to be divided into be 7 sections, m in each section ₀and m ₁with relation be all fixing.Therefore, in this step, current input need only to be determined the hop count at place, simultaneously according to m in this section ₀and m ₁with relation, can obtain in this section with m ₀between fixing the first difference pid_minus, and m in this section ₀with m ₁between fixing the second difference m0_add.Then, just subtract each other with pid_minus and obtain m ₀, by m ₀be added with m0_add and obtain m ₁, as shown in Figure 2.

Concrete logic is as follows:

// first by the span segmentation of nid_1

if(nid_1<8'd30)

nid_1_part＝3’d0；

else if(nid_1>8'd29&&nid_1<8'd59)

nid_1_part＝3’d1；

else if(nid_1>8'd58&&nid_1<8'd87)

nid_1_part＝3’d2；

else if(nid_1>8'd86&&nid_1<8'd114)

nid_1_part＝3’d3；

else if(nid_1>8'd113&&nid_1<8'd140)

nid_1_part＝3’d4；

else if(nid_1>8'd139&&nid_1<8'd165)

nid_1_part＝3’d5；

else

nid_1_part＝3’d6；

// obtain pid_minus according to nid_1_part

case(nid_1_part)

3’d0:

pid_minus＝nid_1；

3’d1:

pid_minus＝nid_1–8’d30；

3’d2:

pid_minus＝nid_1–8’d59；

3’d3:

pid_minus＝nid_1–8’d87；

3’d4:

pid_minus＝nid_1–8’d114；

3’d5:

pid_minus＝nid_1–8’d140；

default:

pid_minus＝nid_1–8’d165；

endcase

// obtain m0_add according to nid_1_part

case(nid_1_part)

3’d0:

m0_add＝3’d0；

3’d1:

m0_add＝3’d1；

3’d2:

m0_add＝3’d2；

3’d3:

m0_add＝3’d3；

3’d4:

m0_add＝3’d4；

3’d5:

m0_add＝3’d5；

default:

m0_add＝3’d6；

endcase

// deduct pid_minus with nid_1 to obtain m0

assign m0＝nid_1–pid_minus；

//m0 adds m0_add and obtains m1

assign m1＝m0+m0_add；

Above logic can be able to realize by an adder.As can be seen here, owing to can sum up from table 1 with m ₀, m ₁between specific rule, just can by given with a subtracter and an adder obtain m ₀, m ₁.Therefore m in hinge structure ₀, m ₁acquisition, greatly reduce required arithmetic operation, thus the generation of frequency domain secondary synchronization code realized in the short period of time by less logic, effectively improve the formation efficiency of frequency domain secondary synchronization code.

Then, in the step 120, the m will obtained ₀and m ₁carry out cyclic shift respectively, obtain local m sequence, that is:

$s_0^{\left(m_0\right)}\left(n\right)=\tilde{s}\left(\right(n+m_0\left)\mathrm{mod}31\right)$

$s_1^{\left(m_1\right)}\left(n\right)=\tilde{s}\left(\right(n+m_1\left)\mathrm{mod}31\right)$

$c_0\left(n\right)=\tilde{c}\left(\right(n+N_{ID}^{\left(2\right)}\left)\mathrm{mod}31\right)$

$c_1\left(n\right)=\tilde{c}\left(\right(n+N_{ID}^{\left(2\right)}+3\left)\mathrm{mod}31\right)$

$z_1^{\left(m_0\right)}\left(n\right)=\tilde{z}\left(\right(n+\left(m_0\mathrm{mod}8\right)\left)\mathrm{mod}31\right)$

$z_1^{\left(m_1\right)}\left(n\right)=\tilde{z}\left(\right(n+\left(m_1\mathrm{mod}8\right)\left)\mathrm{mod}31\right))$

n＝0,1,L,30

Because m sequence length is 31 bits, therefore above-mentioned formula is a cyclic shift of m sequence.

Then, in step 130, c sequence, z sequence needed for generating according to the local m sequence obtained and frequency domain secondary synchronization code, generate the result that local m sequence is multiplied.

Specifically, when producing m sequence, with 0 replacement-1, then the state transition diagram that is multiplied of m sequence is as shown in table 2 below:

Actual result/bear results	Sequence 1 value/replacement value	Sequence 2 values/replacement value
			1/1	-1/0	-1/0
-1/0	-1/0	1/1
			-1/0	1/1	-1/0
1/1	1/1	1/1

Table 2

The slash left side in table 2 represents the state transition diagram with multiplication, represents the state transition diagram after with 0 replacement-1 on the right of slash.Be not difficult to find, the c sequence needed for local m sequence and frequency domain secondary synchronization code are generated, z sequence carry out with or operation, the result that can obtain expecting (i.e. local m sequence be multiplied result).Such as, will sequence and c ₀(n) sequence carry out with or operation, subframe 0 can be obtained will sequence and c ₀(n) sequence carry out with or operation, subframe 5 can be obtained will sequence and c ₁(n) sequence, sequence carry out with or operation, subframe 0 can be obtained will sequence and c ₁(n) sequence, sequence carry out with or operation, subframe 5 can be obtained that is, by the c sequence needed for local m sequence and frequency domain secondary synchronization code are generated, z sequence carry out with or operation, can generate with the identical subframe 0 generated by following formula subframe 5 subframe 0 subframe 5

$d_{Local}^{Fre}\left(2n\right)=\left\{\begin{array}{cc}{s}_0^{\left(m_0\right)}\left(n\right)c_0\left(n\right)& insubframe0\\ s_1^{\left(m_1\right)}\left(n\right)c_0\left(n\right)& insubframe5\end{array}\right.$

$d_{Local}^{Fre}(2n+1)=\left\{\begin{array}{cc}{s}_1^{\left(m_1\right)}\left(n\right)c_1\left(n\right)z_1^{\left(m_0\right)}\left(n\right)& insubframe0\\ s_0^{\left(m_0\right)}\left(n\right)c_1\left(n\right)z_1^{\left(m_0\right)}\left(n\right)& insubframe5\end{array}\right.$

When specific implementation, realize by following hardware logic:

d_even_sub0＝(m_seq_end)？(m_seq_s0～^m_seq_c0):31'b0；

d_even_sub1＝(m_seq_end)？(m_seq_s1～^m_seq_c0):31'b0；

d_odd_sub0＝(m_seq_end)？(m_seq_s1～^m_seq_c1～^m_seq_z0):31'b0；

d_odd_sub1＝(m_seq_end)？(m_seq_s0～^m_seq_c1～^m_seq_z1):31'b0；

Wherein, d_even_sub0 represents subframe 0 d_even_sub1 represents subframe 5 d_odd_sub0 represents subframe 0 d_odd_sub1 represents subframe 5

Due in hardware implementing, by local m sequence and c sequence, z sequence being carried out with or operating, the result that local m sequence is multiplied with c sequence, z sequence can be obtained, therefore utilize with or operate the multiplication replacing m sequence, further reduce the arithmetic operation generated needed for frequency domain secondary synchronization code, improve the formation efficiency of frequency domain secondary synchronization code.

Then, in step 140, to result (the i.e. subframe 0 that the local m sequence generated is multiplied subframe 5 subframe 0 subframe 5 interweave, and carry out binary phase shift keying (Binary Phase Shift Keying is called for short " BPSK ") modulation after interleaving, obtain frequency domain secondary synchronization code.This step is same as the prior art, does not repeat them here.

Be not difficult to find, in the present embodiment, the adder less with area and subtracter achieve utilization ask parameter m ₀and m ₁process, with or being multiplied of multiple m sequence of logic realization, utilize a counter to complete intertexture within 64 cycles, BPSK modulates mapping, creates frequency domain secondary synchronization sequences.The generation of local auxiliary synchronous signals is completed in a short period of time by very little logic.Due to without the need to a series of multiplication by defining in standard, complementation with the arithmetic operation such as to round downwards and obtain required m ₀, m ₁.Thus greatly reduce the arithmetic operation generated needed for frequency domain secondary synchronization code, the generation of frequency domain secondary synchronization code is realized in the short period of time by less logic, effectively improves the formation efficiency of frequency domain secondary synchronization code.And, utilize an adder and a subtracter to obtain m ₀and m ₁, realize rapidly simple, further increase the formation efficiency of frequency domain secondary synchronization code.

Second execution mode of the present invention relates to a kind of frequency domain secondary synchronization code generation method.Second execution mode is roughly the same with the first execution mode, and main distinction part is: in the first embodiment, according to current place section with m ₀and m ₁corresponding relation obtain m ₀and m ₁time, be obtain m by an adder and a subtracter ₀and m ₁.And in second embodiment of the invention, by with under type according to current place section with m ₀and m ₁corresponding relation obtain m ₀and m ₁:

Prestore with m ₀and m ₁mapping table, comprise in this mapping table all possible value, each the corresponding m of value ₀with a m ₁.According to current place section obtain m ₀and time, according to current value search described mapping table, obtain with current corresponding m ₀and m ₁.

Be not difficult to find, in the present embodiment, equally without the need to a series of multiplication by defining in standard, complementation with the arithmetic operation such as to round downwards and obtain required m ₀, m ₁.Thus greatly reduce the arithmetic operation generated needed for frequency domain secondary synchronization code, the generation of frequency domain secondary synchronization code is realized in the short period of time by less logic, effectively improves the formation efficiency of frequency domain secondary synchronization code.

It should be noted that, above the step of various method divide, just in order to be described clearly, a step can be merged into when realizing or some step is split, be decomposed into multiple step, as long as comprise identical logical relation, all in the protection range of this patent; To adding inessential amendment in algorithm or in flow process or introducing inessential design, but the core design not changing its algorithm and flow process is all in the protection range of this patent.

Third embodiment of the invention relates to a kind of frequency domain secondary synchronization code generating apparatus, specifically can be used for generating the frequency domain secondary synchronization code in time division duplex long evolving system.The concrete structure of present embodiment as shown in Figure 3, comprises:

Corresponding relation divides module, for according to cell ID group number with the corresponding relation of the generation parameter of frequency domain secondary synchronization code, described in inciting somebody to action span be divided into N section, described in same section with the generation parameter of described frequency domain secondary synchronization code, there is identical corresponding relation, described in different section from the generation parameter of described frequency domain secondary synchronization code, there is different corresponding relations; Wherein, the generation parameter of described frequency domain secondary synchronization code is m ₀and m ₁.

Generate parameter acquisition module, for when frequency domain secondary synchronization code need be generated, according to current place section with the corresponding relation of the generation parameter of described frequency domain secondary synchronization code, obtain the generation parameter of described frequency domain secondary synchronization code.

Secondary synchronization code generation module, for the generation parameter of described frequency domain secondary synchronization code obtained according to described generation parameter acquisition module, generates described frequency domain secondary synchronization code.

Wherein, generate parameter acquisition module and comprise following submodule:

Difference obtains submodule, for according to current the section at place, obtains in this section with m ₀between m in the first fixing difference pid_minus and this section ₀with m ₁between fixing the second difference m0_add;

Subtraction submodule, for by current deduct the pid_minus of described acquisition, obtain described m ₀;

Addition submodule, for the described m that will obtain ₀add the m0_add of described acquisition, obtain described m ₁.

Secondary synchronization code generation module comprises:

Cyclic shift submodule, for the described m that will obtain ₀and m ₁carry out cyclic shift respectively, obtain local m sequence;

Multiplied result obtains submodule, for c sequence, z sequence needed for the described local m sequence obtained and frequency domain secondary synchronization code generation, generates the result that local m sequence is multiplied;

Modulation submodule, interweaves for the result be multiplied to the described local m sequence generated, and carries out binary phase shift keying BPSK modulation after interleaving, obtain frequency domain secondary synchronization code.

It is worth mentioning that, this multiplied result obtain submodule described local m sequence and frequency domain secondary synchronization code are generated needed for c sequence, z sequence carry out with or after obtain the result that described local m sequence is multiplied.

Be not difficult to find, present embodiment is the system embodiment corresponding with the first execution mode, and present embodiment can be worked in coordination with the first execution mode and be implemented.The relevant technical details mentioned in first execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment also can be applicable in the first execution mode.

It should be noted that, each module involved in present embodiment is logic module, and in actual applications, a logical block can be a physical location, also can be a part for a physical location, can also realize with the combination of multiple physical location.In addition, in order to outstanding innovative part of the present invention, the unit not too close with solving technical problem relation proposed by the invention is not introduced in present embodiment, but this does not show the unit that there is not other in present embodiment.

Persons of ordinary skill in the art may appreciate that the respective embodiments described above realize specific embodiments of the invention, and in actual applications, various change can be done to it in the form and details, and without departing from the spirit and scope of the present invention.

Claims (9)

1. a frequency domain secondary synchronization code generation method, is characterized in that, comprise following steps:

In advance according to cell ID group number with the corresponding relation of the generation parameter of frequency domain secondary synchronization code, described in inciting somebody to action span be divided into N section, described in same section with the generation parameter of described frequency domain secondary synchronization code, there is identical corresponding relation, described in different section from the generation parameter of described frequency domain secondary synchronization code, there is different corresponding relations; Wherein, the generation parameter of described frequency domain secondary synchronization code is m ₀and m ₁;

When frequency domain secondary synchronization code need be generated, according to current place section with the corresponding relation of the generation parameter of described frequency domain secondary synchronization code, obtain the generation parameter of described frequency domain secondary synchronization code;

According to the generation parameter of the described frequency domain secondary synchronization code obtained, generate described frequency domain secondary synchronization code;

Wherein, described according to current place section with the corresponding relation of the generation parameter of described frequency domain secondary synchronization code, obtain, in the step of generation parameter of described frequency domain secondary synchronization code, comprising following sub-step:

According to current the section at place, obtains in this section with m ₀between m in the first fixing difference pid_minus and this section ₀with m ₁between fixing the second difference m0_add;

By current deduct the pid_minus of described acquisition, obtain described m ₀;

By the described m obtained ₀add the m0_add of described acquisition, obtain described m ₁.

2. frequency domain secondary synchronization code generation method according to claim 1, is characterized in that,

Prestore mapping table with the generation parameter of frequency domain secondary synchronization code, comprises in this mapping table all possible value, each the corresponding m of value ₀with a m ₁;

According to current place section with the corresponding relation of the generation parameter of described frequency domain secondary synchronization code, when obtaining the generation parameter of described frequency domain secondary synchronization code, according to current value search described mapping table, obtain with current corresponding m ₀and m ₁.

3. frequency domain secondary synchronization code generation method according to claim 1, is characterized in that, the generation parameter of the described frequency domain secondary synchronization code that described basis obtains, generates in the step of described frequency domain secondary synchronization code, comprise following sub-step:

By the described m obtained ₀and m ₁carry out cyclic shift respectively, obtain local m sequence;

C sequence, z sequence needed for generating according to the described local m sequence obtained and frequency domain secondary synchronization code, generate the result that local m sequence is multiplied;

The result that the described local m sequence generated is multiplied is interweaved, and carries out binary phase shift keying BPSK modulation after interleaving, obtain frequency domain secondary synchronization code.

4. frequency domain secondary synchronization code generation method according to claim 3, it is characterized in that, c sequence, z sequence needed for generating according to the described local m sequence obtained and frequency domain secondary synchronization code, generate in the step of the result that local m sequence is multiplied, comprise following sub-step:

C sequence needed for described local m sequence and frequency domain secondary synchronization code being generated, z sequence are carried out with or operate, and obtain the result that described local m sequence is multiplied.

5. frequency domain secondary synchronization code generation method according to any one of claim 1 to 4, is characterized in that,

Described frequency domain secondary synchronization code is the frequency domain secondary synchronization code in time division duplex long evolving system.

6. a frequency domain secondary synchronization code generating apparatus, is characterized in that, comprises:

Corresponding relation divides module, for according to cell ID group number with the corresponding relation of the generation parameter of frequency domain secondary synchronization code, described in inciting somebody to action span be divided into N section, described in same section with the generation parameter of described frequency domain secondary synchronization code, there is identical corresponding relation, described in different section from the generation parameter of described frequency domain secondary synchronization code, there is different corresponding relations; Wherein, the generation parameter of described frequency domain secondary synchronization code is m ₀and m ₁;

Generate parameter acquisition module, for when frequency domain secondary synchronization code need be generated, according to current place section with the corresponding relation of the generation parameter of described frequency domain secondary synchronization code, obtain the generation parameter of described frequency domain secondary synchronization code;

Secondary synchronization code generation module, for the generation parameter of described frequency domain secondary synchronization code obtained according to described generation parameter acquisition module, generates described frequency domain secondary synchronization code;

Wherein, described generation parameter acquisition module comprises following submodule:

Difference obtains submodule, for according to current the section at place, obtains in this section with m ₀between m in the first fixing difference pid_minus and this section ₀with m ₁between fixing the second difference m0_add;

Subtraction submodule, for by current deduct the pid_minus of described acquisition, obtain described m ₀;

Addition submodule, for the described m that will obtain ₀add the m0_add of described acquisition, obtain described m ₁.

7. frequency domain secondary synchronization code generating apparatus according to claim 6, is characterized in that, described secondary synchronization code generation module comprises:

Cyclic shift submodule, for the described m that will obtain ₀and m ₁carry out cyclic shift respectively, obtain local m sequence;

Multiplied result obtains submodule, for c sequence, z sequence needed for the described local m sequence obtained and frequency domain secondary synchronization code generation, generates the result that local m sequence is multiplied;

Modulation submodule, interweaves for the result be multiplied to the described local m sequence generated, and carries out binary phase shift keying BPSK modulation after interleaving, obtain frequency domain secondary synchronization code.

8. frequency domain secondary synchronization code generating apparatus according to claim 7, it is characterized in that, described multiplied result obtain submodule described local m sequence and frequency domain secondary synchronization code are generated needed for c sequence, z sequence carry out with or after obtain the result that described local m sequence is multiplied.

9. the frequency domain secondary synchronization code generating apparatus according to any one of claim 6 to 8, is characterized in that,

Described frequency domain secondary synchronization code is the frequency domain secondary synchronization code in time division duplex long evolving system.