CN103186360A - Fast arithmetic multi-bit serial pulse dual-base binary finite field multiplier - Google Patents

Abstract

The invention relates to a fast arithmetic multi-bit serial pulse dual-base binary finite field multiplier, comprising an input end B, k PE modules, an FRRP module and an R3 module. The k PE modules are connected in series, the k PE modules pass through k cycles, in the first cycle, the input of A is that B is directly input, and the calculation result is restored and input into a temporary register C through the FRRP module; in the second cycle, the input of A is that B is input through the R3 module, the calculation result is also restored through the FRRP module, and is added to the calculation result of the first cycle and stored in the temporary register C; so, in the k cycle, the input of A is that B is input after passing through the R3 module for (k-1) times, the calculation result is restored through the FRRP module, added to the accumulation result of the previous (k-1) times and stored in the temporary register C, and the temporary register C outputs the result.

Description

Fast operation multi-bit serial pulse double-base binary finite field multiplier

Technical Field

The present invention relates to a binary finite field multiplier, and more particularly, to a fast operation multi-bit serial pulse binary finite field multiplier with dual bases.

Background

In recent years, ellipsesCircular curve cryptography (ECC) [1 ]],[2]Has been linked to the study of cryptography. With the advent of elliptic curve cryptography in public key cryptosystems, some hardware implementation issues have been raised on the application of ECC. NIST recommends 5 binary fields, GF (2)¹⁶³),GF(2²³³),GF(2²⁸³),GF(2⁴⁰⁹),and GF(2⁵⁷¹). In the cryptographic protocol based on the ECC base, there is a field multiplication which is an indispensable element of the computation cost. The availability of cryptographic system hardware generally affects area, power consumption, and performance.

For the implementation of very-large-scale integration (VLSI), systolic array architecture is the better choice. In the extended two-bit field, a variety of efficient systolic array multipliers have been designed and can be categorized as bit parallel and as series mechanisms. Efficient bit-parallel systolic multipliers typically employ either the LSB first or MSB first algorithm. The main advantage of the bit-parallel systolic multiplier is the connectivity throughout the computation. However, these structures require O (m) for the bibit field based polynomial²)XOR，O(m²)AND，O(m²) One bit latch and o (m) delay complexity. To reduce temporal and spatial complexity, LEE [8],[9],[13]The algorithm shows that field multiplication can be used for establishing a full-parallel systolic multiplier by Toeplitz matrix-vector multiplication (TMVP) for special polynomials such as all-one polynomial, five-term polynomial and three-term polynomial. Bit-cascaded systolic array multipliers require the spatial complexity of o (m), but they result in longer computational delays.

For a trade-off between temporal and spatial complexity, digital serial systolic multipliers have been disclosed between being parallel and being series multipliers. A digital serial conversion polynomial based multiplier based on an internal digital and external parallel architecture is described in [20 ]]Is set forth in (1). In such a multiplier, m bits of the element field length can be subdivided

A sub-segment of length d. In each clock cycle, a string of d bits is computed and a multiplication of m bits is computed. An expandable and systolic multiplier has been developed [15 ] using an inherent parallel hank vector matrix of d x d bits],[16]The delay of which is

One clock cycle. The use of different structures inside and outside the multi-bit serial ripple multiplier is presented in the literature. The delays of these multipliers areA clock cycle. As mentioned earlier, the design of low complexity systolic finite field multipliers depends on the choice of irreducible polynomials and the choice of representation bases, which require high delays to implement the multiplication calculations.

Disclosure of Invention

The technical problem solved by the invention is as follows: a fast operation multi-bit serial pulse double-base binary finite field multiplier is constructed, and the technical problem that the conventional multiplier needs high delay to realize multiplication calculation is solved.

The technical scheme of the invention is as follows: a fast operation multi-bit serial pulse double-base binary finite field multiplier is constructed, and comprises B, k PE modules, an FRRP module and an R3 module at input ends, wherein the k PE modules are connected in series, the k PE modules are connected in series through k periods, and the input of the 1 st period A is A₀、A₁、...、A_k-1B, directly inputting, and restoring and inputting a calculation result into a temporary storage C through the FRRP module; input A of 2 nd cycle A_k、A_k+1、…、A_2k-1B is input through the R3 module, the calculation result is also restored through the FRRP module, and is added with the calculation result of the 1 st period and is stored in the temporary storage C; thus, for the k-th cycle, the input to A isB is input after passing through the R3 module for (k-1) times, a calculation result is restored through the FRRP module, is added with the accumulated result for (k-1) times, is stored in a temporary storage C, and then the result is output by the temporary storage C, the R3 module realizes Bx^kdmod F (x), the PE modules include R1 module, CMP module, CVP module, PWM module,

An exclusive OR gate, andthe R3 module is output to the R1 module and then undergoes coefficient conversion by the CMP module, the A segment is input to the CVP module to undergo coefficient conversion of the A segment, and the calculation results of the CMP module and the CVP module are input to the PWM module to realize B_inAnd A segment product calculation by

Accumulated by an exclusive-or gate, the result being stored inIn a latch, is composed of

Latch output result

Wherein a is represented by a trinomial polynomial f (x) =1+ xⁿ+x^mIs expressed as A = a₀+a₁x+...+a_m-1x^m-1There are m coefficients, i.e. (a)₀,a₁,...,a_m-1). Cutting m-bit A into pieces by using a segmentation cutting method

Each segment has d bits and total k²Is segmented, thus having

B may be represented by double base as B = B₀β₀+b₁β₁+...+b_m-1β_m-1As the other input of the multiplier; and C is an output result.

The further technical scheme of the invention is as follows: the FRRP module comprises an FR module, an R2 module, the R2 module realizes Cmod (x)^m+1), the input of the FR module is the calculation result of k series PE modules, and the result is restored and output to the R2 module.

The further technical scheme of the invention is as follows: the CMP module comprises exclusive-OR gates XOR _1 and XOR _2, and the exclusive-OR gates XOR _1 and XOR _2 are connected in parallel.

The further technical scheme of the invention is as follows: the CVP module is an exclusive OR gate XOR _ 3.

The further technical scheme of the invention is as follows: the PWM module comprises three AND gates AND _1, AND _2 AND AND _3 which are connected in parallel. And point-to-point multiplying the results output by the CMP module and the CVP module.

The further technical scheme of the invention is as follows: the FR-module comprises two parallel exclusive or gates XOR _4 and XOR _ 5.

The invention has the technical effects that: constructing a fast operation multi-bit serial pulse double-base binary finite field multiplier, which comprises B, k PE modules at input ends, an FRRP module and an R3 module, wherein the k PE modules are connected in series, the k PE modules pass through k periods, and the input of the 1 st period A is (A)₀,A₁,…A_k-1) B, directly inputting, and restoring and inputting a calculation result into a temporary storage C through the FRRP module; input of 2 nd cycle A (A)_k,A_k+1,…,A_2k-1) B is input through the R3 module, the calculation result is also restored through the FRRP module, and is added with the calculation result of the 1 st period and is stored in the temporary storage C; thus, for the k-th cycle, the input to A is

B is input after passing through the R3 module for (k-1) times, a calculation result is restored through the FRRP module, added with the accumulated result for (k-1) times, stored in the temporary storage C, and then the result is output by the temporary storage C. Some live multiplications can be obtained in a bit-parallel structure through the sub-subspace TMVP. In a binary field GF (2)^m) The irresolvable three-term polynomial and the five-term polynomial are widely used in the field of cryptography, and the bit length is usually large in such fields. The proposed architecture can go to very low levels once a d x d Toeplitz multiplication is selected by using the quadratic TMVP equation through a new digital concatenation new station shrink double-base multiplier

A clock cycle.

Drawings

FIG. 1 is a schematic structural diagram of the present invention.

Fig. 2 is a diagram of a multi-bit serial ripple multiplier according to the present invention.

Fig. 3 is a block diagram of the processing unit PE according to the present invention.

FIG. 4 is a specific circuit diagram of the PE module according to the present invention.

Detailed Description

The technical solution of the present invention is further illustrated below with reference to specific examples.

As shown in fig. 2, the embodiment of the present invention is: a fast operation multi-bit serial pulse double-base binary finite field multiplier is constructed, and comprises B, k PE modules, an FRRP module and an R3 module at input ends, wherein the k PE modules are connected in series, and the k PE modules are connected in seriesOver k cycles, the input for the 1 st cycle A is A₀、A₁、…、A_k-1B, directly inputting, and restoring and inputting a calculation result into a temporary storage C through the FRRP module; input A of 2 nd cycle A_k、A_k+1、…、A_2k-1B is input through the R3 module, the calculation result is also restored through the FRRP module, and is added with the calculation result of the 1 st period and is stored in the temporary storage C; thus, for the k-th cycle, the input to A is

B is input after passing through the R3 module for (k-1) times, a calculation result is restored through the FRRP module, is added with the accumulated result for (k-1) times, is stored in a temporary storage C, and then the result is output by the temporary storage C, the R3 module realizes Bx^kdmod F (x), the PE modules include R1 module, CMP module, CVP module, PWM module,

An exclusive OR gate, andthe R3 module is output to the R1 module and then undergoes coefficient conversion by the CMP module, the A segment is input to the CVP module to undergo coefficient conversion of the A segment, and the calculation results of the CMP module and the CVP module are input to the PWM module to realize B_inAnd A segment product calculation by

Accumulated by an exclusive-or gate, the result being stored in

In a latch, is composed of

Latch output result

Wherein A is a trinomial polynomialF(x)=1+xⁿ+x^mIs expressed as A = a₀+a₁x+...+a_m-1x^m-1There are m coefficients, i.e. (a)₀,a₁,...,a_m-1). Cutting m-bit A into pieces by using a segmentation cutting method

Each segment has d bits and total k²Is segmented, thus having

B may be represented by double base as B = B₀β₀+b₁β₁+...+b_m-1β_m-1As the other input of the multiplier; and C is an output result.

The preferred embodiments of the present invention are: the FRRP module comprises an FR module, an R2 module, the R2 module realizes Cmod (x)^m+1), the input of the FR module is the calculation result of k series PE modules, and the result is restored and output to the R2 module.

The inputs of the CMP module and the CVP module are B_inAnd

the output result is used as the input of the PWM module, and the output of the PWM module passes throughAn exclusive OR gate, and

a latch for outputting the result

The input to the R1 module is B_inThe output passes through m latches and outputs a result B_out. The input to the CMP module is Bx^dk(i+1)+jdThe output is [ B ]^(p+q),B(^p+q+1),...,B^(p+q+d-1)]The input of the CVP module is A_ik+jOutput is [ a_q,a_q+1,...,a_q+d-1]^TWherein

To represent

The number of rows and columns arranged in a matrix, i, j =0, 1.. the k-1, i denotes the ith row of the matrix, j denotes the jth column of the matrix, p denotes dk (i +1) + jd, q denotes (ik + j) d, and T denotes [ a ], [_q,a_q+1,...,a_q+d-1]Transposing of the matrix. The output result is accumulated with the result of the previous FRRP module and output to the next FRRP module.

The whole structure of the double-base multiplication is shown in the structure of the double-base multiplier of the systolic array of FIG. 1, A, B and C are three in GF (2)^m) By an undecomposed trinomial polynomial F (x) =1+ xⁿ+x^mWherein n is less than or equal to m/2. Element a is represented by a polynomial base representation, B and C are represented by a dual base representation, and the entire multiplier implements the C = abmodf (x) function, with A, B as input and C as output result. A by a trinomial polynomial f (x) =1+ xⁿ+x^mIs expressed as A = a₀+a₁x+...+a_m-1x^m-1There are m coefficients, i.e. (a)₀,a₁,...,a_m-1). Cutting m-bit A into pieces by using a segmentation cutting methodEach segment has d bits and total k²Is segmented, thus havingEach segment Ai may be denoted A_i=a_id+a_id+1x+…+a_id+d-1x^d-1All segments

Instead of a as input to the entire multiplier. B may be represented by double base as B = B₀β₀+b₁β₁+...+b_m-1β_m-1As the other input to the multiplier. C is the output result, calculated by C = abmodf (x), i.e. the function implemented by the whole multiplier.

Since A is divided intoSo A can be represented as $A=A_0+A_1{x}^d+...+A_{k^2-1}{x}^{(k^2-1)d}.$ Thus unfolding a in C = abmodf (x) can yield:

wherein $\begin{array}{c}C=\mathrm{AB}\mathrm{mod}F\left(x\right)\\ =B(A_0+A_1{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;{+A}_{k^2-1}{x}^{(k^2-1)d})\mathrm{mod}F\left(x\right)\\ =\left(B(A_0+A_1{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{k-1}{x}^{(k-1)d}\right)+\\ {\mathrm{Bx}}^{\mathrm{dk}}(A_k+A_{k+1}{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{2k-1}{x}^{(k-1)d})+\\ \&CenterDot;\&CenterDot;\&CenterDot;+\\ {\mathrm{Bx}}^{\mathrm{dk}(k-1)}(A_{k(k-1)}+A_{k(k-1)+1}{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{k^2-1}{x}^{(k-1)d}))\mathrm{mod}F\left(x\right)\\ =({\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="130403102318.png"\; state="\{\{state\}\}">C</figure-callout>}}_0+{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+\&CenterDot;\&CenterDot;\&CenterDot;+C_{k-1})\mathrm{mod}F\left(x\right)\\ {\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="130403102318.png"\; state="\{\{state\}\}">C</figure-callout>}}_0=B(A_0+A_1{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{k-1}{x}^{(k-1)d})\\ {\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">C</figure-callout>}}_1={\mathrm{Bx}}^{\mathrm{dk}}(A_k+A_{k+1}{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{2k-1}{x}^{(k-1)d})\\ \&CenterDot;\&CenterDot;\&CenterDot;\\ C_{k-1}={\mathrm{Bx}}^{\mathrm{dk}(k-1)}(A_{k(k-1)}+A_{k(k-1+1)}{x}^d+\&CenterDot;\&CenterDot;\&CenterDot;+A_{k^2-1}{x}^{(k-1)d})\end{array}$

In the overall multiplier structure of FIG. 1, C is calculated in line 1₀=B(A₀+A₁x^d+…+A_k-1x^(k-1)d) Its 1 st processing element PE_0,0Calculating BA₀Product result2 nd processing element PE_0,1Calculating BA₁x^dThe result of the multiplication, and so on, the k-th processing element PE_0,k-1Calculating BA_k-1x^(k-1)dAnd (4) multiplying the result. The calculation results of the whole k processing units are accumulated again to finally obtain C₀And input to the 1 st FRRP (FinalReconstruction-Reduction-Polymer) module. Likewise, line 2 of the overall multiplier structure calculates C₁=Bx^dk(A_k+A_k+1x ^d+…+A_2k-1x^(k-1)d) Incremental R3 modular calculation Bx^dkmod F (x), whose input is B. Its 1 st processing element PE_1,0Calculating Bx^dxA₀The result of the multiplication, subsequently similar to line 1, is calculated as result C₁Input to the 2 nd FRRP module, and then add up to the 1 st FRRP module to obtain (C)₀+C₁) mod F (x). Each line of the whole multiplier carries out similar calculation until the k line, and the output result of the R3 module is Bx^dk(k-1)mod F (x), the kth FRRP module input is C_k-1The output is (C)₀+C₁+…+C_k-1) mod F (x), which is the whole multiplier operation result C = (C)₀+C₁+…+C_k-1)modF(x)。

The detailed circuit of each processing unit PEi, j, as shown in fig. 2, is used to calculate Bx^dk(i+1)+jdA_ik+jAnd (4) multiplying the result. A. the_in、B_inAnd

as input, B_outAndas an output. For the 1 st processing element PE of each row_i,0Of which A is_inInput is A_ik，B_inIs output from the (i +1) th R3 module, namely Bx^dk(i+1)mod F (x), and

the initialization is 0. B is_outThe output of R1 is also 2 ndA processing unit PE_i,1The result of the output is Bx^dk(i+1)+dmodF(x)。

Output is

As a result of (1), i.e. calculating Bx^dk(i+1)A_ikAnd (4) multiplying the result. The 2 nd processing element PE per row_i,1Of which A is_inInput is A_ik+1，B_inInput is Bx^dk(i+1)+dmodF(x)，

Input is the 1 st processing element PE_i,0The result of the calculation is Bx^dk(i+1)A_ikAs the 3 rd processing element PE_i,1Is inputted

B_outOutput is Bx^dk(i+1)+2dmod F (x) the result of the calculation as the 3 rd processing element PE_i,1Input B of_in，

Output is Bx^dk(i+1)+dA_ik+1And (4) multiplying the result. By analogy, the j +1 processing element PE in each row_i,jCalculated is Bx^dk(i+1)+jdA_ik+jProduct result, A thereof_inInput is A_ik+j，B_inInput is Bx^dk(i+1)+jdmodF(x)，

Input to the jth module

Output the result as Bx^{dk(i+1)+(j-1)d}A_ik+(j-1)，B_outOutput is Bx^{dk(i+1)+(j+1)d}mod f (x) the result of the calculation,

output is Bx^dk(i+1)+jdA_ik+jAnd (4) multiplying the result.

Mix Bx^dk(i+1)+jdAnd A_ik+jAre separately unfolded, i.e. Bx^dk(i+1)+jd=(b₀β₀+b₁β₁+…+b_m-1β_m-1)x^dk(i+1)+jd，A_ik+j=a_(ik+j)d+a_(ik+j)d+1x+…+a_(ik+j)d+d-1x^d-1 _,According to the double-base multiplication rule, the following results are obtained:

Bx^dk(i+1)+jdA_ik+j

=(b₀β₀+b₁β₁+…+b_m-1β_m-1)x^dk(i+1)+jdA_ik+j

=(b₀ ^(p)β₀+b₁ ^(p)β₁+…b_m-1 ^(p)β_m-1)A_ik+j

=(a_(ik+j)d+a_(ik+j)d+1x+…+a_(ik+j)d+d-1x^d-1)B^(p)

=a_qB^(p)+a_q+1xB^(p)+…+a_q+d-1x^d-1B^(p)

=a_qB^(p+q)+a_q+1B(^p+q+1)+…+a_q+d-1B^(p+q+d-1)

=[B^(p+q),B^(p+q+1),...,B^(p+q+d-1)][a_q,a_q+1,...,a_q+d-1]^T

p=dk(i+1)+jd

wherein q = (ik + j) d

B^(p)=b₀ ^(p)β₀+b₁ ^(p)β₁+…+b_m-1 ^(p)β_m-1

FIG. 3 processing element PE_i,jIn the detailed circuit of (1), the input of the CMP module is Bx^dk(i+1)+jdThe output is [ B ]^(p+q),B^(p+q+1),...,B^(p+q+d-1)]The input of the CVP module is A_ik+jOutput is [ a_q,a_q+1,...,a_q+d-1]^TThe PWM module is used for calculating [ B^(p+q),B^(p+q+1),...,B^(p+q+d-1)][a_q,a_q+1,...,a_q+d-1]^TThe result of the multiplication is then summed with

Adding the result to a register L and outputting the result from the register LThe input to the R1 module is B_inRealization of x^dB_inmod F (x) operation, the result is stored in register L, which is used as B_outAnd (6) outputting.

In calculating [ B^(p+q),B^(p+q+1),...,B^(p+q+d-1)][a_q,a_q+1,...,a_q+d-1]^TDue to Toeplitz matrix-vector product, split into $\left[\begin{array}{cc}{t}_1& t_2\\ t_0& t_1\end{array}\right]\left[\begin{array}{c}{v}_0\\ {\mathrm{<figure-callout\; id="1"\; label="v"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">v</figure-callout>}}_1\end{array}\right],$ ( $\left[\begin{array}{cc}{t}_1& t_2\\ t_0& {\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">t</figure-callout>}}_1\end{array}\right]$ Represents the Toeplitz matrix [ B^(p+q),B^(p+q+1),...,B^(p+q+d-1)]Divided into four blocks, two of which are identical and are t₁The other two blocks are t₀And t₂， $\left[\begin{array}{c}{v}_0\\ {\mathrm{<figure-callout\; id="1"\; label="v"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">v</figure-callout>}}_1\end{array}\right]$ Will vector [ a_q,a_q+1,...,a_q+d-1]^TDivided into two segments, T representing a matrix transpose, where one can obtain

$=[B^{(p+q)},B^{(p+q+1)},...,B^{(p+q+d-1)}][a_q,a_{q+1},...,a_{q+d-1}{]}^T$

$=\left[\begin{array}{cc}{t}_1& t_2\\ t_0& t_1\end{array}\right]\left[\begin{array}{c}{v}_0\\ {\mathrm{<figure-callout\; id="1"\; label="v"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">v</figure-callout>}}_1\end{array}\right]=\left[\begin{array}{c}{t}_1({\mathrm{<figure-callout\; id="0"\; label="v"\; filenames="130403102318.png"\; state="\{\{state\}\}">v</figure-callout>}}_0+v_1)+v_1(t_2+t_1)\\ t_1({\mathrm{<figure-callout\; id="0"\; label="v"\; filenames="130403102318.png"\; state="\{\{state\}\}">v</figure-callout>}}_0+v_1)+v_0({\mathrm{<figure-callout\; id="0"\; label="t"\; filenames="130403102318.png"\; state="\{\{state\}\}">t</figure-callout>}}_0+t_1)\end{array}\right]$

$=\left[\begin{array}{c}{c}_0\\ {\mathrm{<figure-callout\; id="1"\; label="c"\; filenames="130403102318.png,130403102327.png"\; state="\{\{state\}\}">c</figure-callout>}}_1\end{array}\right]$

Fig. 4 shows the CMP, CVP and PWM specific circuits of the processing unit PE. The input to the CMP module is (t)₀,t₁,t₂) Input (t) via exclusive or gates XOR _1 and XOR _2₀+t₁,t₁,t₁+t₂) (ii) a The CVP module inputs (v)₀,v₁) Is input (v) via an exclusive or gate XOR _3₀,v₀+v₁,v₁) (ii) a The PWM module multiplies the results output by the CMP module AND the CVP module point to point, passes through 3 AND gates AND _1, AND _2 AND AND _3 AND outputs (v)₀(t₀+t₁),t₁(v₀+v₁),v₁(t₂+t₁) ); the FR reduction module calculates c by using 2 exclusive OR gates XOR _4 and XOR _5₀=t₁(v₀+v₁)+v₁(t₂+t₁) And c₁=t₁(v₀+v₁)+v₀(t₀+t₁) Output (c)₀,c₁)。

Fig. 2 shows a multi-bit serial ripple multiplier architecture proposed by the present invention, which is obtained by folding the structure shown in fig. 1. In FIG. 1 use k²An arithmetic unit PE ofThe structure and function of the rows of k arithmetic elements PE are the same, so the remaining k arithmetic elements PE can be replaced with the k arithmetic elements PE of the 1 st row, which requires k cycles. The input for the 1 st cycle A is (A)₀,A₁,…,A_k-1) B, directly inputting, and inputting a calculation result into a temporary storage C through an FRRP reduction module; input of 2 nd cycle A (A)_k,A_k+1,…,A_2k-1) B is input through an R3 module, and the calculation result is added with the calculation result of the 1 st period through an FRRP reduction module and is stored in a temporary storage C; thus, knowing the kth cycle, the input to A is

B passes through the (k-1) time R3 module and then is input, the calculation result passes through the FRRP restoration module, is added with the previous (k-1) time accumulation result and is stored in the register C, and the register C outputs the result, wherein C = ABmodF (x).

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (6)

1. A fast operation multi-bit serial pulse binary finite field multiplier is characterized in that the multiplier comprises an input endB、kA PE module, an FRRP module, an R3 modulekA plurality of PE modules are connected in series, thekA PE module warpkOne period, 1 st periodAIs inputted by

And B direct transfusionAnd in, the calculation result is restored and input to the temporary storage through the FRRP moduleCPerforming the following steps; 2 nd cycleAIs inputted，BThe calculation result is also restored by the FRRP module after being input by the R3 module, added with the calculation result of the 1 st period and stored in a temporary storageCPerforming the following steps; thus, firstkIn the course of one period of time,Ais inputted by

，BThrough (a) tok-1) inputting after the R3 module, the calculation result is restored by the FRRP module, andk-1) adding the results of the sub-accumulations and saving them in a registerCIn the intermediate registerCOutput results, the R3 module implements

The PE module includes an R1 module, a CMP module, a CVP module, a PWM module, a,An exclusive OR gate, andthe R3 module is output to the R1 module and then undergoes coefficient conversion by the CMP module, the A segment is input to the CVP module to undergo coefficient conversion of the A segment, and the calculation results of the CMP module and the CVP module are input to the PWM module to realize

AndAfractional product calculation through

Accumulated by an exclusive-or gate, the result being stored in

In a latch, is composed of

Latch output result

Wherein,Aby a trinomial polynomial

Is shown as

All of (1) tomA coefficient of

，

Using a segmentation cutting method, willmOf bitsAIs cut into

Each segment ofdBits, in total, havek ² Is segmented, thus having

；BBy a double substrate can be represented as

As the other input of the multiplier;Cis the output result.

2. The fast-acting multi-bit serial systolic dual-basis binary finite field multiplier of claim 1, in which said FRRP block includes an FR block, an R2 block, said R2 block implementing

The input of the FR module is the calculation result of k series PE modules, and the result is restored and output to the R2 module.

3. The fast acting multi-bit serial systolic dual-basis binary finite field multiplier of claim 1, characterized in that said CMP module comprises XOR-gates XOR _1 and XOR _2, said XOR-gates XOR-1 and XOR _2 being connected in parallel.

4. The fast acting multi-bit serial systolic dual-basis binary finite field multiplier of claim 1, in which said CVP block is an exclusive or gate XOR _ 3.

5. The fast acting multi-bit serial systolic dual-basis binary finite field multiplier of claim 1, characterized in that said PWM block comprises three AND gates AND _1, AND _2 AND _3 connected in parallel, point-to-point multiplying the results output by said CMP block AND said CVP block.

6. The fast acting multi-bit serial systolic dual-basis binary finite field multiplier of claim 1, in which said FR block comprises two parallel exclusive or gates XOR _4 and XOR _ 5.

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