CN103175757B - Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate - Google Patents
Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate Download PDFInfo
- Publication number
- CN103175757B CN103175757B CN201110433485.XA CN201110433485A CN103175757B CN 103175757 B CN103175757 B CN 103175757B CN 201110433485 A CN201110433485 A CN 201110433485A CN 103175757 B CN103175757 B CN 103175757B
- Authority
- CN
- China
- Prior art keywords
- field effect
- effect transistor
- boron
- surface channel
- channel pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a method for testing the diffusion of boron to metal or metallic silicide of a surface PMOS (P-channel metal oxide semiconductor) polysilicon gate. The method comprises the following steps of: preparing a first NMOS (N-channel metal oxide semiconductor) field effect transistor and a first surface PMOS field effect transistor by using the process and the parameter of a reference MOSFET (metal-oxide-semiconductor field effect transistor) process; preparing a second NMOS (N-channel metal oxide semiconductor) field effect transistor and a second surface PMOS field effect transistor by adopting the MOSFET process for reducing the thermal process; and comparing the absolute value of the difference Delta VTN of threshold voltages of both the first NMOS field effect transistor and the second NMOS field effect transistor with the absolute value of the difference Delta VTP of the threshold voltages of both the first surface PMOS field effect transistor and the second surface PMOS field effect transistor, wherein if the absolute value of the Delta VTP is less than or equal to the absolute value of the Delta VTN, that no boron can diffuse to the surface PMOS field effect transistor which is prepared by adopting the reference MOSFET process is indicated, and if the absolute value of the Delta VTP is more than the absolute value of the Delta VTN, that the boron can diffuse obviously to the surface PMOS field effect transistor is indicated. The method disclosed by the invention can be used for electrically and quantitatively evaluating the influence of the diffusion of the boron of the surface PMOS polysilicon gate prepared by adopting the reference MOSFET process on a device.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of method measuring surface channel PMOS polysilicon gate boron and spread to metal or metal silicide.
Background technology
Along with in semiconductor integrated circuit chip, the integrated level of device is more and more higher, and the size of wherein conventional Metal-oxide-semicondutor field effect transistor (MOSFET) will reduce further, and requires lower operating voltage and larger drive current.
For reduction of device size, reduce costs, industry usually adopts the method for so-called " self-aligned via holes " (SAC); And to reduction operating voltage, improve drive current, the especially metal-oxide-semiconductor of P type raceway groove, then need to use surface channel (surface channel) device.But, when the two combines time, will special requirement be had for grid structure and technique:
1) before gate polycrystalline silicon etching, polysilicon N-type is carried out and P type adulterates;
2) N-type polycrystalline silicon must be connected by metal or metal silicide with P type polysilicon, to ensure CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor (CMOS)) and the normal work of SRAM (Static Random Access Memory, static random memory);
MOSFET technological process generally includes following steps:
One. prepared by active area;
Two. two trap ion implantation;
Three. threshold voltage adjustment is injected;
Four .MOS device grids oxide layer growths;
Five. prepared by grid, wherein PMOS grid adopts the P type polysilicon being doped to boron (B);
Six. polysilicon oxidation;
Seven. lightly doped drain (LDD) injects and rapid thermal annealing;
Eight. silicon nitride or monox lateral wall CVD deposit;
Nine. source and drain is injected and rapid thermal annealing;
Ten. prepared by self-aligned metal silicate;
11. back segment metal connecting line.
For this reason, need to judge whether that boron (B) spreads to metal or metal silicide, judge that boron (B) has much impacts to metal or metal silicide generation diffusion couple device, judges boron whether (B) can accept to the impact of metal or metal silicide generation diffusion couple device, judges diffusion in full wafer silicon chip face whether.But the SIMS (Secondary Ion MassSpectrometry, secondary ion mass spectrum) that current industry adopts usually and the method comparing NMOS/PMOS relative capacity all can not meet above requirement simultaneously.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method measuring surface channel PMOS polysilicon gate boron and spread to metal or metal silicide, the impact of the boron diffusion couple device of energy electrical property quantitative evaluation benchmark MOSFET artistic face channel PMOS polysilicon.
For solving the problems of the technologies described above, the method that mensuration surface channel PMOS polysilicon gate boron of the present invention spreads to metal or metal silicide, comprises the following steps:
One. utilize process and the parameter of benchmark MOSFET technique, preparation the one NMOS field effect transistor and first surface channel PMOS field effect transistor;
Utilize the MOSFET technique reducing thermal process, preparation the 2nd NMOS field effect transistor and second surface channel PMOS field effect transistor;
The MOSFET technique reducing thermal process is compared with benchmark MOSFET technique, and the temperature of the thermal process after grid preparation process reduces and/or time shorten, and other technological process is identical with parameter;
Wherein, NMOS field effect transistor adopts N-type polycrystalline silicon as gate electrode, and PMOS adopts the P type polysilicon being doped to boron as gate electrode;
Two. calculate the difference of the threshold V T N (A) of a NMOS field effect transistor and the threshold V T N (B) of the 2nd NMOS field effect transistor: Delta VTN=VTN (A)-VTN (B);
Calculate the threshold V T P (A) of first surface channel PMOS field effect transistor and the difference of the threshold V T P (B) of second surface channel PMOS field effect transistor: Delta VTP=VTP (A)-VTP (B);
Three. compare the absolute value of Delta VTN and Delta VTP, if the absolute value of Delta VTP is less than or equal to the absolute value of Delta VTN, then benchmark MOSFET artistic face channel PMOS field effect transistor does not have boron to spread; If the absolute value of Delta VTP is much larger than the absolute value of Delta VTN, then benchmark MOSFET artistic face channel PMOS field effect transistor has obvious boron to spread.
If there occurs boron diffusion, then can contrast first surface channel PMOS field effect transistor, second surface channel PMOS field effect transistor electrical property to assess the impact of boron diffusion couple device.
If the absolute value of Delta VTP is than the absolute value of Delta VTN greatly more than 50mV, then benchmark MOSFET artistic face channel PMOS field effect transistor has obvious boron to spread.
The MOSFET technique reducing thermal process is compared with benchmark MOSFET technique, and the temperature of the thermal process after grid preparation process reduces at least 10 DEG C.
The MOSFET technique reducing thermal process is compared with benchmark MOSFET technique, the time shorten at least 10% of the thermal process after grid preparation process.
Thermal process after grid preparation process can comprise lightly doped drain and inject and rapid thermal annealing, source and drain injection and rapid thermal annealing.
One embodiment, utilize process and the parameter of benchmark MOSFET technique, first silicon chip manufactures multiple NMOS field effect transistor, surface channel PMOS field effect transistor, utilize process and the parameter of the MOSFET technique reducing thermal process, same manufacture multiple NMOS field effect transistor, surface channel PMOS field effect transistor on the second silicon chip, wherein NMOS field effect transistor adopts N-type polycrystalline silicon as gate electrode, and surface channel PMOS adopts the P type polysilicon being doped to boron as gate electrode; According to the order of magnitude of the difference of the threshold voltage of the corresponding each NMOS field effect transistor in the first silicon chip, the second silicon chip full wafer silicon chip face, the order of magnitude of the difference of the threshold voltage of corresponding each surface channel PMOS field effect transistor, judges the homogeneity of the boron diffusion of the surface channel PMOS field effect transistor of the whole silicon chip of the first silicon chip benchmark MOSFET technique everywhere.
The method that mensuration surface channel PMOS polysilicon gate boron of the present invention spreads to metal or metal silicide, by benchmark MOSFET technique, the respective difference reducing the double grid N/PMOSFET threshold voltage of the MOSFET manufacture technics of thermal process carrys out the boron diffusion of determinating reference MOSFET artistic face channel PMOS polysilicon, the method needs to prepare two groups of NMOS and surface channel PMOS, and (wherein NMOS adopts N-type polycrystalline silicon as gate electrode, surface channel PMOS adopts boron doped p-type polysilicon as gate electrode), it is different that these two groups of different N/PMOS are temperature in the thermal process in technological process and/or time, other as process such as threshold voltage adjustment ion implantation etc. all, then the threshold voltage of two groups of NMOS and surface channel PMOS is measured respectively, obtain the difference of two groups of NMOS threshold voltages, the difference of two groups of surface channel PMOS threshold voltages, finally by comparing these two differences to realize the judgement of benchmark MOSFET artistic face channel PMOS polysilicon boron diffusion.What is more important, if benchmark MOSFET artistic face channel PMOS polysilicon there occurs boron diffusion, the electrical property that then can contrast above two groups of surface channel PMOSs has great impact to the boron diffusion couple device assessing benchmark MOSFET artistic face channel PMOS polysilicon, and this impact can be quantized by electrical property, also can the reliability of test component and IP, thus can determine whether can accept, and process and the parameter of benchmark MOSFET technique can be utilized, first silicon chip manufactures multiple NMOS field effect transistor, surface channel PMOS field effect transistor, utilize process and the parameter of the MOSFET technique reducing thermal process, the multiple NMOS field effect transistor of same manufacture on the second silicon chip, surface channel PMOS field effect transistor, according to the first silicon chip, the order of magnitude of the difference of the threshold voltage of the corresponding each NMOS field effect transistor in the second silicon chip full wafer silicon chip face, the order of magnitude of the difference of the threshold voltage of corresponding each surface channel PMOS field effect transistor, judge the homogeneity of the thermal process of conventional MOSFET technique in whole silicon chip boron diffusion everywhere.
Accompanying drawing explanation
In order to be illustrated more clearly in the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in the present invention or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the method one embodiment schematic diagram that mensuration surface channel PMOS polysilicon gate boron of the present invention spreads to metal or metal silicide;
Fig. 2 is the threshold voltage of a NMOS field effect transistor and the threshold voltage schematic diagram of the 2nd NMOS field effect transistor;
Fig. 3 is the threshold voltage of first surface channel PMOS field effect transistor and the threshold voltage schematic diagram of second surface channel PMOS field effect transistor.
Embodiment
Below in conjunction with the accompanying drawing in the present invention, carry out clear, complete description to the technical scheme in the present invention, obviously, described embodiment is a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, other embodiments all that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belong to the scope of protection of the invention.
Embodiment one
Measure surface channel PMOS polysilicon gate boron to metal or metal silicide diffusion method one embodiment as shown in Figure 1, comprise the following steps:
One. utilize process and the parameter of benchmark MOSFET technique, preparation the one NMOS field effect transistor and first surface channel PMOS field effect transistor; Wherein, NMOS field effect transistor adopts N-type polycrystalline silicon as gate electrode, and PMOS adopts the P type polysilicon being doped to boron (B) as gate electrode;
Utilize the MOSFET technique reducing thermal process, preparation the 2nd NMOS field effect transistor and second surface channel PMOS field effect transistor;
The MOSFET technique reducing thermal process is compared with benchmark MOSFET technique, and the temperature of the thermal process after grid preparation process reduces and/or time shorten, and other technological process is identical with parameter; The MOSFET technique preferably reducing thermal process is compared with benchmark MOSFET technique, and the temperature of the thermal process after grid preparation process reduces at least 10 DEG C, time shorten at least 10%.
Wherein, NMOS field effect transistor adopts N-type polycrystalline silicon as gate electrode, and PMOS adopts the P type polysilicon being doped to boron as gate electrode;
Two. measure and obtain the threshold V T N (A) of a NMOS field effect transistor, the threshold V T N (B) of the 2nd NMOS field effect transistor, the threshold V T P (A) of first surface channel PMOS field effect transistor, the threshold V T P (B) of second surface channel PMOS field effect transistor;
Calculate the difference of the threshold V T N (A) of a NMOS field effect transistor and the threshold V T N (B) of the 2nd NMOS field effect transistor: Delta VTN=VTN (A)-VTN (B);
Calculate the threshold V T P (A) of first surface channel PMOS field effect transistor and the difference of the threshold V T P (B) of second surface channel PMOS field effect transistor: Delta VTP=VTP (A)-VTP (B);
Three. compare the absolute value of Delta VTN and Delta VTP, if the absolute value of Delta VTP is less than or equal to the absolute value of Delta VTN, then benchmark MOSFET artistic face channel PMOS field effect transistor does not have boron to spread; If the absolute value of Delta VTP is much larger than the absolute value of Delta VTN, then benchmark MOSFET artistic face channel PMOS field effect transistor has obvious boron to spread.
Preferably, if the absolute value of Delta VTP than the absolute value of Delta VTN greatly more than 50mV, then benchmark MOSFET artistic face channel PMOS field effect transistor has obvious boron to spread.
Preferably, if there occurs boron diffusion, then measure the electrical property obtaining first surface channel PMOS field effect transistor, second surface channel PMOS field effect transistor, assess the impact of boron diffusion couple device by the electrical property of contrast first surface channel PMOS field effect transistor, second surface channel PMOS field effect transistor.This impact can be quantized by electrical property, also can the reliability of test component and IP (ip module), thus can determine whether boron diffusion can accept.
Preferably, process and the parameter of benchmark MOSFET technique can be utilized, first silicon chip manufactures multiple NMOS field effect transistor, surface channel PMOS field effect transistor, utilize process and the parameter of the MOSFET technique reducing thermal process, same manufacture multiple NMOS field effect transistor, surface channel PMOS field effect transistor on the second silicon chip, wherein NMOS field effect transistor adopts N-type polycrystalline silicon as gate electrode, and surface channel PMOS adopts the P type polysilicon being doped to boron as gate electrode; According to the order of magnitude of the difference of the threshold voltage of the corresponding each NMOS field effect transistor in the first silicon chip, the second silicon chip full wafer silicon chip face, the order of magnitude of the difference of the threshold voltage of corresponding each surface channel PMOS field effect transistor, judges the homogeneity of the boron diffusion of the surface channel PMOS field effect transistor of the whole silicon chip of the first silicon chip benchmark MOSFET technique everywhere.
Embodiment two
Based on embodiment one, benchmark MOSFET technique comprises the following steps:
One. prepared by active area;
Two. two trap ion implantation;
Three. threshold voltage adjustment is injected;
Four .MOS device grids oxide layer growths;
Five. prepared by grid, wherein surface channel PMOS grid adopts the P type polysilicon being doped to boron (B);
Six. polysilicon oxidation;
Seven. lightly doped drain (LDD) injects and rapid thermal annealing;
Eight. silicon nitride or monox lateral wall CVD deposit;
Nine. source and drain is injected and rapid thermal annealing;
Ten. prepared by self-aligned metal silicate;
11. back segment metal connecting line.
That the threshold V T N (A) of a NMOS field effect transistor is almost 0 with the difference of the threshold V T N (B) of the 2nd NMOS field effect transistor, the threshold V T N (A) of a visible NMOS field effect transistor and the threshold V T N (B) of the 2nd NMOS field effect transistor shown in Fig. 2.
That the absolute value of the difference of the threshold V T P (A) of first surface channel PMOS field effect transistor and the threshold V T P (B) of second surface channel PMOS field effect transistor, the threshold V T P (A) of visible first surface channel PMOS field effect transistor and the threshold V T P (B) of second surface channel PMOS field effect transistor is up to 80mV shown in Fig. 3.Can find out, the thermal process of benchmark MOSFET technique can cause serious boron diffusion, and this diffusion can cause the PMOS threshold voltage shift up to about 80mV.It should be noted that, can both the difference of calculated threshold voltage at different device grids oxidated layer thickness in above two figure, thus all can lead to the same conclusion, but in the method, this different thickness of grid oxide layer is non-essential, from another angle, the popularity that the method is applied is described on the contrary.
The method that mensuration surface channel PMOS polysilicon gate boron of the present invention spreads to metal or metal silicide, by benchmark MOSFET technique, the respective difference reducing the double grid N/PMOSFET threshold voltage of the MOSFET manufacture technics of thermal process carrys out the boron diffusion of determinating reference MOSFET artistic face channel PMOS polysilicon, the method needs to prepare two groups of NMOS and surface channel PMOS, and (wherein NMOS adopts N-type polycrystalline silicon as gate electrode, surface channel PMOS adopts boron doped p-type polysilicon as gate electrode), it is different that these two groups of different N/PMOS are temperature in the thermal process in technological process and/or time, other as process such as threshold voltage adjustment ion implantation etc. all, then the threshold voltage of two groups of NMOS and surface channel PMOS is measured respectively, obtain the difference of two groups of NMOS threshold voltages, the difference of two groups of surface channel PMOS threshold voltages, finally by comparing these two differences to realize the judgement of benchmark MOSFET artistic face channel PMOS polysilicon boron diffusion.What is more important, if benchmark MOSFET artistic face channel PMOS polysilicon there occurs boron diffusion, the electrical property that then can contrast above two groups of surface channel PMOSs has great impact to the boron diffusion couple device assessing benchmark MOSFET artistic face channel PMOS polysilicon, and this impact can be quantized by electrical property, also can the reliability of test component and IP, thus can determine whether can accept, and process and the parameter of benchmark MOSFET technique can be utilized, first silicon chip manufactures multiple NMOS field effect transistor, surface channel PMOS field effect transistor, utilize process and the parameter of the MOSFET technique reducing thermal process, the multiple NMOS field effect transistor of same manufacture on the second silicon chip, surface channel PMOS field effect transistor, according to the first silicon chip, the order of magnitude of the difference of the threshold voltage of the corresponding each NMOS field effect transistor in the second silicon chip full wafer silicon chip face, the order of magnitude of the difference of the threshold voltage of corresponding each surface channel PMOS field effect transistor, judge the homogeneity of the thermal process of conventional MOSFET technique in whole silicon chip boron diffusion everywhere.
Claims (5)
1. measure the method that surface channel PMOS polysilicon gate boron spreads to metal or metal silicide, it is characterized in that, comprise the following steps:
One. utilize process and the parameter of benchmark MOSFET technique, preparation the one NMOS field effect transistor and first surface channel PMOS field effect transistor;
Utilize the MOSFET technique reducing thermal process, preparation the 2nd NMOS field effect transistor and second surface channel PMOS field effect transistor;
The MOSFET technique reducing thermal process is compared with benchmark MOSFET technique, and the temperature of the thermal process after grid preparation process reduces and/or time shorten, and other technological process is identical with parameter;
Wherein, NMOS field effect transistor adopts N-type polycrystalline silicon as gate electrode, and PMOS field effect transistor adopts the P type polysilicon being doped to boron as gate electrode;
Two. calculate the difference of the threshold V T N (A) of a NMOS field effect transistor and the threshold V T N (B) of the 2nd NMOS field effect transistor: Delta VTN=VTN (A)-VTN (B);
Calculate the threshold V T P (A) of first surface channel PMOS field effect transistor and the difference of the threshold V T P (B) of second surface channel PMOS field effect transistor: Delta VTP=VTP (A)-VTP (B);
Three. compare the absolute value of Delta VTN and Delta VTP, if the absolute value of Delta VTP is less than or equal to the absolute value of Delta VTN, then benchmark MOSFET artistic face channel PMOS field effect transistor does not have boron to spread; If the absolute value of Delta VTP is than the absolute value of Delta VTN greatly more than 50mV, then benchmark MOSFET artistic face channel PMOS field effect transistor has obvious boron to spread.
2. mensuration surface channel PMOS polysilicon gate boron according to claim 1 to metal or metal silicide diffusion method, it is characterized in that,
If there occurs boron diffusion, then the electrical property of contrast first surface channel PMOS field effect transistor, second surface channel PMOS field effect transistor assesses the impact of boron diffusion couple device.
3. mensuration surface channel PMOS polysilicon gate boron according to claim 1 to metal or metal silicide diffusion method, it is characterized in that,
The MOSFET technique reducing thermal process is compared with benchmark MOSFET technique, and the temperature of the thermal process after grid preparation process reduces at least 10 DEG C.
4. mensuration surface channel PMOS polysilicon gate boron according to claim 1 to metal or metal silicide diffusion method, it is characterized in that,
The MOSFET technique reducing thermal process is compared with benchmark MOSFET technique, the time shorten at least 10% of the thermal process after grid preparation process.
5. mensuration surface channel PMOS polysilicon gate boron according to claim 1 to metal or metal silicide diffusion method, it is characterized in that,
Thermal process after grid preparation process comprises, and lightly doped drain injects and rapid thermal annealing, source and drain injection and rapid thermal annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110433485.XA CN103175757B (en) | 2011-12-21 | 2011-12-21 | Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110433485.XA CN103175757B (en) | 2011-12-21 | 2011-12-21 | Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103175757A CN103175757A (en) | 2013-06-26 |
| CN103175757B true CN103175757B (en) | 2015-04-08 |
Family
ID=48635766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110433485.XA Active CN103175757B (en) | 2011-12-21 | 2011-12-21 | Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103175757B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010086858A (en) * | 2000-03-03 | 2001-09-15 | 윤종용 | Method to optimize P-channel MOS transistor for impeding boron penetration |
| CN1384547A (en) * | 2001-05-02 | 2002-12-11 | 三菱电机株式会社 | Semiconductor device and its manufacture |
| CN101819993A (en) * | 2010-04-13 | 2010-09-01 | 东南大学 | P type lateral insulated gate bipolar device for reducing hot carrier effect |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8294485B2 (en) * | 2009-02-12 | 2012-10-23 | International Business Machines Corporation | Detecting asymmetrical transistor leakage defects |
-
2011
- 2011-12-21 CN CN201110433485.XA patent/CN103175757B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010086858A (en) * | 2000-03-03 | 2001-09-15 | 윤종용 | Method to optimize P-channel MOS transistor for impeding boron penetration |
| CN1384547A (en) * | 2001-05-02 | 2002-12-11 | 三菱电机株式会社 | Semiconductor device and its manufacture |
| CN101819993A (en) * | 2010-04-13 | 2010-09-01 | 东南大学 | P type lateral insulated gate bipolar device for reducing hot carrier effect |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103175757A (en) | 2013-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100394537C (en) | Manufacturing method for semiconductor device | |
| CN101740549B (en) | Test structure and test method for precisely evaluating reliability performance of gate oxide | |
| Lou et al. | A novel single-device DC method for extraction of the effective mobility and source-drain resistances of fresh and hot-carrier degraded drain-engineered MOSFET's | |
| US20120273887A1 (en) | Semiconductor device manufacturing method and semiconductor device | |
| US6275059B1 (en) | Method for testing and diagnosing MOS transistors | |
| CN102522386B (en) | Gate-oxidizing-layer interface-trap density-testing structure and testing method | |
| US6995027B2 (en) | Integrated semiconductor structure for reliability tests of dielectrics | |
| Chen et al. | Stress-induced MOSFET mismatch for analog circuits | |
| US20090309097A1 (en) | Testing device on water for monitoring vertical mosfet on-resistance | |
| CN102176442A (en) | Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device | |
| CN103175757B (en) | Method for testing diffusion of boron to metal or metallic silicide of surface PMOS (p-channel metal oxide semiconductor) polysilicon gate | |
| Roll | Leakage current and defect characterization of short channel MOSFETs | |
| CN100388413C (en) | Manufacturing method for semiconductor device | |
| US7335518B2 (en) | Method for manufacturing semiconductor device | |
| KR100494439B1 (en) | testing method of ion-implanting energy for ion-implanter | |
| US7351595B2 (en) | Method for manufacturing semiconductor device | |
| Garba-Seybou et al. | Location of Oxide Breakdown Events under Off-state TDDB in 28nm N-MOSFETs dedicated to RF applications | |
| Lee et al. | An electrical failure analysis (EFA) flow to quantitatively identify invisible defect on individual transistor: Using the characterization of random dopant fluctuation (RDF) as an example | |
| US6403979B1 (en) | Test structure for measuring effective channel length of a transistor | |
| US8809077B2 (en) | Method of manufacturing semiconductor device | |
| Tian et al. | Physical and electrical characterization of PAI implant energy’s impact on multi-Vt SoC device performance | |
| US7043328B2 (en) | Method for manufacturing semiconductor device utilizing monitor wafers | |
| RENAUX et al. | Implementation of fd soi cmos technology in ite | |
| US7867884B2 (en) | Sample wafer fabrication method | |
| Tuinhout et al. | Methodology to evaluate long channel matching deterioration and effects of transistor segmentation on MOSFET matching |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140107 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140107 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |