CN103165682B - A kind of electrode structure of PIN diode - Google Patents
A kind of electrode structure of PIN diode Download PDFInfo
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- CN103165682B CN103165682B CN201310063704.9A CN201310063704A CN103165682B CN 103165682 B CN103165682 B CN 103165682B CN 201310063704 A CN201310063704 A CN 201310063704A CN 103165682 B CN103165682 B CN 103165682B
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Abstract
The invention discloses a kind of electrode structure of PIN diode, described electrode comprises P electrode and N electrode, and wherein P electrode is formed in the top of described PIN diode tube core, and described N electrode is formed in below the tube core of described PIN diode; Described P electrode and N electrode are by insulator separation.
Description
Technical field
The invention belongs to diode technologies field, particularly a kind of electrode structure of Primary Component PIN diode of electric semiconductor DC-to-AC converter.
Background technology
The Primary Component of current electric semiconductor DC-to-AC converter generally adopts diode, specifically divides, and has PN type and PIN type.
The load of DC-to-AC converter is the motor of induction type load mostly.In the course of the work, electric current in DC-to-AC converter, usually carries out work using IGBT as switch between induction type load and the closed circuit of support element, controls electric energy by repetition cut-off state and conducting state.Under the state of IGBT conducting, do not flow through electric current in PIN diode, PIN diode is in cut-off state.On the other hand, under the state of IGBT cut-off, flow through electric current in PIN diode, PIN diode is in conducting state.In order to improve the switching characteristic of DC-to-AC converter, require to make PIN diode be converted to cut-off state from conducting state as early as possible.For this reason, need to shorten the life-span in PIN diode.If shorten the life-span, exist and make conducting resistance uprise this problem.Therefore, in order to not only guarantee the switching characteristic of PIN diode but also reduce conducting resistance, just require the life-span controlling PIN diode accurately.
The conventional structure of PIN diode is: intrinsic semiconductor layer is clipped between p-type and n-type semiconductor layer, forms the horizontal three-decker of sandwich formula.The horizontal PIN diode of this routine is restricted in miniaturized, because when the PIN diode laterally formed, reduces that characteristic size causes p layer, junction area between i layer and n layer is restricted.China granted patent CN100583460C discloses a kind of PIN diode, the junction area that its structure adopted can be improved reduction characteristic size to a certain extent and limit.But the sensitivity of PIN diode disclosed in this patent or deficiency.
And in prior art, the electrode of PIN diode is general is all only formed on the part surface of P doped layer and N doped layer, this structure, when encapsulating, often only can be placed in packaging body in one way, thus limit the convenience of encapsulation.
Summary of the invention:
The present invention proposes a kind of electrode structure of PIN diode, the electrode structure of the PIN diode adopting the present invention to propose, can be applied in various packaging body easily.
The electrode structure of the PIN diode that the present invention proposes, this structure is: described electrode comprises P electrode and N electrode;
Wherein, the tube core of described PIN diode is made up of P+ doped layer, P-doped layer, intrinsic layer I, N-doped layer and N+ doped layer.
Wherein, N+ doped layer is made up of, in inverted T shape structure base part and fin ledge;
Wherein, N-doped layer comprises Part I and Part II, and described Part I is formed on the surface of the base part of N+ doped layer, and described Part II is formed in the surface of the fin ledge of described N+ doped layer;
Wherein, insulating barrier, it is formed above the Part I of N-doped layer;
Wherein, intrinsic semiconductor layer, it is formed above insulating barrier and N-doped layer, to surround described N-doped layer;
Wherein, P-doped layer, it is formed above insulating barrier and intrinsic semiconductor layer, to surround described intrinsic semiconductor layer;
Wherein, P+ doped layer, it is formed above insulating barrier and P-doped layer, to surround described P-doped layer.
Wherein, P+ doped layer, P-doped layer and intrinsic semiconductor layer are isolated by the Part I of insulating barrier and N-doped layer.
Wherein said P electrode is formed in the surface of whole P+ doped layer, in inverted U structure; Described N electrode surrounds the side of Part I and the bottom surface of N+ doped layer of N-doped layer, U-shaped structure, described P electrode and N electrode by insulating barrier every.
The electrode structure of the PIN diode that the present invention proposes comprises the PIN diode of the P+P-IN-N+ structure (I is intrinsic semiconductor layer) had, and it can reduce conduction voltage drop.And P electrode be formed in PIN diode P+ doped layer above whole peripheral surface, N electrode is formed in the whole peripheral surface below the N+ doped layer of described PIN diode and N-doped layer, therefore in the process of encapsulation, PIN diode can be placed in packaging body with various modes of emplacement, and this brings great convenience to encapsulation.
Accompanying drawing explanation
Fig. 1 is the PIN diode structure schematic diagram that the present invention proposes.
Embodiment:
As shown in Figure 1, the electrode structure of the PIN diode that the present invention proposes comprises: N electrode, P electrode and PIN diode, wherein, PIN diode comprises: N+ doped layer 102, it is made up of base part and fin ledge, in inverted T shape structure, N+ doped layer 102 is formed by the N-shaped impurity mixing high concentration in the material such as silicon, germanium, this N-shaped impurity such as phosphorus (P) or arsenic (As), in the present invention, preferably adopt phosphorus as N-shaped impurity, its doping content is approximately 1 × 10
19cm
-3to 1 × 10
21cm
-3between; N-doped layer 103 comprises Part I 1031 and Part II 1032, described Part I 1031 is formed on the surface of the base part of N+ doped layer 102, described Part II 1032 is formed on the surface of the fin ledge of described N+ doped layer 102, N-doped layer can be formed by the N-shaped impurity mixing such as phosphorus (P) or arsenic (As) in the semi-conducting material such as silicon, germanium equally, in the present invention, preferred employing phosphorus is as N-shaped impurity, and its doping content is approximately 5 × 10
15cm
-3to 5 × 10
16cm
-3between.
Insulating barrier 101, it is formed above the Part I 1031 of N-doped layer 103, and this insulating barrier is shallow trench isolation layer (STI) structure; Insulating barrier 101 makes N-doped layer 103 isolate with P-doped layer 105 and P+ doped layer 106, thus can avoid less desirable electronic leak and short circuit;
Intrinsic semiconductor layer 104, it is formed above insulating barrier 101 and N-doped layer 103, to surround described N-doped layer 103; Intrinsic semiconductor layer 104 can adopt the material same with N-doped layer 103 to be formed.
P-doped layer 105, it is formed above insulating barrier 101 and intrinsic semiconductor layer 104, to surround described intrinsic semiconductor layer 104; P-doped layer 105 is by mixing p-type impurity to be formed to the semi-conducting material such as silicon, germanium, and p-type impurity is such as boron (B), and the doping content of this P-doped layer is approximately: 1 × 10
15cm
-3to 1 × 10
16cm
-3;
P+ doped layer 106, it is formed above insulating barrier 101 and P-doped layer 105, to surround described P-doped layer 105, P+ doped layer 106 is by mixing p-type impurity to be formed to the semi-conducting material such as silicon, germanium, p-type impurity is such as boron (B), and the doping content of this P+ doped layer 106 is approximately: 5 × 10
18cm
-3to 1 × 10
20cm
-3.
P electrode is formed in the top of the P+ doped layer 106 of described PIN diode, and to surround described P+ doped layer 106, described N electrode is formed in the below of described N+ doped layer 102, to surround side and the N+ doped layer 102 of the Part I 1031 of N-doped layer; Described P electrode and N electrode are by insulator separation.Wherein P electrode and N electrode can adopt and form the metal material that good ohmic contacts with semiconductor energy and form, metal or its alloys such as this material such as Al, Mo, Ta, Ti, W.
It should be noted that, although indicate in present embodiment that N+ doped layer, N-doped layer, intrinsic semiconductor layer, P-doped layer and P+ doped layer can have the semi-conducting material such as silicon or germanium to form, but this material being not N+ doped layer, N-doped layer, intrinsic semiconductor layer, P-doped layer and P+ doped layer can be different, in the present invention, above-mentioned each layer, under the prerequisite adopting same material, can select the semi-conducting material such as silicon or germanium to form.
Above execution mode is to invention has been detailed introduction, but above-mentioned execution mode is not intended to limit scope of the present invention, and protection scope of the present invention is defined by the appended claims.
Claims (3)
1. an electrode structure for PIN diode, is characterized in that:
Described electrode comprises P electrode and N electrode;
Wherein, the tube core of described PIN diode is made up of P+ doped layer, P-doped layer, intrinsic layer I, N-doped layer and N+ doped layer; N+ doped layer is made up of, in inverted T shape structure base part and fin ledge; N-doped layer comprises Part I and Part II, and described Part I is formed on the surface of the base part of N+ doped layer, and described Part II is formed in the surface of the fin ledge of described N+ doped layer; Insulating barrier, it is formed above the Part I of N-doped layer; Intrinsic semiconductor layer, it is formed above insulating barrier and N-doped layer, to surround described N-doped layer; P-doped layer, it is formed above insulating barrier and intrinsic semiconductor layer, to surround described intrinsic semiconductor layer; P+ doped layer, it is formed above insulating barrier and P-doped layer, to surround described P-doped layer; P+ doped layer, P-doped layer and intrinsic semiconductor layer are isolated by the Part I of insulating barrier and N-doped layer;
Wherein said P electrode is formed in the surface of whole P+ doped layer, in inverted U structure; Described N electrode surrounds the side of Part I and the bottom surface of N+ doped layer of N-doped layer, and U-shaped structure, described P electrode and N electrode are by insulator separation.
2. PIN diode as claimed in claim 1, is characterized in that:
The doping content of N+ doped layer is 1 × 10
19cm
-3to 1 × 10
21cm
-3between; The doping content of N-doped layer is 5 × 10
15cm
-3to 5 × 10
16cm
-3between; The doping content of P-doped layer is: 1 × 10
15cm
-3to 1 × 10
16cm
-3between; The doping content of P+ doped layer is: 5 × 10
18cm
-3to 1 × 10
20cm
-3between.
3. PIN diode as claimed in claim 2, is characterized in that:
Described N+ doped layer, N-doped layer, intrinsic semiconductor layer, P-doped layer and P+ doped layer are made up of identical semi-conducting material.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310063704.9A CN103165682B (en) | 2013-02-28 | 2013-02-28 | A kind of electrode structure of PIN diode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310063704.9A CN103165682B (en) | 2013-02-28 | 2013-02-28 | A kind of electrode structure of PIN diode |
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|---|---|
| CN103165682A CN103165682A (en) | 2013-06-19 |
| CN103165682B true CN103165682B (en) | 2015-08-05 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103236436B (en) * | 2013-02-28 | 2016-02-17 | 溧阳市宏达电机有限公司 | A kind of manufacture method of electrode of PIN diode |
| KR101779300B1 (en) * | 2016-06-17 | 2017-09-19 | 한양대학교 산학협력단 | Fin field effect transistor comprising barrier region |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081019A (en) * | 1995-10-05 | 2000-06-27 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Semiconductor diode with suppression of auger generation processes |
| CN101236995A (en) * | 2007-02-01 | 2008-08-06 | 国际商业机器公司 | PIN diode and method for making PIN diode and forming semiconductor fin structure |
| CN101393937A (en) * | 2007-09-20 | 2009-03-25 | 三菱电机株式会社 | Semiconductor device |
| CN102122693A (en) * | 2010-01-08 | 2011-07-13 | 台湾积体电路制造股份有限公司 | Diode |
| JP2013021142A (en) * | 2011-07-12 | 2013-01-31 | Toyota Central R&D Labs Inc | Semiconductor device |
| CN103236436A (en) * | 2013-02-28 | 2013-08-07 | 溧阳市宏达电机有限公司 | Method for manufacturing electrode of PIN (positive intrinsic negative) diode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8207064B2 (en) * | 2009-09-17 | 2012-06-26 | Sandisk 3D Llc | 3D polysilicon diode with low contact resistance and method for forming same |
-
2013
- 2013-02-28 CN CN201310063704.9A patent/CN103165682B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081019A (en) * | 1995-10-05 | 2000-06-27 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Semiconductor diode with suppression of auger generation processes |
| CN101236995A (en) * | 2007-02-01 | 2008-08-06 | 国际商业机器公司 | PIN diode and method for making PIN diode and forming semiconductor fin structure |
| CN101393937A (en) * | 2007-09-20 | 2009-03-25 | 三菱电机株式会社 | Semiconductor device |
| CN102122693A (en) * | 2010-01-08 | 2011-07-13 | 台湾积体电路制造股份有限公司 | Diode |
| JP2013021142A (en) * | 2011-07-12 | 2013-01-31 | Toyota Central R&D Labs Inc | Semiconductor device |
| CN103236436A (en) * | 2013-02-28 | 2013-08-07 | 溧阳市宏达电机有限公司 | Method for manufacturing electrode of PIN (positive intrinsic negative) diode |
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| CN103165682A (en) | 2013-06-19 |
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Effective date of registration: 20190108 Address after: 213300 Hongkou Road 218, Zhongguancun Science and Technology Industrial Park, Liyang City, Changzhou City, Jiangsu Province Patentee after: Liyang High-tech Venture Center Address before: 213300 No. 86 Beimen East Road, Liyang City, Changzhou City, Jiangsu Province Patentee before: Liyang Hongda Motors Co., Ltd. |