CN103165449A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN103165449A CN103165449A CN201110407018XA CN201110407018A CN103165449A CN 103165449 A CN103165449 A CN 103165449A CN 201110407018X A CN201110407018X A CN 201110407018XA CN 201110407018 A CN201110407018 A CN 201110407018A CN 103165449 A CN103165449 A CN 103165449A
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Abstract
The invention provides a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device comprises proving a semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and etching the dielectric layer to enable the dielectric layer to be fin-shaped; forming a sacrificial layer on the semiconductor substrate to cover the fin-shaped dielectric layer; etching the sacrificial layer to form side wall bodies on two sides of the fin-shaped dielectric layer; carrying out hydrogen annealing on the side wall bodies to form metal layers on two sides of the fin-shaped dielectric layer; forming graphene layers on the metal layers to cover the metal layers; and carrying out dehumidification and evaporation processing on the metal layers to achieve peeling between the graphene layers and the metal layers. According to the manufacturing method of the semiconductor device, fin-shaped channels comprising graphene with a single-layer structure can be formed, and thus electrical properties of FinFet devices are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method that forms fin (Fin) the shape raceway groove of FinFet device.
Background technology
Along with constantly dwindling of channel dimensions, it fin formula field effect transistor (FinFet) is reached the approval that day by day obtains the semiconductor manufacturing factory business with the first-selected semiconductor device of making of the semiconductor fabrication process of lower node as 22nm, because can adapt to the scaled requirement of device size better.
Prior art adopts following processing step to form fin (Fin) the shape raceway groove of FinFet device usually: at first, form a buried oxide layer to make silicon-on-insulator (SOI) structure on silicon substrate; Then, form a silicon layer on described silicon-on-insulator (SOI) structure, described silicon layer can be monocrystalline silicon or polysilicon; Then, graphical described silicon layer, and etching through patterned described silicon layer to form described fin (Fin) shape raceway groove.Next, can form grid in the both sides of described fin (Fin) shape raceway groove, and form germanium silicon stressor layers at the two ends of described fin (Fin) shape raceway groove.
There are some researches show, Graphene has fabulous electric property, for example very high electron mobility, the quantum hall effect that at room temperature namely possesses, have high-speed transfer passage greater than 0.4 micron long etc.Yet, it is very difficult that Graphene is formed on silicon substrate, this is to be formed on the number of plies of the Graphene on silicon substrate because adopt traditional chemical vapor deposition method to be difficult to control, and the Graphene with sandwich construction is difficult to embody above-mentioned outstanding electric property.
Therefore, need to propose a kind of method, have the Graphene of single layer structure to form on silicon substrate, thereby improve the electric property of fin (Fin) the shape raceway groove of FinFet device by Graphene.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, form a dielectric layer on described Semiconductor substrate, and the described dielectric layer of etching is so that described dielectric layer is fin-shaped; Form a sacrifice layer on described Semiconductor substrate, to cover the described dielectric layer that is fin-shaped; The described sacrifice layer of etching is to form a sidewall bodies in the described both sides that are the dielectric layer of fin-shaped; Described sidewall bodies is carried out hydrogen annealing, to form a metal level in the described both sides that are the dielectric layer of fin-shaped; Form a graphene layer to cover described metal level on described metal level; Described metal level is implemented dehumidification and evaporation process, to realize peeling off between described graphene layer and described metal level.
Further, adopt chemical vapor deposition method or spin coating proceeding to form described dielectric layer.
Further, the material of described dielectric layer comprises oxide, silicon nitride, has the material of low k value or has the material of loose structure.
Further, adopt chemical vapor deposition method or atom layer deposition process to form described sacrifice layer.
Further, the material of described sacrifice layer is copper nitride.
Further, adopt the described sacrifice layer of dry method etch technology etching.
Further, the thickness of described sidewall bodies is 500-600nm.
Further, adopt the nitrogen element in the described copper nitride of hydrogen annealing process removal, to form described metal level in the described both sides that are the dielectric layer of fin-shaped.
Further, described hydrogen annealing process is rapid thermal anneal process.
Further, the main gas that described hydrogen annealing process adopts is hydrogen, wherein contains the nitrogen of 5-20%.
Further, the temperature of described hydrogen annealing process is 150-300 ℃.
Further, the pressure of described hydrogen annealing process is 1-10Torr.
Further, the time of described hydrogen annealing process is 5-120min.
Further, adopt chemical vapor deposition method to form described graphene layer.
Further, described graphene layer is single layer structure.
Further, the temperature of described dehumidification and evaporation process is higher than 1000 ℃.
Further, the duration of described dehumidification and evaporation process is 5-7h.
Further, the described dielectric layer that is fin-shaped is arrayed on described Semiconductor substrate.
According to the present invention, can form fin (Fin) the shape raceway groove of the Graphene that comprises single layer structure, and then improve the electric property of FinFet device.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 E is the schematic cross sectional view of each step of method of fin (Fin) the shape raceway groove of the formation FinFet device that proposes of the present invention;
Fig. 2 is the flow chart of method of fin (Fin) the shape raceway groove of the formation FinFet device that proposes of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and be implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that the method for fin (Fin) the shape raceway groove of the formation FinFet device that explaination the present invention proposes in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination but do not get rid of.
Below, the detailed step of method of fin (Fin) the shape raceway groove of the formation FinFet device that the present invention proposes is described with reference to Figure 1A-Fig. 1 E and Fig. 2.
With reference to Figure 1A-Fig. 1 E, wherein show the schematic cross sectional view of each step of method of fin (Fin) the shape raceway groove of the formation FinFet device that the present invention proposes.
At first, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, doped with monocrystalline silicon of impurity etc.As example, in the present embodiment, described Semiconductor substrate 100 selects single crystal silicon material to consist of.
Next, form a dielectric layer 101 on described Semiconductor substrate 100.The material of described dielectric layer 101 comprises oxide, silicon nitride, have the material of low k value (being low-k) or have the material of loose structure.The technique that forms described dielectric layer 101 can adopt chemical vapor deposition method or spin coating proceeding.Then.The described dielectric layer 101 of etching is so that described dielectric layer 101 is fin-shaped.
Then, as shown in Figure 1B, form a sacrifice layer on described Semiconductor substrate 100, to cover the described dielectric layer 101 that is fin-shaped.The material of described sacrifice layer is copper nitride (Cu
3N), also can adopt with copper nitride and similarly can remove nonmetalloid wherein and only keep the material of metallic element wherein by hydrogen annealing process.Form process using chemical vapor deposition method or the atom layer deposition process of described sacrifice layer.Then, adopt the described sacrifice layer of dry method etch technology etching, to form a sidewall bodies 102 in the described both sides that are the dielectric layer 101 of fin-shaped.The thickness of described sidewall bodies 102 is 500-600nm.
Then, as shown in Fig. 1 C, the nitrogen element in the constituent material copper nitride of the described sidewall bodies 102 of employing hydrogen annealing process removal is to form a metal level 103 in the described both sides that are the dielectric layer 101 of fin-shaped.Described hydrogen annealing process is rapid thermal anneal process (RTA), and the main gas of employing is hydrogen, wherein contains the nitrogen of 5-20%, and temperature is 150-300 ℃, and pressure is 1-10Torr, and the time is 5-120min.
Then, as shown in Fig. 1 D, adopt chemical vapor deposition method to form a graphene layer 104 to cover described metal level 103 on described metal level 103, described graphene layer 104 is single layer structure.
Then, as shown in Fig. 1 E, described metal level 103 is implemented dehumidification and evaporation process, realize peeling off between described graphene layer 104 and described metal level 103 by described metal level 103 is vapored away, be close to the described graphene layer that is the dielectric layer 101 of fin-shaped thereby form one in the described both sides that are the dielectric layer 101 of fin-shaped.The temperature of described dehumidification and evaporation process is higher than 1000 ℃, duration 5-7h.
So far, whole processing steps of method enforcement have according to an exemplary embodiment of the present invention been completed, need to prove, only enumerated the situation of only having a fin (Fin) shape raceway groove on described Semiconductor substrate 100 in the present embodiment, and easily be understood that for the ordinary skill in the art, the method that the present invention proposes is equally applicable to have on described Semiconductor substrate 100 a plurality of situations that are fin (Fin) the shape raceway groove of arrayed.Next, can complete by subsequent technique the making of whole FinFet device, described subsequent technique and traditional FinFet device manufacturing process are identical.According to the present invention, can form fin (Fin) the shape raceway groove of the Graphene with single layer structure, and then improve the electric property of FinFet device.
With reference to Fig. 2, wherein show the flow chart of method of fin (Fin) the shape raceway groove of the formation FinFet device that the present invention proposes, be used for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, form a dielectric layer on described Semiconductor substrate, and the described dielectric layer of etching is so that described dielectric layer is fin-shaped;
In step 202, form a sacrifice layer on described Semiconductor substrate, to cover the described dielectric layer that is fin-shaped;
In step 203, the described sacrifice layer of etching is to form a sidewall bodies in the described both sides that are the dielectric layer of fin-shaped;
In step 204, described sidewall bodies is carried out hydrogen annealing, to form a metal level in the described both sides that are the dielectric layer of fin-shaped;
In step 205, form a graphene layer to cover described metal level on described metal level;
In step 206, described metal level is implemented dehumidification and evaporation process, to realize peeling off between described graphene layer and described metal level.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (18)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, form a dielectric layer on described Semiconductor substrate, and the described dielectric layer of etching is so that described dielectric layer is fin-shaped;
Form a sacrifice layer on described Semiconductor substrate, to cover the described dielectric layer that is fin-shaped;
The described sacrifice layer of etching is to form a sidewall bodies in the described both sides that are the dielectric layer of fin-shaped;
Described sidewall bodies is carried out hydrogen annealing, to form a metal level in the described both sides that are the dielectric layer of fin-shaped;
Form a graphene layer to cover described metal level on described metal level;
Described metal level is implemented dehumidification and evaporation process, to realize peeling off between described graphene layer and described metal level.
2. method according to claim 1, is characterized in that, adopts chemical vapor deposition method or spin coating proceeding to form described dielectric layer.
3. method according to claim 1 and 2, is characterized in that, the material of described dielectric layer comprises oxide, silicon nitride, have the material of low k value or have the material of loose structure.
4. method according to claim 1, is characterized in that, adopts chemical vapor deposition method or atom layer deposition process to form described sacrifice layer.
5. according to claim 1 or 4 described methods, is characterized in that, the material of described sacrifice layer is copper nitride.
6. method according to claim 1, is characterized in that, adopts the described sacrifice layer of dry method etch technology etching.
7. method according to claim 1, is characterized in that, the thickness of described sidewall bodies is 500-600nm.
8. method according to claim 5, is characterized in that, adopts the nitrogen element in the described copper nitride of hydrogen annealing process removal, to form described metal level in the described both sides that are the dielectric layer of fin-shaped.
9. method according to claim 8, is characterized in that, described hydrogen annealing process is rapid thermal anneal process.
10. method according to claim 8, is characterized in that, the main gas that described hydrogen annealing process adopts is hydrogen, wherein contains the nitrogen of 5-20%.
11. method according to claim 8 is characterized in that, the temperature of described hydrogen annealing process is 150-300 ℃.
12. method according to claim 8 is characterized in that, the pressure of described hydrogen annealing process is 1-10Torr.
13. method according to claim 8 is characterized in that, the time of described hydrogen annealing process is 5-120min.
14. method according to claim 1 is characterized in that, adopts chemical vapor deposition method to form described graphene layer.
15. method according to claim 1 is characterized in that, described graphene layer is single layer structure.
16. method according to claim 1 is characterized in that, the temperature of described dehumidification and evaporation process is higher than 1000 ℃.
17. method according to claim 1 is characterized in that, the duration of described dehumidification and evaporation process is 5-7h.
18. method according to claim 1 is characterized in that, the described dielectric layer that is fin-shaped is arrayed on described Semiconductor substrate.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107735864A (en) * | 2015-06-08 | 2018-02-23 | 美商新思科技有限公司 | Substrate and the transistor with the 2D material channels on 3D geometric figures |
| CN107968121A (en) * | 2016-10-20 | 2018-04-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
| CN108735669A (en) * | 2017-04-13 | 2018-11-02 | 格芯公司 | Integrated graphene detector with waveguide |
| CN110212065A (en) * | 2019-06-11 | 2019-09-06 | 厦门乾照光电股份有限公司 | A kind of PVD sputtering equipment, LED component and preparation method thereof |
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| US20100055388A1 (en) * | 2008-08-29 | 2010-03-04 | Advanced Micro Devices, Inc. | Sidewall graphene devices for 3-d electronics |
| US7732859B2 (en) * | 2007-07-16 | 2010-06-08 | International Business Machines Corporation | Graphene-based transistor |
| CN102054870A (en) * | 2010-10-26 | 2011-05-11 | 清华大学 | Semiconductor structure and forming method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7732859B2 (en) * | 2007-07-16 | 2010-06-08 | International Business Machines Corporation | Graphene-based transistor |
| US20100055388A1 (en) * | 2008-08-29 | 2010-03-04 | Advanced Micro Devices, Inc. | Sidewall graphene devices for 3-d electronics |
| CN102054870A (en) * | 2010-10-26 | 2011-05-11 | 清华大学 | Semiconductor structure and forming method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107735864A (en) * | 2015-06-08 | 2018-02-23 | 美商新思科技有限公司 | Substrate and the transistor with the 2D material channels on 3D geometric figures |
| US10950736B2 (en) | 2015-06-08 | 2021-03-16 | Synopsys, Inc. | Substrates and transistors with 2D material channels on 3D geometries |
| CN107735864B (en) * | 2015-06-08 | 2021-08-31 | 美商新思科技有限公司 | Substrate and transistor with 2D material channel on 3D geometry |
| CN107968121A (en) * | 2016-10-20 | 2018-04-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
| CN107968121B (en) * | 2016-10-20 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
| CN108735669A (en) * | 2017-04-13 | 2018-11-02 | 格芯公司 | Integrated graphene detector with waveguide |
| CN108735669B (en) * | 2017-04-13 | 2023-03-24 | 格芯美国公司 | Integrated graphene detector with waveguide |
| CN110212065A (en) * | 2019-06-11 | 2019-09-06 | 厦门乾照光电股份有限公司 | A kind of PVD sputtering equipment, LED component and preparation method thereof |
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| CN103165449B (en) | 2015-09-09 |
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