CN103164564A

CN103164564A - Vector testing virtual layer generating method of territory validation rule

Info

Publication number: CN103164564A
Application number: CN2012105124088A
Authority: CN
Inventors: 侯劲松; 王勇; 张萍; 李宁
Original assignee: MIRCOSCAPE TECHNOLOGY Co Ltd
Current assignee: MIRCOSCAPE TECHNOLOGY Co Ltd
Priority date: 2012-12-04
Filing date: 2012-12-04
Publication date: 2013-06-19

Abstract

A territory validation rule file is an important file which is used for verifying whether territory design confirms to a process processing restraint condition or not. In order to verify accuracy of the rule file, a plurality of tested vectors need constructing, and then a calculated result is analyzed whether the calculated result is consistent with the territory validation rule file. In the territory validation rule file, people often encounter checking of a geometric rule among a special device image and other layers, and a common rule comprises distance checking from a Gate of a metal oxide semiconductor (MOS) tube to other layers, and distance checking that the Gate of the MOS tube is covered by other layers. A common construction tested vector method comprises the following steps that aimed at each rule, an image of the MOS tube is manually constructed, and then a distance relation image from the Gate of the MOS tube to other layers is constructed. In order to improve production efficiency, the invention provides a virtual layer generating method. Two virtual layers of N gate Layer and P Gate Layer are introduced by the method, and the two virtual layers can directly conduct gap and covering checking with other random layers and do not need drawing the image of the MOS tube each time.

Description

The test vector virtual level generation method of layout verification rule

Technical field

The test vector virtual level generation method of layout verification rule is a kind of inspection method in layout verification (DRC) in integrated circuit Autocad instrument.The invention belongs to layout verification field in integrated circuit Autocad instrument.

Background technology

The later stage of integrated circuit (IC) design comprises layout design and layout verification, and these two functions are the important steps in eda tool; Layout verification be according to the logical relation of layout design rules, electricity rule and original input to layout design carry out correctness checking and can be by the extraction to circuit and parameter, the input file that produces breadboardin carries out rear simulation, with further inspection electric property.

The layout verification rule file is to verify whether layout design meets the vital document of processes constraint condition, and the correctness direct relation of this file the chip manufacture success or failure.In order to verify the correctness of this rule file, need a lot of test vectors of structure, then whether the result of calculation of analytical test vector is consistent with the layout verification rule file.What test vector referred to here is generally one group of domain figure, is used for reflecting the test case of whether violating design rule.

In the layout verification rule file; often can run into the inspection of the geometrical rule between special component graphics and other layer; for example metal-oxide-semiconductor is the figure that often occurs during the device rule checks; common rule has: the Gate of metal-oxide-semiconductor checks to the distance between other layer, the distance inspection that the Gate of metal-oxide-semiconductor is surrounded by other Layer.The method of common structure test vector is: for each rule, and the Gate of all figures of a metal-oxide-semiconductor of manual structure, and then structure metal-oxide-semiconductor and the distance relation figure of other Layer.The weakness of this method is: when the device of metal-oxide-semiconductor and the relation of other Layer were a lot, the workload of manual flower metal-oxide-semiconductor was larger, needed to seek a kind of mechanism that can repeated citing metal-oxide-semiconductor Gate.

In order to address the above problem, the present invention proposes a kind of generation method of virtual level, the method has been introduced NgateLayer and two virtual levels of PGateLayer, these two virtual levels can be directly and other any layer carry out the inspection of spacing and encirclement, and do not need all to draw the metal-oxide-semiconductor figure at every turn.After introducing virtual level, can support complicated arbitrarily metal-oxide-semiconductor type, high-voltage MOS pipe for example, the metal-oxide-semiconductor of two-layer Poly etc.

Summary of the invention

Suppose being described below of a design rule: the figure of the Gate layer of metal-oxide-semiconductor can not be less than 0.1 micron to the minor increment of M1 figure.

The diagram of this rule is as shown in Figure 1:

In Fig. 1, blue figure is the raceway groove GateLayer of metal-oxide-semiconductor, red figure is the active area of metal-oxide-semiconductor, it is usually stacked by two layer and forms, if NMOS pipe, it is comprised of the active area SN of input horizon AA and N-type, if the PMOS pipe, it is comprised of the active area SP of input horizon AA and P type.The figure of grey is hole Contact, and green figure is the figure of the M1 that will check.To check the distance of blue figure and green figure in this example.

A complete metal-oxide-semiconductor figure is by active area, and raceway groove and hole three parts form, and wherein active area may be superimposed by 2 even a plurality of layer and form; Raceway groove can be ground floor poly, can be also second layer poly; Hole layer Contact is that a unique layer forms.

In order automatically to generate GateLayer to the test vector of M1 apart from inspection, the basic ideas of this patent are: at first by the layer definition of the embedded metal-oxide-semiconductor of the definition of overall layer, secondly directly quote this virtual level of GateLayer of metal-oxide-semiconductor and realize that efficient test vector generates when definition rule.

The definition of global layer as shown in Figure 2.

In Fig. 2, first layer of Wiring Layer is GT, it is exactly the raceway groove layer that consists of metal-oxide-semiconductor, first layer at ContactLayer is CT, and it is exactly the Contact Layer that consists of metal-oxide-semiconductor, SN in Nactive Layers, AA is exactly the active area that consists of the N-type metal-oxide-semiconductor, SP in Pactive Layers, AA are exactly the active area that consists of P type metal-oxide-semiconductor, and these Layer have consisted of the fundamental figure of a common metal-oxide-semiconductor.

After defining overall layer, can realize GateLayer to the definition of M1 distance by the virtual level of directly quoting NgateLayer, define method as shown in Figure 3.

In Fig. 3, Layer1 has inserted this original common layer of M1, has inserted this virtual level of NgateLayer in Layer2, and instrument allows it automatically to insert virtual level.The implication of option Parallel To Gate is: check and the Spacing of Gate parallel direction, the another one option is Perpendicular To Gate, and its implication is: check the Spacing with the Gate vertical direction.

After inserting above-mentioned information, operation generates the process of test vector automatically, has obtained the test vector result of Fig. 4:

As seen from Figure 4, test vector can be automatically generates the figure of Gate, and reason is: in the arranging of overall layer, Nactive Layer, Wiring Layer, Contact Layer has set, and these layer of instrument meeting Automatic-searching generate the figure of a Gate.

For another example, if check the distance of Contact and Gate in the Gate figure, as shown in Figure 5.

In order to generate the test vector of Fig. 5, can realize GateLayer to the definition of Contact distance by the virtual level of directly quoting NgateLayer, define method is as shown in Figure 6.

After inserting the information of Fig. 6, operation generates the process of test vector automatically, has obtained the test vector result of Fig. 7, can see, meets expected result.

More than introduced the application of virtual level NgateLayer, in like manner, for the figure of virtual level PGateLayer, building method similarly repeats no more.

Description of drawings

Fig. 1 GateLayer to the M1 figure apart from schematic diagram

Fig. 2 overall situation layer definition diagram

Fig. 3 GateLayer is to the parameter input figure of M1 Graph Distance

Fig. 4 GateLayer is to the test vector of M1 Graph Distance figure as a result

Fig. 5 GateLayer to the Contact figure apart from schematic diagram

Fig. 6 GateLayer is to the parameter input figure of Contact Graph Distance

Fig. 7 GateLayer is to the test vector of Contact Graph Distance figure as a result

Embodiment:

The first step: if version check rule for typical MOS device, define 2 virtual level NGateLayer and PGateLayer.These two virtual levels can directly be used for defining and the spacing of other layer and the rule of encirclement.

Second step: in the definition of overall annexation, active layer (the Nactive Layer of definition metal-oxide-semiconductor, Pactive Layer), the layer such as channel layer (Poly), hole layer (Contact), make follow-up rule can directly drink these layer.

The 3rd step: for the spacing inspection of virtual level and other Layer, instrument directly generates the NgateLayer (PGateLayer) of metal-oxide-semiconductor and the distance relation figure between other Layer automatically, and does not need manually to spend the device of metal-oxide-semiconductor.

The 4th step: for the encirclement inspection of virtual level and other Layer, instrument directly generates the NgateLayer (PGateLayer) of metal-oxide-semiconductor and the encirclement distance relation figure between other Layer automatically, and does not need manually to spend the device of metal-oxide-semiconductor.

Claims

1. the test vector virtual level generation method of layout verification rule, its basic meaning is in the test vector generative process of layout verification rule, for some complicated component graphics, often needs to generate complex devices by the method for artificial picture component graphics.This patent has proposed a kind of definition of virtual level, by virtual level is carried out the geometrical rule inspection, has solved and has described the larger problem of complex devices figure rule workload, thereby improved the efficient that test vector generates.

Concrete steps are as follows:

(1) for typical MOS device, define 2 virtual level NGateLayer and PGateLayer.These two virtual levels can directly be used for defining and the spacing of other layer and the rule of encirclement.

(2) in the definition of overall annexation, active layer (the Nactive Layer of definition metal-oxide-semiconductor, Pactive Layer), the layer such as channel layer (Poly), hole layer (Contact), make follow-up rule can directly drink these layer.

(3) for the spacing inspection of virtual level and other Layer, instrument directly generates the NgateLayer (PGateLayer) of metal-oxide-semiconductor and the distance relation figure between other Layer automatically, and does not need manually to spend the device of metal-oxide-semiconductor.

(4) for the encirclement inspection of virtual level and other Layer, instrument directly generates the NgateLayer (PGateLayer) of metal-oxide-semiconductor and the encirclement distance relation figure between other Layer automatically, and does not need manually to spend the device of metal-oxide-semiconductor.