CN103152062A - Generation method of real-time signal and device - Google Patents

Abstract

The invention discloses a generation method of a real-time signal and a device. The method includes that a base band signal data point is read by each work clock of a signal processor. Each read base band signal data point is parallely divided into an n-way base band signal. N data points of a low frequency sine signal and a low frequency cosine signal with the sampling frequency of the work clock are respectively produced by the signal processor. An n-way base band and an n-way low frequency signal are modulated in an orthogonal mode by the signal processor. An n-way modulating signal is stored in the buffer according to a timing sequence after the parallel n-way modulating signal is obtained. A group of n-way modulating signals outputs are read by each work clock according to the principle of first in-first out. According to the scheme of the generation method of the real-time signal and the device, hardware equipment cost of a signal producing system is reduced. The fact that a high frequency signal which is not produced by the present processor according to the Nyquist law is produced in real time is achieved.

Description

A kind of generation method and device of live signal

Technical field

The present invention relates to Digital Signal Processing and software wireless electrical domain, relate in particular to a kind of live signal generation method and device.

Background technology

Constantly from the simulation-to-digital transformation, the modern signal generation system gets more and more and uses the software radio equipment to realize along with the communication technology, and a large amount of signal of software radio equipment is processed and all realized in numeric field by high performance processor.At present, use the signal creating method of digital processing unit to mainly contain two kinds, a kind of is at the signal highest frequency hour, completes the generation of live signal with the processor that satisfies the Nyquist law, and namely the work clock of processor is greater than 2 times of the signal highest frequency.A kind of is when the signal highest frequency is larger, on the low rate processor, that the waveform of signal is pre-stored, comes settling signal to generate by the mode of quick broadcast.

When using first method to generate signal, signal frequency is higher, requires the work clock of signal processor higher, and price is also higher simultaneously, and the signal processor work clock on market neither be unrestrictedly high.When using second method to generate signal, requiring to produce very large time-delay in multiple signals parallel generation situation, can't satisfy the real-time response requirement.

It is that baseband signal with certain bandwidth generates a near bandwidth signal upper frequency by quadrature modulation that conventional live signal generates, and modulated carrier frequency is far longer than signal bandwidth.DDS(Direct Digital Synthesizer due to signal processor) local frequency of unit generation can only be less than 1/2nd of work clock, therefore along with the increase of carrier frequency, can greatly increase the processor cost, and life does not become highest frequency higher than the signal of work clock.

Summary of the invention

In view of the above problems, the present invention has been proposed in order to a kind of overcome the problems referred to above or the live signal generation method that addresses the above problem at least in part and device are provided.

According to one aspect of the present invention, a kind of live signal generation method is provided, comprising:

Each work clock of signal processor reads the data point of a baseband signal take work clock as sample rate, and the parallel n roadbed band signal data that are divided into of each baseband signal data point that will read;

Each work clock of signal processor can consist of the data point of a carrier signal and the Low Frequency Sine Signals take work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each road low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and satisfies 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zBe the value the set centre frequency greater than the signal to be generated of signal processor maximum functional clock, wherein, when the value of k is odd number, n take work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to every a work clock, be done sign-inverted one time;

Signal processor carries out quadrature modulation with described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point, after the n road modulation signal that obtains walking abreast, deposit chronologically described n road modulation signal in buffer memory, and according to the first-in first-out principle, each work clock reads one group of n road modulation signal output.

Further, in the method for the invention, according to signal bandwidth, work clock and shunt number n generate prototype FIR filter, and prototype FIR filter is divided into n branching filter, the FIR of first branch filter is from first value of prototype FIR filter, get a value every n point, until ending, in like manner n branching filter is worth from n of prototype filter and begins value, get one every n value, until ending.Described signal processor utilizes the FIR of branch filter, read a baseband signal data point at each work clock, use respectively each described baseband signal data point that n the FIR of branch filter will read parallel n way strong point of being divided into, thereby complete the parallel baseband signal of n road take work clock as sample rate that be divided into of the baseband signal take work clock as sample rate with a road.

Wherein, prototype FIR filter is low pass filter, and need satisfy sample rate is nf _o', cut-off frequecy of passband is more than or equal to baseband signal bandwidth, less than or equal to work clock.

Further, in the method for the invention, described signal processor is followed successively by θ, 2 π f by the first phase that n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a sinusoidal pattern carrier signal after n Low Frequency Sine Signals data point combination; Be followed successively by θ, 2 π f by the first phase that n low frequency cosine signal data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a longitudinal cosine type carrier signal after n low frequency cosine signal data point combination; Wherein, θ freely is worth.

Further, in the method for the invention, described signal processor is f by the frequency that n DDS is set _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n realizes when each work clock arrives, utilize n DDS generate respectively n individual take work clock as sample rate the Low Frequency Sine Signals data point and the data point of low frequency cosine signal.

According to another aspect of the present invention, a kind of live signal generating apparatus is provided, comprising:

The parallel processing unit along separate routes of baseband signal is used for each work clock and reads the data point of a baseband signal take work clock as sample rate, and the parallel n roadbed band signal data that are divided into of each baseband signal data point that will read;

Carrier signal parallel generation unit can consist of the data point of a carrier signal and the low frequency sinusoidal signal take work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and satisfies 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zFor set value greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, when the value of k is odd number, n take work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to every a work clock, be done sign-inverted one time;

The signal modulating unit is used for described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out quadrature modulation, the n road modulation signal that obtains walking abreast;

The signal buffer unit be used for depositing chronologically described n road modulation signal in buffer memory, and according to the first-in first-out principle, each work clock reads one group of n road modulation signal output.

Further, in signal processor of the present invention, the parallel processing unit along separate routes of described baseband signal specifically comprises:

Filter arranges subelement, is used for the signal bandwidth according to the signal to be generated of work clock, shunt number n and setting, and the generation sample rate is nf _o', cut-off frequecy of passband is more than or equal to the prototype FIR filter of baseband signal bandwidth less than or equal to work clock, and described prototype FIR filter is divided into n branching filter; Wherein, i the FIR of branch filter got a value every n point from i value of prototype FIR filter, until ending, i=1,2 ..., n;

Subelement is processed in parallel shunt, is used for utilizing the FIR of branch filter, reads a baseband signal data point at each work clock, the parallel n roadbed band signal data point that is divided into of each described baseband signal data point of using respectively n the FIR of branch filter to read.

Further, in signal processor of the present invention, described carrier signal parallel generation unit is followed successively by θ, 2 π f by the first phase that n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a sinusoidal pattern carrier signal after n Low Frequency Sine Signals data point combination; Be followed successively by θ, 2 π f by the first phase that n low frequency cosine signal data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a longitudinal cosine type carrier signal after n low frequency cosine signal data point combination; Wherein, θ freely is worth.

Further, in signal processor of the present invention, described carrier signal parallel generation unit, the concrete frequency that is used for arranging n DDS is f _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, and when each work clock arrives, generate respectively n take work clock as sample rate the Low Frequency Sine Signals data point and the data point of low frequency cosine signal.

Beneficial effect of the present invention is as follows:

The method of the invention and device, n low frequency sine and cosine signal combination producing high-frequency carrier signal have been realized utilizing, realized under low working clock frequency, complete the generative process of higher frequency signals, not only reduce the hardware device cost of signal generating system, but also realized the high-frequency signal that the present processor of real-time generation does not become according to the life of Nyquist law.

Description of drawings

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do one to the accompanying drawing of required use in embodiment or description of the Prior Art and introduce simply, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

The flow chart of the live signal generation method that Fig. 1 provides for the embodiment of the present invention;

The flow chart of the another live signal generation method that Fig. 2 provides for the embodiment of the present invention;

The structural representation of the signal processor that Fig. 3 provides for the embodiment of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.

High in order to solve in prior art the required hardware cost of live signal generating mode, and can't generate highest frequency higher than the problem of the signal of work clock, the embodiment of the present invention provides a kind of live signal generation method and device, it is by parallel account form along separate routes, use the sine of n lower frequency and the carrier signal of cosine signal combination producing upper frequency, and baseband signal and carrier signal are completed quadrature modulation on low clock frequency, well realized generating high-frequency signal with low frequency work clock processor.Below just by several specific embodiments, technical scheme of the present invention is elaborated.

Embodiment one

As shown in Figure 1, the embodiment of the present invention provides a kind of live signal generation method, comprising:

Step S101, each work clock of signal processor reads the data point of a baseband signal take work clock as sample rate, and the parallel n roadbed band signal data that are divided into of each baseband signal data point that will read;

In this step, the work clock f of signal processor _o' satisfy following condition: f _o'≤f _oAnd f _s=nf _o', f in formula _oBe the maximum functional clock frequency of signal processor, f _sSpeed for the signal processor output signal;

Preferably, the implementation of this step is as follows:

According to signal bandwidth, work clock and shunt number n generate prototype FIR filter, prototype FIR filter is divided into n branching filter, the FIR of first branch filter is from first value of prototype FIR filter, get a value every n point, until ending, in like manner n branching filter is worth from n of prototype filter and begins value, get one every n value, until ending.Described signal processor utilizes the FIR of branch filter, read a baseband signal data point at each work clock, use respectively each described baseband signal data point that n the FIR of branch filter will read parallel n way strong point of being divided into, thereby complete the parallel baseband signal of n road take work clock as sample rate that be divided into of the baseband signal take work clock as sample rate with a road.

Wherein, prototype FIR filter is low pass filter, and need satisfy sample rate is nf _o', cut-off frequecy of passband is more than or equal to baseband signal bandwidth, less than or equal to work clock.

Certainly, those skilled in the art also can utilize existing other parallel modes along separate routes to carry out shunt and process, and about parallel mode along separate routes, the present invention does not do unique restriction.

Step S102, each work clock of signal processor can consist of the data point of a carrier signal and the Low Frequency Sine Signals take work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination;

Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and satisfies 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zBe the value the set centre frequency greater than the signal to be generated of signal processor maximum functional clock, wherein, when the value of k is odd number, n take work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to every a work clock, be done sign-inverted one time.

Preferably, in this step, described signal processor is followed successively by θ, 2 π f by the first phase that n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a sinusoidal pattern carrier signal after n Low Frequency Sine Signals data point combination; Be followed successively by θ, 2 π f by the first phase that n low frequency cosine signal data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a longitudinal cosine type carrier signal after n low frequency cosine signal data point combination; Wherein, θ freely is worth.

Preferably, the specific implementation of this step is: the frequency that described signal processor arranges n DDS is f _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, and when each work clock arrives, utilize n DDS generate respectively n individual take work clock as sample rate the Low Frequency Sine Signals data point and the data point of low frequency cosine signal.

Need to prove, in this step, low frequency is with respect to centre frequency f _z.

Step S103, signal processor carries out quadrature modulation with described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point, after the n road modulation signal that obtains walking abreast, deposit chronologically described n road modulation signal in buffer memory, and according to the first-in first-out principle, each work clock reads one group of n road modulation signal output.

Embodiment two

The embodiment of the present invention provides a kind of live signal generation method, and is identical with the principle of embodiment one described method, and it is in conjunction with concrete implementation detail further elaborating embodiment one described method.

In the present embodiment, the maximum functional clock frequency of supposing signal processor is f _o, the bandwidth that generate signal is B _s, centre frequency is f _z, satisfy f _z＞＞B _s, f _o＞＞B _s, and f _zF _o

Concrete, the present embodiment provides a kind of live signal generation method, the signal product process schematic diagram of the method as shown in Figure 2, described method specifically comprises the steps:

Steps A: baseband signal is done parallel processing along separate routes, obtain n roadbed band signal;

Step B: generate n Low Frequency Sine Signals data point and cosine signal data point, generate the high-frequency carrier signal in order to subsequent combination;

Step C: modulating baseband signal and output on parallel basis along separate routes.

About steps A, the specific implementation process is as follows:

Steps A 1: according to the work clock of equipment index signalization processor.

Generate equipment index according to signal, determine that signal is from the speed f of the FIFO buffer unit input D/A processor of signal processor _s, need to satisfy: f _s2f _zThereby, the work clock f of definite signal processor _o', satisfy f _o'≤f _o, and, f _s=nf _o', n is positive integer.

Steps A 2: prototype FIR filter.

Generate the prototype low-pass FIR filter:

Satisfy passband

Interior decay is not more than 0.1dB, stopband

Interior decay is not less than 60dB, and wherein l is the length of filter.

Steps A 3: with the parallel n road signal that is divided into of baseband signal.

The prototype low-pass FIR filter is divided into n the FIR of branch filter

Raw baseband signal is According to shown in Figure 2, every through a clock, buffer shifts once, simultaneously each branch's FIR filter reads a baseband signal, produces n new data.Namely corresponding to each input baseband signal s _in(i), an equal parallel output n data:

Input successively baseband signal according to said process

Just can complete the parallel n roadbed band signal that is divided into of a roadbed band signal

About step B, the specific implementation process is as follows:

Use same signal processor because base band signal process and carrier signal generate, the working clock frequency of signal processor each unit is consistent, so carrier signal uses n road signal combination to represent equally.If the longitudinal cosine type carrier signal is intuitively used n road signal indication:

$\left[\begin{array}{c}{\mathrm{sig}}_{I_1}\left(i\right)=\cos (2\mathrm{\π}{f}_z\mathrm{ni}/f_s+\mathrm{\θ})=\cos (2\mathrm{\π}{f}_{z}i/{f_o}^{\′}+\mathrm{\θ})\\ \mathrm{si}{g}_{I_2}\left(i\right)=\cos (2\mathrm{\π}{f}_z\mathrm{ni}/f_s+2\mathrm{\π}{f}_z/f_s+\mathrm{\θ})=\cos (2\mathrm{\π}{f}_{z}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{I_n}=\cos (2\mathrm{\π}{f}_z\mathrm{ni}/f_s+2\mathrm{\π}{f}_z(n-1)n/f_s+\mathrm{\θ})=\cos (2\mathrm{\π}{f}_{z}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right]$

Due to f _zF _o', utilize the signal processor of work on hand clock frequency to complete, so need to be to f _zDo conversion, order

K is positive integer, and wherein the value of k satisfies:

When k is odd number:

$\left\{\begin{array}{c}{\mathrm{sig}}_{I_1}\left(i\right)={(-1)}^i\·\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+\mathrm{\θ})\\ {\mathrm{sig}}_{I_2}\left(i\right)={(-1)}^i\·\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{I_n}\left(i\right)={(-1)}^i\·\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right.$

When k is even number:

$\left\{\begin{array}{c}{\mathrm{sig}}_{I_1}\left(i\right)=\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+\mathrm{\θ})\\ {\mathrm{sig}}_{I_2}\left(i\right)=\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{I_n}\left(i\right)=\cos (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right.$

By above-mentioned formula, can find out, when frequency of utilization is f _z', the first phase of n road signal is respectively

The cosine signal combination of (wherein θ freely is worth) just can be completed the generation of longitudinal cosine type carrier signal, wherein, can find out from above-mentioned formula, when k is odd number, with the cosine signal that generates, every a work clock, does sign-inverted one time.In like manner can be by parallel n road sinusoidal signal

Combination producing sinusoidal pattern carrier signal.

When k is odd number:

$\left\{\begin{array}{c}{\mathrm{sig}}_{Q_1}\left(i\right)={(-1)}^i\·\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+\mathrm{\θ})\\ {\mathrm{sig}}_{Q_2}\left(i\right)={(-1)}^i\·\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{Q_n}\left(i\right)={(-1)}^i\·\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right.$

When k is even number:

$\left\{\begin{array}{c}{\mathrm{sig}}_{Q_1}\left(i\right)=\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+\mathrm{\θ})\\ {\mathrm{sig}}_{Q_2}\left(i\right)=\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\\ ......\\ {\mathrm{sig}}_{Q_n}\left(i\right)=\sin (2\mathrm{\π}{f_z}^{\′}i/{f_o}^{\′}+2\mathrm{\π}{f}_z(n-1)/{{\mathrm{nf}}_o}^{\′}+\mathrm{\θ})\end{array}\right.$

By above-mentioned formula, can find out, when frequency of utilization is f _z', the first phase of n road signal is respectively θ, 2, π f _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _oThe sinusoidal signal combination that the DDS of '+θ (wherein θ freely is worth) generates just can be completed the generation of sinusoidal pattern carrier signal, wherein, can find out from above-mentioned formula, when k is odd number, with the cosine signal that generates, every a work clock, do sign-inverted one time.

So the frequency that the present invention configures n DDS is f _z' be respectively 2 π (i-1) f with first phase _z/ nf _o'+θ, i=1,2 ..., n generates one group of n road low frequency sinusoidal signal data point and cosine signal data point at each work clock; This group low-frequency signals has been realized the high-frequency carrier signal of combination producing by the modulation of step C and output chronologically.

About step C, the specific implementation process is as follows:

Step C1: as shown in Figure 2, be f with the baseband signal of parallel shunt and low frequency sine and the cosine signal of DDS generation at working clock frequency _o' signal processor on carry out quadrature modulation, the parallel modulation signal in the n road of generation is

Wherein:

$\left\{\begin{array}{c}{y}_1\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_1}\left(i\right)\right)\·\mathrm{si}{g}_{I_1}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_1}\left(i\right)\right)\·{\mathrm{sig}}_{I_1}\left(i\right)\\ y_2\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_2}\left(i\right)\right)\·{\mathrm{sig}}_{I_2}\left(i\right)+\mathrm{imag}\left(s_{\mathrm{ou}{t}_2}\left(i\right)\right)\·{\mathrm{sig}}_{I_2}\left(i\right)\\ ...\\ y_n\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_n}\left(i\right)\right)\·{\mathrm{sig}}_{I_n}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_n}\left(i\right)\right)\·{\mathrm{sig}}_{I_n}\left(i\right)\end{array}\right.$

Step C2: modulation signal along separate routes will walk abreast

Deposit in buffer chronologically.Each work clock produces one group of data y ₁(i), y ₂(i) ..., y _n(i), put into successively buffer according to the order on the 1 road to n road, the order of finally putting into data is:

[y ₁(1),y ₂(1),…,y _n(1),y ₁(2),y ₂(2),…,y _n(2),…,…,y ₁(m),y ₂(m),…,y _n(m)]

Step C3: as shown in Figure 2, with the data of buffer according to the first-in first-out principle, with f _sSpeed is sent in the D/A processor, thus the whole generative process of settling signal.

Reach in order further to set forth the present invention technological means and the effect that predetermined purpose is taked, below provide a concrete application example, the technical scheme that the present invention is proposed is further expalined explanation.

In this application example, use the maximum functional clock frequency of signal processor to be 275MHz, the buffer output data rate is 1GHz to the maximum.The bandwidth that generates signal is that 2MHz, centre frequency are the signal of 350MHz.Further, the described live signal of this application example generation method is completed as follows:

Steps A: baseband signal is done parallel processing along separate routes;

Concrete, the detailed processing procedure of this step is as follows:

Steps A 1: according to the work clock of equipment index signalization processor.

At first determine that from the speed of FIFO buffer input D/A processor the work clock of signal processor uses 250MHz according to D/A performance and the signal of signal generation equipment, parallel way n=4.

Steps A 2: prototype FIR filter.

Generation is satisfied the interior decay of passband 0 ~ 0.002 π and is not more than 0.1dB, and the filter that is not less than 40dB of decaying in stopband 0.25 π ~ π is:

$\tilde{h}=[\mathrm{0.008087,0.0364044,0.09101758,0.15776736,0.20479681},$

$\mathrm{0.20479681,0.1577673,0.0910175,00364044,0.0080876}]$

The length of filter is 10.

Steps A 3: utilize the FIR filter with parallel 4 road signals that are divided into of baseband signal;

The prototype low-pass FIR filter is divided into n the FIR of branch filter

Raw baseband signal is

According to shown in Figure 2, every through a clock, buffer shifts once, simultaneously each branch's FIR filter reads a baseband signal, produces n new data.Namely corresponding to each input baseband signal s _in(i), export respectively n data:

Input successively baseband signal according to said process

Just can complete the parallel 4 roadbed band signals that are divided into of a roadbed band signal

Step B generates n Low Frequency Sine Signals data point and cosine signal data point, generates the high-frequency carrier signal in order to subsequent combination;

Concrete, the detailed processing procedure of this step is as follows:

Step B1: the first phase of asking shunting sign according to frequency of carrier signal.

Use same signal processor because base band signal process and carrier signal generate, working clock frequency is consistent, so same 4 tunnel signal combination of using of carrier signal represent, the sample rate of one-channel signal is 250MHz, and 4 tunnel carrier signals can be expressed as:

$\left\{\begin{array}{c}{\mathrm{sig}}_{I_1}\left(j\right)=\cos \left(2.8\mathrm{\πi}\right)\\ {\mathrm{sig}}_{I_2}\left(j\right)=\cos (2.8\mathrm{\πi}+0.7\mathrm{\π})\\ {\mathrm{sig}}_{I_3}\left(j\right)=\cos (2.8\mathrm{\πi}+1.4\mathrm{\π})\\ {\mathrm{sig}}_{I_4}\left(j\right)=\cos (2.8\mathrm{\πi}+2.1\mathrm{\π})\end{array}\right.$

So, the first phase of every road signal is respectively 0,0.7 π, 1.4 π, 2.1 π.

Step B2: calculate minimum frequency corresponding to each road signal.

Intuitively drawing frequency corresponding to every road signal by step B1 is 350MHz, utilizes the signal processor of work on hand clock frequency to complete, and now, 350MHz is done conversion, due to

So k=2, have:

$\left\{\begin{array}{c}{\mathrm{sig}}_{I_1}\left(i\right)=\cos (0.8\mathrm{\πi})\\ {\mathrm{sig}}_{I_2}\left(i\right)=\cos (0.8\mathrm{\πi}+0.7\mathrm{\π})\\ {\mathrm{sig}}_{I_3}\left(i\right)=\cos (0.8\mathrm{\πi}+1.4\mathrm{\π})\\ {\mathrm{sig}}_{I_4}\left(i\right)=\cos (0.8\mathrm{\πi}+2.1\mathrm{\π})\end{array}\right.$

In like manner can generate the signal of parallel n road phase phasic difference 90o Be respectively:

$\left\{\begin{array}{c}{\mathrm{sig}}_{Q_1}\left(i\right)=\sin (0.8\mathrm{\πi})\\ {\mathrm{sig}}_{Q_2}\left(i\right)=\sin (0.8\mathrm{\πi}+0.7\mathrm{\π})\\ {\mathrm{sig}}_{Q_3}\left(i\right)=\sin (0.8\mathrm{\πi}+1.4\mathrm{\π})\\ {\mathrm{sig}}_{Q_4}\left(i\right)=\sin (0.8\mathrm{\πi}+2.1\mathrm{\π})\end{array}\right.$

Thereby realizing using frequency less than the signal processor work clock is that the sinusoidal and cosine signal combination producing frequency of the low frequency of 100MHz is the high-frequency carrier signal of 350MHz.As shown in Figure 2 n DDS being inserted frequency is 100MHz, and first phase is set to 0,0.7 π, 1.4 π, 2.1 π.

Step C, modulating baseband signal and output on parallel basis along separate routes;

Concrete, the detailed processing procedure of this step is as follows:

Step C1: as shown in Figure 2, with parallel baseband signal along separate routes with parallel along separate routes sine or cosine signal in the signal processor frequency be 250MHz work clock on carry out quadrature modulation, 4 channel parallel datas of generation are Wherein:

$\left\{\begin{array}{c}{y}_1\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_1}\left(i\right)\right)\·{\mathrm{sig}}_{I_1}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_1}\left(i\right)\right)\·{\mathrm{sig}}_{I_1}\left(i\right)\\ y_2\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_2}\left(i\right)\right)\·{\mathrm{sig}}_{I_2}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_2}\left(i\right)\right)\·{\mathrm{sig}}_{I_2}\left(i\right)\\ y_3\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_3}\left(i\right)\right)\·{\mathrm{sig}}_{I_3}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_3}\left(i\right)\right)\·{\mathrm{sig}}_{I_3}\left(i\right)\\ y_4\left(i\right)=\mathrm{real}\left(s_{{\mathrm{out}}_4}\left(i\right)\right)\·{\mathrm{sig}}_{I_4}\left(i\right)+\mathrm{imag}\left(s_{{\mathrm{out}}_4}\left(i\right)\right)\·{\mathrm{sig}}_{I_4}\left(i\right)\end{array}\right.$

Step C2: array along separate routes will walk abreast

Deposit in buffer chronologically.Each work clock produces one group of data y ₁(i), y ₂(i), y ₃(i), y ₄(i), put into successively buffer according to the 1 road to the 4 tunnel order.The order of finally putting into data is:

[y ₁(1),y ₂(1),y ₃(1),y ₄(1),y ₁(2),y ₂(2),y ₃(2),y ₄(2),

…,y ₁(m),y ₂(m),y ₃(m),y ₄(m)]

Step C3: according to as shown in Figure 2, the data of buffer according to the first-in first-out principle, are sent in the D/A processor with 1GHz speed, thus the whole generative process of settling signal.

Embodiment three

As shown in Figure 3, the present embodiment provides a kind of signal processor, specifically comprises:

The parallel processing unit 310 along separate routes of baseband signal is used for each work clock and reads the data point of a baseband signal take work clock as sample rate, and the parallel n roadbed band signal data that are divided into of each baseband signal data point that will read;

Carrier signal parallel generation unit 320 can consist of the data point of a carrier signal and the low frequency sinusoidal signal take work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and satisfies 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zFor set value greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, when the value of k is odd number, n take work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to every a data point, be done sign-inverted one time;

Signal modulating unit 330 is used for described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out quadrature modulation, the n road modulation signal that obtains walking abreast;

Signal buffer unit 340 be used for depositing chronologically described n road modulation signal in buffer memory, and according to the first-in first-out principle, each work clock reads one group of n road modulation signal output.

Wherein, the work clock f of described signal processor _o' satisfy following condition: f _o'≤f _oAnd f _s=nf _o', f in formula _oBe the maximum functional clock frequency of signal processor, f _sSpeed for the signal processor output signal.

Preferably, the parallel processing unit 310 along separate routes of described baseband signal comprises:

Filter arranges subelement, is used for the signal bandwidth according to the signal to be generated of work clock, shunt number n and setting, and the generation sample rate is nf _o', cut-off frequecy of passband is more than or equal to the prototype FIR filter of baseband signal bandwidth less than or equal to work clock, and described prototype FIR filter is divided into n branching filter; Wherein, i the FIR of branch filter got a value every n point from i value of prototype FIR filter, until ending, i=1,2 ..., n;

Subelement is processed in parallel shunt, is used for utilizing the FIR of branch filter, reads a baseband signal data point at each work clock, the parallel n roadbed band signal data point that is divided into of each described baseband signal data point of using respectively n the FIR of branch filter to read.

Preferably, carrier signal parallel generation unit 320 is followed successively by θ, 2 π f by the first phase that n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a sinusoidal pattern carrier signal after n Low Frequency Sine Signals data point combination; Be followed successively by θ, 2 π f by the first phase that n road low frequency cosine signal data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a longitudinal cosine type carrier signal after n low frequency cosine signal data point combination; Wherein, θ freely is worth.

Preferably, carrier signal parallel generation unit 320, the concrete frequency that is used for arranging n DDS is f _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, and when each work clock arrives, utilize n DDS generate respectively n individual take work clock as sample rate the Low Frequency Sine Signals data point and the data point of low frequency cosine signal.

In sum, the described method and apparatus of the present embodiment, by using n low frequency sine and cosine signal data point combination producing high-frequency carrier signal, realized under low work clock, complete the generative process of higher frequency signals, not only reduce the hardware device cost of signal generating system, but also realized the high-frequency signal that the present processor of real-time generation does not become according to the life of Nyquist law.

Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of claim of the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.

Claims (10)

1. a live signal generation method, is characterized in that, comprising:

Each work clock of signal processor reads the data point of a baseband signal take work clock as sample rate, and the parallel n roadbed band signal data that are divided into of each baseband signal data point that will read;

Each work clock of signal processor can consist of the data point of a carrier signal and the Low Frequency Sine Signals take work clock as sample rate and the data point of low frequency cosine signal after generating respectively n combination; Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and satisfies 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zBe the value the set centre frequency greater than the signal to be generated of signal processor maximum functional clock, wherein, when the value of k was odd number, the n take work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point were done sign-inverted one time every a work clock;

Signal processor carries out quadrature modulation with described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point, after the n road modulation signal that obtains walking abreast, deposit chronologically described n road modulation signal in buffer memory, and according to the first-in first-out principle, each work clock reads one group of n road modulation signal output.

2. the method for claim 1, is characterized in that, the work clock f of described signal processor _o' satisfy following condition: f _o'≤f _oAnd f _s=nf _o', f in formula _oBe the maximum functional clock frequency of signal processor, f _sSpeed for the signal processor output signal.

3. method as claimed in claim 1 or 2, is characterized in that, each baseband signal data point that described signal processor will read is parallel is divided into n roadbed band signal data, specifically comprises:

According to work clock, the signal bandwidth of the signal to be generated of number n and setting along separate routes, the generation sample rate is nf _o', cut-off frequecy of passband is more than or equal to the prototype FIR filter of baseband signal bandwidth less than or equal to work clock, and described prototype FIR filter is divided into n branching filter; Wherein, i the FIR of branch filter got a value every n point from i value of prototype FIR filter, until ending, i=1,2 ..., n;

Described signal processor utilizes the FIR of branch filter, reads a baseband signal data point at each work clock, the parallel n roadbed band signal data point that is divided into of each described baseband signal data point of using respectively n the FIR of branch filter to read.

4. method as claimed in claim 1 or 2, is characterized in that, described signal processor is followed successively by θ, 2 π f by the first phase that n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a sinusoidal pattern carrier signal after n Low Frequency Sine Signals data point combination; Be followed successively by θ, 2 π f by the first phase that n low frequency cosine signal data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a longitudinal cosine type carrier signal after n low frequency cosine signal data point combination; Wherein, θ freely is worth.

5. method as claimed in claim 4, is characterized in that, described signal processor is f by the frequency that n DDS is set _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n realizes when each work clock arrives, utilize n DDS generate respectively n individual take work clock as sample rate the Low Frequency Sine Signals data point and the data point of low frequency cosine signal.

6. a signal processor, is characterized in that, comprising:

The parallel processing unit along separate routes of baseband signal is used for each work clock and reads the data point of a baseband signal take work clock as sample rate, and the parallel n roadbed band signal data that are divided into of each baseband signal data point that will read;

Carrier signal parallel generation unit can consist of the data point of a carrier signal and the low frequency sinusoidal signal take work clock as sample rate and the data point of low frequency cosine signal after being used for generating respectively n combination; Wherein, the frequency f of each low frequency signal data point _z'=f _z-kf _o' 2, in formula, k gets and satisfies 0≤f _z'≤f _o' 2 positive integer, f _o' be work clock, f _zFor set value greater than the centre frequency of the signal to be generated of signal processor maximum functional clock, wherein, when the value of k is odd number, n take work clock as sample rate Low Frequency Sine Signals data point and n low frequency cosine signal data point need to every a data point, be done sign-inverted one time;

The signal modulating unit is used for described n roadbed band signal and n Low Frequency Sine Signals data point, a n low frequency cosine signal data point are carried out quadrature modulation, the n road modulation signal that obtains walking abreast;

The signal buffer unit be used for depositing chronologically described n road modulation signal in buffer memory, and according to the first-in first-out principle, each work clock reads one group of n road modulation signal output.

7. signal processor as claimed in claim 6, is characterized in that, the work clock f of described signal processor _o' satisfy following condition: f _o'≤f _oAnd f _s=nf _o', f in formula _oBe the maximum functional clock frequency of signal processor, f _sSpeed for the signal processor output signal.

8. signal processor as described in claim 6 or 7, is characterized in that, the parallel processing unit along separate routes of described baseband signal specifically comprises:

Filter arranges subelement, is used for the signal bandwidth according to the signal to be generated of work clock, shunt number n and setting, and the generation sample rate is nf _o', cut-off frequecy of passband is more than or equal to the prototype FIR filter of baseband signal bandwidth less than or equal to work clock, and described prototype FIR filter is divided into n branching filter; Wherein, i the FIR of branch filter got a value every n point from i value of prototype FIR filter, until ending, i=1,2 ..., n;

Subelement is processed in parallel shunt, is used for utilizing the FIR of branch filter, reads a baseband signal data point at each work clock, the parallel n roadbed band signal data point that is divided into of each described baseband signal data point of using respectively n the FIR of branch filter to read.

9. signal processor as described in claim 6 or 7, is characterized in that, described carrier signal parallel generation unit is followed successively by θ, 2 π f by the first phase that n Low Frequency Sine Signals data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a sinusoidal pattern carrier signal after n Low Frequency Sine Signals data point combination; Be followed successively by θ, 2 π f by the first phase that n road low frequency cosine signal data point is set _z/ nf _o'+θ ..., 2 π (n-1) f _z/ nf _o'+θ realizes consisting of a longitudinal cosine type carrier signal after n low frequency cosine signal data point combination; Wherein, θ freely is worth.

10. signal processor as claimed in claim 9, is characterized in that, described carrier signal parallel generation unit, and the concrete frequency that is used for arranging n DDS is f _z', first phase is respectively 2 π (i-1) f _z/ nf _o'+θ, i=1,2 ..., n, and when each work clock arrives, utilize n DDS generate respectively n individual take work clock as sample rate the Low Frequency Sine Signals data point and the data point of low frequency cosine signal.

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