CN103151375A - Integrated mos power transistor with thin grid oxide layer and low grid charge - Google Patents
Integrated mos power transistor with thin grid oxide layer and low grid charge Download PDFInfo
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Abstract
The invention relates to an integrated MOS power transistor with a thin grid oxide layer and low grid charges. A separation grid power transistor comprises a transversely-arranged power MOSFET which includes a doped silicon substrate, a grid oxide layer formed on the surface of the substrate and a separation polysilicon layer formed on the grid oxide layer. The polysilicon layer is cut into two portions that are electrically isolated from each other: a first portion of a polysilicon grid, postioned on a channel region of the substrate; and a second portion of a polysilicon field plate, positioned on a part of a transition region of the substrate. The two polysilicon portions are separated by a gap. A lgiht doped region is injected inside the substrate below the gap, so that a bridge having the same dope type with the main body of the substrate is formed. The field plate extends above a channel formed inside the substrate and filled with field oxide. The field plate is electrically coupled to a source electrode of the separation grid power transistor.
Description
Related application
Present patent application is that the title of submitting on November 13rd, 2009 is the part continuation application of the U.S. Patent application (sequence number is 12/618,515) of " IMPROVED MOSPOWER TRANSISTOR ".The full text that with sequence number is by reference this U.S. Patent application of 12/618,515 is incorporated in the application.
Technical field
The present invention relates to the field of power transistor.More specifically, the present invention relates to have the field of integrated MOS power transistor of the gate charge of minimizing.
Background technology
The power feeding mechanism is equipment or the system of output loading or load group that the energy of electric energy or other type is provided to.Term " power feeding mechanism " can refer to main power distribution system and other elementary or secondary energy source.Switched-mode power supply, Switching Power Supply or SMPS are the power supplys that comprises switching regulaor.Although linear regulator uses transistor (in this transistorized active region, this transistor being applied biasing) to specify output voltage, SMPS with two-forty fully saturated with end fully between the active switching transistor.Then, the square waveform of generation passes low pass filter (being generally inductor and capacitor (LC) circuit), with the output voltage that obtains to be similar to.
Because SMPS has high power conversion efficiency, small size and light weight and low cost, so SMPS is the voltage conversion device of principal mode at present.SMPS obtains input power from sources such as battery or wall power sockets, and according to the circuit that is coupled to SMPS output, the requirement of power is transformed into short pulse with input power.
MOSFET (mos field effect transistor) generally is used in SMPS.MOSFET is made usually individually, as discrete transistor.Then, each MOSFET is connected to other integrated circuit as the part of SMPS.Use by this way discrete device to increase cost and the size of whole SMPS.
Consume the parts of most power because MOSFET is some in SMPS, so high performance MOSFET is important to the conversion efficiency of SMPS.In addition, the switching frequency of the maximum possible of MOSFET has been indicated the inductor that is included in the SMPS output filter circuit and size, cost and the power loss of capacitor.Under normal SMPS operation, MOSFET is by fast conducting and shutoff, so for effective operation, MOSFET should have low-resistance value and low grid capacitance value.
The 4th terminal that MOSFET has grid, drain electrode and source terminal and is called main body, substrate, main body block or substrate.Substrate is the semi-conductive main body block at finger grid, source electrode and drain electrode place simply.The 4th terminal is used for transistor is applied biasing and makes its operation.Gate terminal is regulated the electronics pass the channel region in substrate and is flowed, namely or allow electronics to flow through raceway groove or block electrons flows through raceway groove.When voltage influence that electronics is applied in, electronics passes raceway groove from source terminal and flows to drain terminal.
The raceway groove of MOSFET is doped to make N type semiconductor or P type semiconductor.Drain electrode and source electrode have the type opposite with raceway groove in the situation that enhancement mode MOSFET can be doped to, or as having type with channel-like being doped in depletion-mode MOSFET.MOSFET adopts insulator between grid and substrate, for example silicon dioxide.This insulator is commonly referred to grid oxic horizon.Therefore, gate terminal is separated by the raceway groove in grid oxic horizon and substrate.
When voltage being applied between grid and source terminal, the field penetration grid oxic horizon that produces also produces so-called " inversion layer (inversion layer) " or raceway groove at the semiconductor-insulator interface place.Inversion channel has the type identical with drain electrode with source electrode, and P type or N-type are so that the raceway groove that provides electric current to pass.Change the conductivity that the voltage between grid and substrate can be regulated this layer, this is used for controlling the current flowing between drain electrode and source electrode.
Power MOSFET is the MOSFET that is widely used as the particular type of low-voltage switches (for example, less than 200V).Lateral direction power MOSFET refers to the structure that drain electrode and source electrode are all placed in each other side, for example drains and source electrode all is positioned at the top surface place of substrate.This is opposite with vertical power mosfet, and wherein drain electrode and source electrode are relative to each other vertically stacking, and for example source electrode is positioned at the top surface place of substrate, and drain electrode is positioned at bottom surface.
Power MOSFET can by how soon a restrictive factor of turn-on and turn-off are the required gate charge amounts of turn-on and turn-off transistor.Gate charge refers to and moves to respectively grid with turn-on transistor and the quantity that shifts out to turn-off transistorized electronics from grid.Required gate charge is larger, and the transistorized time of turn-on and turn-off is just longer.The advantage that has is the power transistor in the diverter switch mode power fast.Frequency is higher, and the size of the discrete parts that uses in the gate driver circuit of SMPS is just less.The parts that less parts are larger are cheap.
Fig. 1 shows the cross sectional side view of the exemplary configurations of conventional lateral direction power MOSFET.In this exemplary configurations, substrate 10 is doped to form p type island region territory or trap 12 and N-type zone or trap 14.P type trap 12 comprises the double diffusion source electrode 16 with the fusion contact site (mergedcontact) 24 between P+ zone 20 and N+ zone 22.Contact site 24 is shorted together P+ zone 20 and N+ zone 22.Contact site 24 is as the source electrode contact site of power transistor, and source electrode is shorted to the main body of substrate, and substrate is the P type in this exemplary configurations.Source electrode contact terminal 42 is coupled to contact site 24 and therefore is coupled to source electrode 16.Substrate 10 also is doped to be formed on the N+ zone 18 in N-type zone 14.N+ zone 18 is as the drain electrode of power transistor.Drain electrode contact terminal 40 is coupled to drain electrode 18.Groove 26 is formed in the top surface of substrate 10.Groove 26 is filled with field oxide.Can use shallow trench isolation to form groove 26 from (STI), and in this case, the groove that is filled with field oxide is called shallow trench isolation from (STI) zone.
Grid oxic horizon 28 is formed on the top surface of substrate 10.Polysilicon gate 30 is formed on grid oxic horizon 28.As shown in Figure 1, the grid oxic horizon 28 between polysilicon gate 30 and substrate 10 is thin oxide layers.Polysilicon gate 30 extends to support high drain electrode-grid voltage on sti region.
Three main region relevant with the operation of power transistor are arranged: channel region, transitional region and drift region in substrate 10.Channel region be formed under polysilicon gate 30 and the p type island region territory 12 of substrate 10 in.In other words, form channel region, wherein polysilicon gate 30 and p type island region territory 12 are overlapping.Drift region is the part under groove 26 or sti region in N-type zone 14.Drift region is to be under off state the drain electrode-grid voltage most zone that descended at transistor.Sti region is necessary for obtaining high drain electrode-grid voltage.On the contrary, if polysilicon gate 30 terminates on thin grid oxide layer, this will cause the too high voltages on grid oxic horizon so, and power transistor can not be carried out function.Similarly, sti region and the polysilicon gate extension on sti region are necessary for reducing high gate-to-drain voltage.
Transitional region is the part under grid oxic horizon 28 and polysilicon gate 30 in N-type zone 14.When power transistor was switched on, transitional region provided the current flow path from the channel region to the drift region.Transitional region is also referred to as accumulator region or neck region.In a lot of the application, transitional region accounts for the maximum single component of the conducting resistance in the low-voltage power MOSFET.The length of transitional region is important design consideration, and wherein length refers to horizontal direction in Fig. 1.If length is too short, the conducting resistance of power MOSFET increases, and device can suffer early stage quasi saturation when making great efforts conducting.If length is oversize, conducting resistance is saturated, and feature conducting resistance (specificon-resistance) increases, and puncture voltage descends.The part on transitional region of being positioned at of polysilicon gate 30 accounts for grid capacitance and a large portion of gate charge thus.
Summary of the invention
Separated grid power transistor (split gate power transistor) comprises the power MOSFET of landscape configuration, and it comprises the silicon substrate of doping, the grid oxic horizon that forms and the separation polysilicon layer that forms on grid oxic horizon on the surface of substrate.Polysilicon layer is cut into the part of two electricity isolation: the second portion that forms the polysilicon field plate that forms on the part of the first of the polysilicon gate on the channel region that is positioned at substrate and the transitional region that is formed on substrate.These two polysilicon segments are separated by the gap.Lightly doped region is injected in the substrate of below, gap, thereby forms the bridge that has identical doping type with substrate body.Field plate also extends on the drift region of substrate, below the groove that is filled with field oxide that wherein drift region forms in substrate.Field plate is electrically coupled to the source electrode of separated grid power transistor.
in one aspect, power transistor comprises the substrate of doping, the substrate of this doping is included in source electrode and the channel region in the first doped region, drain electrode in the second doped region, bridge, First Transition zone and the second transitional region, and the groove in the second doped region, wherein groove is formed in the first surface of substrate, and trench fill has insulating material, in addition, wherein channel region is between source electrode and First Transition zone, the First Transition zone is between channel region and bridge, bridge location is between First Transition zone and the second transitional region, the second transitional region is between bridge and groove, and groove is between the second transitional region and drain electrode.Power transistor also comprises the grid oxic horizon on the first surface that is positioned at substrate; Be positioned on grid oxic horizon and the grid on channel region and First Transition zone; And be positioned on grid oxic horizon and the field plate on the part of the second transitional region and groove, and wherein grid separates with field plate by the gap that is positioned on bridge, and in addition, wherein field plate is electrically coupled to source electrode via conductive trace.
Grid and field plate can be polysilicons.In certain embodiments, the first doped region is the p type island region territory, and the second doped region is N-type zone, and bridge comprises the p type island region territory.Bridge can be doped with P type infusion.In certain embodiments, bridge can be also the N-type zone that is positioned at the interior p type island region territory of bridge and the halo (haloing) between N-type First Transition zone and N-type the second transitional region.N-type zone in bridge can be light dope N-type infusion.In certain embodiments, bridge is continuous on the width in gap, and bridge is continuous along the length in gap.In certain embodiments, halo N-type zone is continuous along the length in gap, and in other embodiments, and halo N-type zone is discontinuous along the length in gap.In certain embodiments, bridge is a plurality of discontinuous section along the length in gap, and each section is continuous on the width in gap, and each section separates along the length in gap and adjacent section.In certain embodiments, each section has p type island region territory and haloN type zone.In other embodiments, each section comprises the p type island region territory, and only has selected section to comprise halo N-type zone.
In certain embodiments, power transistor comprises the lateral double diffusion metal oxide semiconductor field-effect transistor.In certain embodiments, the substrate of doping also is included in the drift region in the second doped region, and wherein drift region is positioned at beneath trenches.In certain embodiments, power transistor also comprises the conductive drain terminal that is coupled to drain electrode and the conductive source terminal that is coupled to source electrode, and wherein source terminal is coupled to field plate via conductive trace.In certain embodiments, substrate comprises silicon substrate.In certain embodiments, source electrode comprises that double diffusion is regional.
In another aspect, a kind of method of making power transistor is disclosed.The method comprises: substrate is adulterated to be formed on source electrode and channel region and the drain electrode in the second doped region and transitional region in the first doped region, wherein channel region is between source electrode and transitional region, and transitional region is between channel region and drain electrode; Press close to drain electrode and form groove in the part of transitional region; Come filling groove with field oxide; Grid oxic horizon is applied on the top surface of substrate; Form conductive layer on the part of channel region, transitional region and groove, remove the part on the first of transitional region of conductive layer, thereby form two conductive layer parts of separating by separated, this conductive layer partly comprise the first conductive layer part on the first that is positioned at channel region and transitional region and be positioned at the second portion of transitional region and this part of groove on the second conductive layer part; Form conductive trace so that the second conductive layer partly is electrically coupled to source electrode; And this part at conductive layer of transitional region is removed and third part that the gap location that forms exposes is adulterated, thereby form doping bridge zone between the second portion of the first of transitional region and transitional region.
Description of drawings
Several exemplary embodiments have been described with reference to the drawings, similar Reference numeral are provided wherein for similar parts.Exemplary embodiment is used for illustrating the present invention rather than restriction the present invention.Accompanying drawing comprises following figure:
Fig. 1 shows the cross sectional side view of the exemplary configurations of conventional lateral direction power MOSFET;
Fig. 2 shows the cross sectional side view according to the power transistor of the separated grid landscape configuration of an embodiment;
Fig. 3 shows the gate charge curve of the separated grid power MOSFET of conventional power MOSFET (for example, as shown in Figure 1 power MOSFET) and Fig. 2;
Fig. 4 shows the cross sectional side view according to the power transistor of the separated grid landscape configuration of another embodiment;
Fig. 5 shows the form of the characteristic corresponding with comparable power transistor;
Fig. 6 shows according to the vertical view of the part of the separated grid power transistor with discontinuous bridge of an embodiment (top down view); And
Fig. 7 shows the form of the characteristic corresponding with comparable power transistor.
Embodiment
The application's embodiment relates to the separated grid power transistor.Those of ordinary skill in the art will recognize, the separated grid power transistor that the below describes in detail is only illustrative, and never it should be thought restrictive.Those skilled in the art in benefit of this disclosure will easily expect other embodiment of this separated grid power transistor.
Now will detailed implementation with reference to separated grid power transistor as depicted in the figures.Identical reference designator will whole accompanying drawings and below detailed description in be used to refer to same or analogous part.For the sake of clarity, do not illustrate and describe all conventional features of implementation as herein described.Certainly, be to be appreciated that in the exploitation of any actual implementation like this, must make the distinctive a lot of decisions of implementation, in order to realize developer's specific objective, for example observe the constraint relevant with application and business; And these specific targets will change because of the difference of implementation and developer's difference.And, should be realized that, such development effort may be complicated and consuming time, but for benefiting from those of ordinary skills of the present disclosure, such development effort is only born the routine matter of engineering.
The embodiment of separated grid power transistor comprises the power MOSFET of landscape configuration, and it comprises the silicon substrate of doping, the grid oxic horizon that forms and the separation polysilicon layer that forms on grid oxic horizon on the surface of substrate.Polysilicon layer is cut into the parts of opened by separated two electricity isolation, the second portion that namely forms the first of the polysilicon gate on the first of the channel region that is positioned at substrate and transitional region and be formed on the polysilicon field plate that forms on the second portion of transitional region of substrate.Field plate also extends on the drift region of substrate, wherein the drift region beneath trenches of field oxide that has been located at the filling that forms in substrate.Field plate is electrically coupled to the source electrode of power transistor.
Cut polysilicon layer on transitional region.Cause because a large portion of grid capacitance is the part due to the polysilicon gate that forms on transitional region, reduced grid capacitance so remove the polysilicon that cuts on transitional region, and therefore reduced gate charge.For given conducting resistance, per cycle of separated grid structure reduces about 50% with gate charge.How soon the gate charge decision turn-on and turn-off switch.Reduce gate charge and allow to switch faster under the same efficiency of whole system, and therefore allow higher frequency.Higher frequency allows to use less discrete parts, and this has reduced cost.But the separated grid power transistor structure is applicable to the power IC of all switches with internal switch.This structure is not limited to integrated MOS FET.The separated grid power transistor structure can be applied to integrated or discrete any lateral direction power MOSFET.
Fig. 2 shows the cross sectional side view according to the power transistor of the separated grid landscape configuration of an embodiment.In this exemplary configurations, power transistor is N raceway groove bilateral diffusion MOS FET (N raceway groove DMOSFET).Substrate 110 is doped to form p type island region territory 112 and N-type zone 114.P type island region territory 112 comprises the double diffusion source electrode 116 with the fusion contact site 124 between P+ zone 120 and N+ zone 122.Contact site 124 is shorted together P+ zone 120 and N+ zone 122.Contact site 124 is as the source electrode contact site of separated grid power transistor, and source electrode is shorted to the main body of P type substrate.The p type island region territory is upper extension of the whole length of the bottom of substrate 110 (being included under the N-type zone 114 of right-hand side of Fig. 2).Source electrode contact terminal 142 is coupled to contact site 124 and therefore is coupled to source electrode 116.Substrate 110 also is doped to be formed on the N+ zone 118 in N-type zone 114.N+ zone 118 is as the drain electrode of separated grid power transistor.Drain electrode contact terminal 140 is coupled to drain electrode 118.Groove 126 is formed in the top surface of substrate 110.Groove 126 is filled with field oxide.In certain embodiments, groove 126 is to use shallow trench isolation to form from (STI) technique, and the groove that is filled with field oxide is called as sti region.In other embodiments, form groove 126 with the part that can remove substrate with any conventional semiconductor fabrication that forms thick oxide in field.
Grid oxic horizon 128 is formed on the top surface of substrate 110.In certain embodiments, deposit grid oxic horizon with conventional semiconductor deposition process.Polysilicon layer is formed on grid oxic horizon 128.Then remove a part of polysilicon layer, thereby form the polysilicon segment of two electricity isolation.In certain embodiments, form polysilicon segment with conventional semiconductor deposition and etch process.The first polysilicon segment forms polysilicon gate 130.The second polysilicon segment forms field plate 132.Polysilicon gate 130 and field plate 132 are physically separated by gap 134, and gap 134 is corresponding to the polysilicon segment that removes.Insulation oxide 138 covers polysilicon gate 130 and field plate 132.As shown in Figure 2, the grid oxic horizon 128 between polysilicon gate 130 and substrate 110 and the grid oxic horizon 128 between field plate 132 and substrate 110 are thin oxide layers.Field plate 132 is by gap 134 and polysilicon gate 130 electricity isolation, and field plate 132 is electrically coupled to source electrode 116.In a lot of the application, power transistor is arranged as has a lot of cross one another, for example source stripes, gate bar and drain bar.For example, drain bar plays drain electrode contact terminal 140, and source stripes plays source electrode contact terminal 142.In the separated grid power transistor, grid and field plate also can be arranged to the bar by separated.For example, the field plate bar plays the field plate contact terminal, and this field plate contact terminal schematically is shown field plate contact terminal 144 in Fig. 2.With reference to figure 2, bar is oriented to and enters and leave the page.If it can be the end of long its of hundreds of micron that grid normally is connected to, field plate extends into a bar similarly, and this end is electrically connected to source stripes by conductive trace.Fig. 2 is at the conceptive conductive trace 146 that this point is shown coupling field plate contact terminal 144 and source electrode contact terminal 142.Alternatively, can along the whole length of device or along the incoming call of the periodicity contact point on device length coupling field plate 132 and source electrode 116, wherein the length of device enters and leaves the page of Fig. 2.In these optional structures, the gap is cut in oxide 138 to be provided to the contact inlet point of field plate 132.Contact point or location in each expectation cut out the gap in oxide 138.
Three main region relevant with the operation of separated grid power transistor, i.e. channel region, transitional region and drift regions are arranged in substrate 110.Channel region be formed under polysilicon gate 130 and the p type island region territory 112 of substrate 110 in.In other words, form channel region, wherein polysilicon gate 130 and p type island region territory 112 are overlapping.Drift region is the part under groove 126 or sti region in N-type zone 114.Drift region is for supporting that high gate-to-drain voltage is necessary.On the contrary, if field plate 132 terminates on thin grid oxide layer, this will cause the too high voltages on grid oxic horizon, and the separated grid power transistor will not worked.Similarly, sti region and the field plate extension on sti region are necessary to reducing high gate-to-drain voltage.
Transitional region is the part under grid oxic horizon 128, gap 134 and field plate 132 in N-type zone 114.When the conducting of separated grid power transistor, transitional region provides the current flow path from the channel region to the drift region.Transitional region is also referred to as accumulator region or neck region.
Fig. 3 shows the gate charge curve of the separated grid power MOSFET of conventional power MOSFET (for example, power MOSFET shown in Figure 1) and Fig. 2.The gate charge curve is the public factor of quality of MOSFET.In order to determine gate charge, drain electrode is connected to the nominal supply power voltage by load resistance, source ground, and grounded-grid.Constant current is applied in grid, and measures grid-source voltage Vgs.When supply power voltage was applied to grid, grid-source voltage Vgs began to rise, until reach threshold voltage, threshold voltage is 1.5V in this example.Threshold voltage is corresponding to the flat of curve, and this flat is the place that power transistor begins conducting.When grid-source voltage Vgs reached quota and decides voltage (in this example, it is 5V that this quota is decided voltage), trace stopped.Gate charge is defined as the integration of measured voltage.In example shown in Figure 3, for the power MOSFET of the operating voltage of the specified grid-source voltage with 5V and 24V, measure the gate charge curve.Usually, in the situation that needn't increase the area of coverage of the polysilicon of the active grid that is used to form the separated grid power transistor and field plate, operating voltage range is that 14V is to 60V.
Also can see, with the flat comparison of curve 210, the flat of curve 200 has reduced about 75%.Flat represents gate-to-drain charge Q gd, and this gate-to-drain charge Q gd is the integration of gate-to-drain voltage on flat site.In flat site, increasing electric current is forced in grid, but grid-source voltage remains unchanged.Gate-to-drain charge Q gd is relevant with the feedback capacity between drain and gate.Usually, grid is positioned at that part on drain well is exaggerated and than the part that is positioned on source well of grid, gate charge is had larger impact.As completing in the separated grid power transistor, field plate is electrically connected to source electrode effectively conductive shields is placed between grid and drain electrode.This has reduced the feedback capacity relevant with the Miller effect.The flat that reduces on the gate charge curve reflected feedback capacity this reduce.
The separated grid power transistor has been realized the reducing of product of conducting resistance (R) and gate charge (Qg).When transistor turns, the conducting resistance of power MOSFET is the resistance between drain electrode and source electrode.Yet the product (being called the feature conducting resistance) of conducting resistance (R) and gate area (A) has slight increase.The feature conducting resistance provides the conceptual tolerance of the size of power transistor.The feature conducting resistance of separated grid structure can't increase due to the increase of physics gate area A, and this is to keep identical with half spacing of the comparable conventional power transistor with single polysilicon bar because have half spacing of the separated grid power transistor of two polysilicon strips.On the contrary, the feature conducting resistance is because the increase of conducting resistance R increases.When the complete conducting of separated grid power transistor, for example when grid-source voltage Vgs=5V, the electric current channel region of flowing through is transverse in transistor area and the drift region of the beneath trenches that is filled with field oxide, and gets back to the N+ drain electrode.Cover in the conventional structure of whole transitional region at polysilicon gate, the polysilicon gate on transitional region is in 5V, and this builds up electronics in transitional region.When grid-source voltage Vgs is timing, think that transitional region is built up, and nonreversible.In the situation that during more electronics accumulated in transitional region, resistance had reduced.Yet in separated grid structure, the part on transitional region of polysilicon gate is removed, and remainder (field plate) is connected to source electrode, rather than the 5V of active grid.Therefore, in the transitional region in the part that electronics only accumulates in directly and polysilicon gate is overlapping.The part under polysilicon field plate and Separation of transitional region is not built up, and only has the natural equilibrium concentration of electronics.Compare with the non-grid structure that separates, less electronics is arranged in transitional region, this causes higher resistance.In exemplary application, (for example lateral direction power MOSFET of Fig. 1) compares with the comparable conventional power transistor that there is no separated grid structure, the R*Qg product have about 44% reduce and the R*A product has about 12% increase.
The separated grid power transistor has also improved the hot carrier life-span, and this is because the field plate of ground connection guides On current away from grid oxic horizon, thereby has reduced iunjected charge to the mobile impact of the on state current of device inside.Field plate has reduced the electric field of any given supply power voltage, and this has kept the puncture voltage of separated grid power transistor effectively.Usually, separated grid structure and the groove that is filled with field oxide have been avoided the premature breakdown of separated grid power transistor.In separated grid structure, field plate extends on sti region, and field plate is electrically connected to source electrode.The recruitment of the source electrode-capacitance of drain that produces is more smaller than the decrease of gate-to-drain electric capacity.Therefore, source electrode-capacitance of drain is higher, but has generally speaking improved efficient.
In exemplary application, be manufactured on the gap 134 (Fig. 2) of the cutting between polysilicon gate 128 and field plate 132 with the semiconductor processing techniques of 0.18 micron, this obtains 0.25 micron wide gap.Yet the gap can be greater than or less than 0.25 micron, and the size in gap only is subject to available technology.For example, adopt the semiconductor fabrication of 0.13 micron can obtain the gap width of 0.2 micron.In fact, the gap can allow the same littlely with technology, thereby minimizes transistorized overall size, for example half spacing.Usually, compare with the comparable power transistor that there is no separated grid structure, realized the formation of separated grid power transistor, and do not increased by half spacing.
Compare with comparable power transistor especially, hereinafter emphasize some electrical characteristics of the separated grid power transistor of Fig. 2.At first, conducting resistance higher a little (device for 24V is approximately high by 12%), this is that transitional region is no longer built up because when break-over of device.Field plate is connected to source electrode, so field plate is grounded, and transitional region does not have so high electron concentration.Secondly, due to less gate area, so grid capacitance and gate charge reduce.The 3rd, because the field plate that source electrode connects is between grid and drain electrode, so greatly reduced the gate-to-drain feedback capacity.This has further reduced gate charge, and reason is between transfer period, and the Miller effect has amplified gate-to-drain electric capacity.The 4th, the peak value ionization by collision reduces, and makes the hot carrier life-span improve.Perhaps, for the given hot carrier life-span, half spacing reduces.The 5th, the efficient of switched-mode power supply (SMPS) has improved.
The embodiment of the separated grid power transistor that the above describes in Fig. 2 provides afore-mentioned characteristics by field plate polysilicon and grid polycrystalline silicon being separated and field plate being connected to source electrode.In the operating period of adopting high drain voltage, set up the inversion layer in hole under the field plate polysilicon.For thin grid oxide layer, the voltage-drop that this inversion layer causes on the grid oxic horizon below field plate is greater than the maximum for the permission of reliable operation.Rated operational voltage at the separated grid power transistor is in the exemplary application of 14V, when drain electrode-source voltage Vds is 14V, the voltage-drop of 4.1V is arranged on the grid oxic horizon under field plate 132.Voltage-drop although it is so is good to enough thick grid oxic horizon, but the voltage-drop that 10 years reliable operations of the grid oxic horizon of the thinner for example 85A of this voltage-drop ratio allow is much higher.For the thick grid oxic horizon of for example 85A, the maximum voltage landing on grid oxic horizon is less than about 3.3V.
The reason of the voltage-drop on the grid oxic horizon in the structure of Fig. 2 is to have the inversion layer in hole under field plate 132.These holes may be due to as the heat seen in common metal-oxide-silicon (MOS) interface generate and cause.
In order to eliminate this inversion layer in hole, inject lightly doped region under the gap between field plate and polysilicon gate.As put on exemplary N channel structure shown in Figure 2, N-type zone under the gap is injected in doped with P type zone, this doped with P type zone is also referred to as the P bridge.This P type bridge force transitional region the exhausting to enter deeply under help and exhaust at the intrinsic P-N knot that forms between P type bridge and transitional region of the part under field plate 132.The formation that deeply exhausts hinders any formation of the inversion charge under field plate, thereby discharges the voltage in this zone.Largest gate oxide layer voltage is reduced to for the level than the thin grid oxide layer safe handling.
Fig. 4 shows the cross sectional side view according to the power transistor of the separated grid landscape configuration of another embodiment.Except the separated grid power inverter of Fig. 4 comprised the bridge of below, gap in the substrate part, that be arranged in polysilicon gate and field plate, the exemplary separated grid power inverter of Fig. 4 was similar to the separated grid power inverter of Fig. 2.As shown in Figure 4, substrate 210 is doped to comprise bridge 236.In certain embodiments, bridge 236 is doped with P type zones.Bridge 236 is used for forcing the part below field plate 232 to enter the formation that deeply exhausts and prevent inversion layer.When with as at the separated grid power transistor that does not comprise bridge shown in Fig. 2 relatively the time, the P type bridge 236 that comprises has reduced the just in time electrostatic potential below field plate.The generation of static electricity that reduces is used for making the hole away from the path of field plate below, and therefore there is no so large voltage-drop on grid oxic horizon.In certain embodiments, bridge is injected into.Should be appreciated that and to adopt such as other conventional doping techniques such as diffusions, as long as this technology allows correctly to apply lightly doped region.In certain embodiments, with the treatment step of carrying out as the part of the power transistor manufacturing process bridge that adulterates.Alternatively, can carry out the doping content that extra treatment step customizes bridge on request.
Fig. 5 shows the form of the characteristic corresponding with comparable power transistor.The first row is for the conventional power transistor with continuous grid, for example power transistor shown in Figure 1.Second hand-manipulating of needle is to having the power transistor of separated grid, for example separated grid power transistor shown in Figure 2.The third line is for the separated grid power transistor with bridge, for example separated grid power transistor shown in Figure 4.The row that are labeled as " R*A " are feature conducting resistance, and wherein R is conducting resistance, and A is gate area.The row that are labeled as " △ R*A " are that the percentage of the special conducting resistance relevant with the continuous grid power transistor of the first row changes.Be labeled as " Q
G" row are gate charges.Be labeled as " R*Q
G" row are products of conducting resistance and gate charge.Be labeled as " △ R*Q
G" row be the conducting resistance relevant with the continuous grid power transistor of the first row and gate charge both the percentage of product change.Be labeled as " BV
DSS" row are puncture voltages.Be labeled as " V
OX@BV " row are voltage-drops on grid oxic horizon under puncture voltage.Be labeled as " V
OX@hot " row are voltage-drops on grid oxic horizon under the hot carrier condition of worst case.
Value shown in the form of Fig. 5 is for the simulated power transistor with same size, and each transistorized rated operational voltage is 14V.For the power transistor structure of the thickness of grid oxide layer with 85A, the maximum rated voltage-drop on grid oxic horizon is 3.6V.As " the V at Fig. 5
OX@BV " shown in row, have " the V of 4.1V
OX@BV " " separation " grid power transistor be unacceptable.Yet it will be acceptable that " continuously " power transistor or " separation (split with bridge) with bridge " power transistor are used for 14V Vds." separation with bridge " power transistor has reduced the voltage-drop on the grid oxic horizon, and so it is applicable to thinner thickness of grid oxide layer.Yet, realized gate charge and R*Q although compare " having separating of bridge " power transistor with conventional " continuously " power transistor
GReducing of product, still " separation with bridge " power transistor has+deterioration (penalty) of 30% large special conducting resistance.Increase by 30% for the feature conducting resistance, the R*Q of " separation with bridge " power transistor
GProduct has reduced 27%.
In optional embodiment, the bridge 236 of Fig. 4 also has been doped lightly doped region, N-doped region for example, and it is positioned at the halo between doped with P type part and N-type zone 214.In certain embodiments, light dope halo N-type zone is injected into.Should be appreciated that, can adopt such as other conventional doping techniques such as diffusions, as long as this technology allows correctly to apply lightly doped region.In certain embodiments, the doping content of the doped with P type of bridge part is about 10
18Scope in, and the doping content in the light dope halo N-type zone of bridge is about 10
17Scope in.The deterioration of the special conducting resistance of seeing has been eliminated in the interpolation in light dope halo N-type zone in having the separated grid structure of bridge.With reference to the form of figure 5, fourth line is for the separated grid power transistor with the bridge that comprises halo.As shown in Figure 5, in fact " separation with bridge/halo " power transistor has reduced 3% with the feature conducting resistance.Compare with " continuously " power transistor, " separation " power transistor and " having separating of bridge " power transistor, " separation with bridge/halo " power transistor has also reduced gate charge and R*Q
GProduct.
It is continuous on both that the bridge of describing in the context of Fig. 5 is configured in the length in the width of crossing over the gap between field plate and grid and gap, and no matter whether this bridge comprises halo.The length in gap enters and leaves the page of Fig. 4.In optional structure, the width of the bridge on the gap keeps continuously, but length is discontinuous.For example, can arrange along the every 1-2 μ of the length direction in gap m the bridge of 0.25 μ m.The use of discontinuous bridge has reduced the deterioration of feature conducting resistance, and prevents simultaneously the formation of hole inversion layer.
Fig. 6 shows the vertical view according to the part of the separated grid power transistor with discontinuous bridge of an embodiment.Being replaced by discontinuous bridge except the bridge of Fig. 4, the exemplary separated grid power transistor of Fig. 6 is similar to the separated grid power transistor of Fig. 4.Fig. 6 shows the part in grid 330, field plate 332 and gap 334.Two bridge section 336A and 336B represent discontinuous bridge.Should be appreciated that discontinuous bridge can comprise the bridge section of a plurality of two.Each bridge section 336A, 336B cross over the whole width W in gap 334, but are discontinuous on the length L in gap 334.Each bridge section 336A, 336B are similar with the bridge 236 of Fig. 4 on Structure and function.For example, each bridge section 336A, 36B can comprise that doped with P type zone or each bridge section 336A, 36B can comprise doped with P type zone and light dope halo N-type zone both.In certain embodiments, all bridge sections are all adulterated in the same manner, and for example all bridge sections all doped with doped with P type zone or all bridge sections all doped with doped with P type zone and light dope halo N-type zone both.In other embodiments, the bridge section can differently be adulterated, and for example some bridge sections have been doped doped with P type zone, and some bridge sections have been doped doped with P type zone and light dope halo N-type zone both.In other optional embodiment, the continuous bridge of Fig. 4 can be modified as and have discontinuous halo N-type zone.In this structure, gap length has the continuous doped with P type zone along the whole length in gap, and the section of bridge comprises that also the halo N-type is regional.
Discontinuous bridge prevents from forming the hole inversion layer under field plate, but there is no the deterioration without the special conducting resistance of bridge separated grid structure.Fig. 7 shows the form of the characteristic corresponding with comparable power transistor.The form of Fig. 7 shows the power transistor shown in form with Fig. 5 similar " continuously " power transistor, " separation " power transistor and " having separating of bridge " power transistor and " have the separating of discontinuous bridge " power transistor corresponding with the separated grid power transistor of Fig. 6.Although be both that similarly result shown in Figure 7 is not to compare with the result of Fig. 5, reason is that each result represents an independent simulation.The value of " separation with discontinuous bridge " power transistor shown in Figure 7 is corresponding to the discontinuous bridge of the bridge section with doped with P type zone, but there is no halo N-type zone.Each bridge section has the length of 0.25 μ m on the spacing of 1.5 μ m.As shown in the form of Fig. 7, replace 24% the feature conducting resistance of " separation with bridge " power transistor to worsen, this deterioration is much lower.The sixth of device L has the R*L product than remainder high 24%, so the resistance of per unit length is only high by 3.4% more at all than the device that there is no bridge.Compare the R*Q of " separation with discontinuous bridge " power transistor with " continuously " grid power transistor
GProduct reduces 36%, and the deterioration of special conducting resistance only has 9%.
Usually, do not have the discontinuous bridge construction of bridge halo that the structure of the continuous bridge with bridge halo is provided.
In the embodiment that provides, bridge or bridge section are floated.In other words, bridge is not coupled to contact site.In other embodiments, bridge or bridge section are coupled to contact site.Contact site can be coupled to ground or an electromotive force.
The embodiment of separated grid power transistor is described to N-channel MOS FET in the above.Also can expect optional embodiment, for example the P channel mosfet.Be applied to the P channel mosfet and need slightly different structure.Can implement optional structure, wherein the separated grid power transistor is configured to opposite polarity aspect all with shown in described embodiment of its Semi-polarity.
Above, it is polysilicon that grid material is described as.Alternatively, grid can be made by any conventional material that uses in the manufacturing of semiconductor transistor, includes but not limited to polysilicon and/or metal.Silicon above substrate being described as.Alternatively, substrate can be based on the compound of silicon, for example SiGe (SiGe).
The application has been described aspect the specific embodiment of details containing, so that understand the structure of separated grid power transistor and the principle of operation.Shown in each figure and a lot of parts of describing all can exchange, obtaining needed result, and this specification also should be read to contain such exchange.Therefore, specific embodiment and the details thereof mentioned of this paper is not to limit the scope of claims.It should be apparent to those skilled in the art that and to modify to the embodiment that is selected for for example, and do not depart from the application's spirit and scope.
Claims (37)
1. power transistor comprises:
a. the substrate that adulterates, it is included in source electrode and channel region in the first doped region, drain electrode in the second doped region, bridge, First Transition zone and the second transitional region, and the groove in described the second doped region, wherein said groove is formed in the first surface of described substrate, and described trench fill has insulating material, in addition, wherein said channel region is between described source electrode and described First Transition zone, described First Transition zone is between described channel region and described bridge, described bridge location is between described First Transition zone and described the second transitional region, described the second transitional region is between described bridge and described groove, and described groove is between described the second transitional region and described drain electrode,
B. grid oxic horizon, it is positioned on the described first surface of described substrate;
C. grid, its be positioned on described grid oxic horizon and be positioned at described channel region and described First Transition zone on; And
D. field plate, it is positioned on described grid oxic horizon and is positioned on the part and described the second transitional region of described groove, wherein said grid separates with described field plate by the gap that is positioned on described bridge, and in addition, wherein said field plate is electrically coupled to described source electrode via conductive trace.
2. power transistor as claimed in claim 1, wherein said grid and described field plate comprise polysilicon.
3. power transistor as claimed in claim 1, wherein said the first doped region is the p type island region territory, and described the second doped region is the N-type zone.
4. power transistor as claimed in claim 3, wherein said bridge comprise the p type island region territory.
5. power transistor as claimed in claim 4, wherein said bridge comprises doped with P type infusion.
6. power transistor as claimed in claim 4, wherein said bridge comprise that also the N-type of the halo between described second transitional region of the described First Transition zone of the described p type island region territory that is positioned in described bridge and N-type and N-type is regional.
7. the described N-type zone in power transistor as claimed in claim 6, wherein said bridge comprises light dope N-type infusion.
8. power transistor as claimed in claim 6, wherein said bridge is continuous on the width in described gap, and described bridge is continuous along the length in described gap.
9. power transistor as claimed in claim 6, wherein said bridge comprises a plurality of discontinuous section along the length in described gap, each section is continuous on the width in described gap, and each section separates along the length in described gap and adjacent section.
10. power transistor as claimed in claim 4, wherein said bridge is continuous on the width in described gap, and described bridge is continuous along the length in described gap.
11. power transistor as claimed in claim 10, wherein said bridge also comprises a plurality of discontinuous N-type zone along the length in described gap, and each discontinuous N-type section is positioned at the halo between described second transitional region of the described First Transition zone of the part in the described p type island region territory in described bridge and N-type and N-type.
12. power transistor as claimed in claim 4, wherein said bridge comprises a plurality of discontinuous section along the length in described gap, each section is continuous on the width in described gap, and each section separates along the length in described gap and adjacent section.
13. power transistor as claimed in claim 12, one or more sections of wherein said bridge comprise that also the N-type of the halo between described second transitional region of the described First Transition zone of described p type island region territory and N-type in the described section that is positioned at described bridge and N-type is regional.
14. power transistor as claimed in claim 1, wherein said power transistor comprises the lateral double diffusion metal oxide semiconductor field-effect transistor.
15. power transistor as claimed in claim 1, the substrate of wherein said doping also are included in the drift region in described the second doped region, wherein said drift region is positioned at the below of described groove.
16. power transistor as claimed in claim 1 also comprises the conductive drain terminal that is coupled to described drain electrode and the conductive source terminal that is coupled to described source electrode, wherein said source terminal is coupled to described field plate via described conductive trace.
17. power transistor as claimed in claim 1, wherein said substrate comprises silicon substrate.
18. power transistor as claimed in claim 1, wherein said source electrode comprise that double diffusion is regional.
19. a method of making power transistor, described method comprises:
A. substrate is adulterated to be formed on source electrode and channel region and the drain electrode in the second doped region and transitional region in the first doped region, wherein said channel region is between described source electrode and described transitional region, and described transitional region is between described channel region and described drain electrode;
B. press close to described drain electrode and form groove in the part of described transitional region;
C. fill described groove with field oxide;
D. grid oxic horizon is applied on the top surface of described substrate;
E. form conductive layer on the part of described channel region, described transitional region and described groove;
F. remove the part on the first of described transitional region of described conductive layer, thereby form two conductive layer parts of separating of being separated by the gap, described two conductive layers that separate partly comprise the first conductive layer part on the first that is positioned at described channel region and described transitional region and be positioned at the second portion of described transitional region and this part of described groove on the second conductive layer part;
G. form conductive trace so that described the second conductive layer partly is electrically coupled to described source electrode; And
H. to described transitional region, be removed and third part that the described gap location that forms exposes is adulterated in this part of described conductive layer, thereby it is regional to form the doping bridge between the described second portion of the described first of described transitional region and described transitional region.
20. method as claimed in claim 19, also be included in and form formation conductive drain terminal in conductive source terminal and the described drain electrode in described substrate on the described source electrode in described substrate, wherein said source terminal is electrically coupled to described the second conductive layer via described conductive trace.
21. method as claimed in claim 19, wherein said grid and described field plate comprise polysilicon.
22. method as claimed in claim 19, wherein said the first doped region is the p type island region territory, and described the second doped region is the N-type zone.
23. method as claimed in claim 22, wherein said bridge comprise the p type island region territory.
24. method as claimed in claim 23, wherein said bridge comprise doped with P type infusion.
25. method as claimed in claim 23, wherein said bridge comprise that also the N-type of the halo between described second transitional region of the described First Transition zone of the described p type island region territory that is positioned in described bridge and N-type and N-type is regional.
26. method as claimed in claim 25, the described N-type zone in wherein said bridge comprises light dope N-type infusion.
27. method as claimed in claim 25, wherein said bridge are continuous on the width in described gap, and described bridge is continuous along the length in described gap.
28. method as claimed in claim 25, wherein said bridge comprises a plurality of discontinuous section along the length in described gap, each section is continuous on the width in described gap, and each section separates along the described length in described gap and adjacent section.
29. method as claimed in claim 23, wherein said bridge are continuous on the width in described gap, and described bridge is continuous along the length in described gap.
30. method as claimed in claim 29, wherein said bridge also comprises a plurality of discontinuous N-type zone along the described length in described gap, and each discontinuous N-type section is positioned at the halo between described second transitional region of the described First Transition zone of the part in the described p type island region territory in described bridge and N-type and N-type.
31. method as claimed in claim 23, wherein said bridge comprises a plurality of discontinuous section along the length in described gap, each section is continuous on the width in described gap, and each section separates along the described length in described gap and adjacent section.
32. method as claimed in claim 31, one or more sections of wherein said bridge comprise that also the N-type of the halo between described second transitional region of the described First Transition zone of described p type island region territory and N-type in the described section that is positioned at described bridge and N-type is regional.
33. method as claimed in claim 19, wherein said power transistor comprises the lateral double diffusion metal oxide semiconductor field-effect transistor.
34. method as claimed in claim 19, the substrate of wherein said doping also are included in the drift region in described the second doped region, wherein said drift region is positioned at the below of described groove.
35. method as claimed in claim 19, wherein said substrate comprises silicon substrate.
36. method as claimed in claim 19, wherein said source electrode comprise that double diffusion is regional.
37. method as claimed in claim 19, wherein said groove uses shallow ditch groove separation process and forms.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/312,827 | 2011-12-06 | ||
| US13/312,827 US8987818B1 (en) | 2009-11-13 | 2011-12-06 | Integrated MOS power transistor with thin gate oxide and low gate charge |
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| CN103151375B CN103151375B (en) | 2017-10-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265478A (en) * | 2018-03-12 | 2019-09-20 | 恩智浦美国有限公司 | Transistor grooves structure with field plate structure |
| CN114334613A (en) * | 2022-03-14 | 2022-04-12 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| US7262476B2 (en) * | 2004-11-30 | 2007-08-28 | Agere Systems Inc. | Semiconductor device having improved power density |
| US7405443B1 (en) * | 2005-01-07 | 2008-07-29 | Volterra Semiconductor Corporation | Dual gate lateral double-diffused MOSFET (LDMOS) transistor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265478A (en) * | 2018-03-12 | 2019-09-20 | 恩智浦美国有限公司 | Transistor grooves structure with field plate structure |
| CN114334613A (en) * | 2022-03-14 | 2022-04-12 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN114334613B (en) * | 2022-03-14 | 2022-06-17 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
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