CN103136162A - ASIC (application specific integrated circuit) on-chip cloud architecture and design method based on same - Google Patents
ASIC (application specific integrated circuit) on-chip cloud architecture and design method based on same Download PDFInfo
- Publication number
- CN103136162A CN103136162A CN2013100746309A CN201310074630A CN103136162A CN 103136162 A CN103136162 A CN 103136162A CN 2013100746309 A CN2013100746309 A CN 2013100746309A CN 201310074630 A CN201310074630 A CN 201310074630A CN 103136162 A CN103136162 A CN 103136162A
- Authority
- CN
- China
- Prior art keywords
- spn
- processing node
- application
- name
- sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Devices For Executing Special Programs (AREA)
- Stored Programmes (AREA)
Abstract
The invention aims to provide an on-chip cloud architecture for a functional integrated circuit and particularly provides an ASIC (application specific integrated circuit) and a design method based on the same. A demand model, a semantic model and a service model of an SOA (service oriented architecture) are mapped to an ASIC chip through an on-chip read-only bus BoW, and an on-chip cloud basic frame IF. The functional integrated circuit is implemented by organizing according to engine and sematic process and computing resources, so that the functional integrated circuit is available for reconfiguration in both dimensions of syntactic element and semantic process and the design method of directly forming an integrated circuit chip by algorithm. Red-division of labor in the field of integrated circuit design is brought, part of labor is responsible for search and development of 'field universal' componentized IP (intellectual property cores), and the other part of labor is able to directly produce target integrated circuit chips by considering application process for 'raw chip' programming. Therefore, capability of designing system applications is improved greatly, and IC technological level space implemented by Moore's law is expanded and exploited.
Description
Technical field
The present invention relates to integrated circuit system field, be particularly related to the interior cloud architectural framework of sheet and the method for designing thereof of a kind of " blank chip ", from aspects such as framework, realization and application, having planned main profile and the feature of " blank chip ", is exactly specifically cloud framework and the ASIC method for designing from algorithm to chip through train formula based on this framework in a kind of ASIC sheet.
Background technology
Moore's Law shows, the integrated level to 2013 of integrated circuit (IC) chip year will reach 4,400,000,000 transistors.Continue 22nm(Intel) and the 20nm(Samsung) after technology, within 2012, IBM announces to have had the 9nm technology.What form distinct contrast therewith is that the development of IC chip architecture and design method seriously lags behind, and based on von Neumann architecture depended software, realizes that the design concept of system occupies the main flow of IC produce market for a long time.Be present in this advanced technologies level of the whole industry and fall behind the huge drop between the system ability, to us, having shortly the ability that manufactures and designs of the top IC chip of development under process conditions that unrivalled opportunity is provided.Unanimously prediction in the industry, 2018-2028 semiconductor products will revert to the U-SoC product of " general ", it is characterized in that the low-power consumption, high-level efficiency of autonomous dynamic restructuring, configuration flow " blank chip (Raw Chip) " cheaply.People only just can obtain user-defined functional circuit by the programming of the configuration to chip, thus the structural evolution of guiding semiconductor industry, and promotion is not done chip design and is specialized in the rise without design (Designless) business model that chip application is innovated.
The appearance of the single-chip cloud computing machine SCC that the universal cpu of take is node, indicate that integrated circuit has entered the cloud epoch in sheet.Improve the infosystem performance, Moore's Law is by reduction of device size, and cloud computing is by enlarging computer cluster, and in sheet, cloud is to come from the Resources on Chip space bonus of Moore's Law with the digestion of cloud framework.But, for concrete application, the integrated thousands of general processors of single-chip may mean that silicon area corresponding to a large amount of instruction constants is wasted; Along with the processor number increases, bus is in the also sharply expansion of accounting of silicon area.
The universal cpu principal character is " engine driving ", it isolates syntactic element formation processing device instruction set from the semantic description for concrete application, it by program, is the sequence performance semantic logic of instruction, make " engine " driver by cpu controller during operation and carry out, make the infinite aggregate of semantic logic can be mapped to the finite set of syntactic element.Belong to the circuit structure feature of " signal driver " during the ASIC operation, syntactic element and semantic logic merge.
Summary of the invention
The objective of the invention is in order to solve above-mentioned problems of the prior art, and cloud framework and the method for designing based on this framework in a kind of ASIC sheet are provided.The present invention is specifically by the demand of SOA, semanteme and service three layer model, by in the sheet the present invention relates to a write bus BoW(BoW:Bus only Write) be mapped to asic chip, set up cloud basic framework IF(IF:Infrastructure Framework in sheet), according to engine, semantic flow process and calculation resources remove to organize the practical function integrated circuit, make its equal restructural on syntactic element and two dimensions of semantic flow process, formation directly generates the DACC(DACC:ASIC Design Approach based on Cloud on Chip of integrated circuit (IC) chip from algorithm) method for designing.
The present invention is achieved by the following technical solutions:
Cloud framework in a kind of ASIC sheet, comprise an interior cloud basic framework IF of sheet that meets SOA three-tier architecture model, for concrete application, cloud basic framework IF instantiation in sheet formed to asic chip, SOA three-tier architecture model comprises demand layer conceptual model, semantic layer logical model and service layer's physical model, the demand layer is asic chip and extraneous interface, extension and the intension of the concrete application of definition, establish whole value that asic chip can provide, produce and describe relevant basic semantic concept and the grammatical feature of application scenarios, semantic layer has defined application layer language LL7 for concrete application, and concrete application scenarios is described as semantic flow process with application layer language LL7, pays application engine AE and processes, application layer language LL7 is comprised of the irrelevant part LL7-PI of problem and contact problem part LL7-PS two parts, the irrelevant part LL7-PI of problem is essential to all applications, the irrelevant part LL7-PI of problem realizes the grammatical feature of application engine AE, and contact problem part LL7-PS relates to the concrete concept of concrete application and is the set that realizes corresponding atomic operation AO, service layer is the set of the atomic operation AO that in the ASIC sheet, cloud provides, comprises flow process control operation and calculation process operation, is packaged into the instruction set that Atomic component AC forms cloud basic framework IF in sheet, in sheet, cloud basic framework IF comprises a write bus BoW and corresponding message passing mechanism in elementary cell IU, sheet, described elementary cell IU comprises a main processing node MPN and several are from processing node SPN
1, SPN
2..., SPN
n, main processing node MPN and several are from processing node SPN
1, SPN
2..., SPN
nunified node interface UNI by separately be connected in sheet, on a write bus BoW, realize interconnected, in described, a write bus BoW comprises two transmission of messages passages and a bar state bus FLAG, main processing node MPN exclusively enjoys a piece of news transmission channel, make the processing node MPN of winner send message frame from processing node SPN to all, several are from processing node SPN
1, SPN
2..., SPN
nshare another transmission of messages passage, make several from processing node SPN
1, SPN
2..., SPN
ncan distinguish independently and send message frame to main processing node MPN, status bus FLAG(is existing known technology, and its principle, application etc. are all well-known to those skilled in the art) with solving several from processing node SPN
1, SPN
2..., SPN
nsend the conflict that message frame causes simultaneously, when certain from processing node SPN
xfirst detected state bus FLAG while sending message frame, the default setting of status bus FLAG is idle condition " 0 ", when detected state bus FLAG is idle condition " 0 ", first status bus FLAG is set to busy condition " 1 ", then send message frame, message frame is set to status bus FLAG idle condition " 0 " after sending and finishing again, when detected state bus FLAG is busy condition " 1 ", according to priority and algorithmic characteristic, a setting commonly used that time delay, this method to set up of △ T(was this field is set, that those skilled in the art know and easily realize), △ T time delay detected state bus FLAG again after finishing, until status bus FLAG is while being idle condition " 0 ", first status bus FLAG is set to busy condition " 1 ", then send message frame, message frame is set to status bus FLAG idle condition " 0 " after sending and finishing again, the application engine AE that described main processing node MPN is elementary cell IU, it adopts general processor CPU, described is Atomic component AC from processing node SPN, Atomic component AC is comprised of Atomic component name AC-NAME and Atomic component entity A C-ENTITY two parts, wherein Atomic component entity A C-ENTITY consists of unified node interface UNI and atomic operation AO two parts, atomic operation AO is independently functional integrated circuit module or one IP kernel independently, for concrete application, completely specified output is arranged under given input, corresponding message passing mechanism comprises unified node interface access protocal UNIAP and unified Atomic component access protocal UACAP, unified node interface access protocal UNIAP belongs to link layer protocol, be responsible for message at main processing node MPN with from error free transmission between processing node SPN, unified Atomic component access protocal UACAP belongs to network layer protocol, be from defining in logic sign or the address of each Atomic component AC node, according to the access mode of Atomic component AC, formulate the message packing rule.
As shown in Figure 1, in sheet, three layers of SOA model of cloud comprise demand layer conceptual model, semantic layer logical model and service layer's physical model:
The demand layer is asic chip and extraneous interface, and extension and the intension of the concrete application of definition, establish whole value that asic chip can provide, and produces and describes relevant basic semantic concept and the grammatical feature of application scenarios.
Semantic layer has defined application layer language LL7 for concrete application, concrete application scenarios is described as semantic flow process with application layer language LL7, pay application engine AE(AE:Application Engine) process, application layer language LL7 divides be a problem irrelevant part LL7-PI and contact problem part LL7-PS, the irrelevant part LL7-PI of problem is essential to all applications, comprise: character set, data type, key word, expression formula, statement (branch, redirect, condition, circulation, addressing, assignment ...) etc. the basic controlling key element, the main realization with the grammatical feature of engine AE and relevant control operation, LL7-PS is for concrete application for contact problem part, comprise the concrete concept that concrete application relates to, computing, the basic syntax such as method and function key element, contact problem part LL7-PS is specifically in order to realize atomic operation AO(AO:Atom Operation) set, as shown in Figure 2, Atomic component AC is comprised of Atomic component name AC-NAME and Atomic component entity A C-ENTITY two parts, wherein Atomic component entity A C-ENTITY consists of unified node interface UNI and atomic operation AO two parts, atomic operation AO is independently functional integrated circuit module or one IP kernel independently, Atomic component AC specifically is packaged into by the asic chip IP kernel mode of operation encouraged by message, unified node interface UNI is responsible for reception and the parsing of message between Atomic component AC and outside, encapsulation and transmission, unified node interface UNI is packaged into atomic operation AO operating result the message that meets unified Atomic component access protocal UACAP, send to a write bus BoW, unified node interface UNI receives the message on a write bus BoW in case of necessity, according to unified Atomic component access protocal UACAP, resolve, generate the excitation information of access AO, drive AO to implement corresponding operation.
Service layer is the set of the atomic operation AO that in the ASIC sheet, cloud provides, comprises flow process control operation and calculation process operation, is packaged into the instruction set that Atomic component AC forms cloud basic framework IF in sheet.Each syntactic element functional module IP kernel of cloud is packaged into the subset of atomic operation set A O in sheet, is packaged into Atomic component AC after configuring a unified node interface UNI.
Further, described main processing node MPN selects sequencer SEQ to replace the application engine AE of general processor CPU as elementary cell IU, the parts that sequencer SEQ comprises have flow process queue, flow process counter, member queue, member counter and member code translator, and the flow process queue is used for storing the sign ID of the semantic flow process corresponding with the different application demand; The flow process counter is used to refer to the process identification ID be activated to current; The member queue is used for storing the application flow AP(AP:Application Processes corresponding with sign ID); application flow AP is the instruction sequence of basic framework IF; it is the sequence of Atomic component name AC-NAME; Atomic component name AC-NAME comprises atomic operation name AO-NAME and interface message IM(IM:Interface Message), specific definition is: AC-NAME=AO-NAME& IM; The member counter is used for determining the execution sequence of application flow AP, and the member counter points to the next Atomic component name AC-NAME that will carry out in the member queue; The message that generates access atomic operation AO resolved current Atomic component name AC-NAME process according to the syntax rule of application layer language LL7 by the member code translator, send in sheet a write bus BoW and activate corresponding Atomic component entity A C-ENTITY and implement concrete operations by unified node interface UNI, the member counter points to the next Atomic component name AC-NAME that will carry out simultaneously.
Describedly can also continue to connect elementary cell IU from processing node SPN, when from processing node SPN, connecting an elementary cell IU, this processing node SPN is as the main processing node MPN of the unit IU that reconnects again.
ASIC method for designing based on cloud framework in above-mentioned ASIC sheet, concept atom by the software field member, and be embodied as the instruction set of coarseness with logic semiconductor, utilize the interconnected Atomic component AC of a write bus BoW in sheet, form cloud basic framework IF in sheet, by definition application layer language, LL7 realizes basic framework IF, support the restructural of language view flow process, the customizability of ASIC is extended to syntactic element and two dimensions of meaning of one's words flow process, for specifically being used for defining application layer language LL7, then the use-case scene that will specifically apply is described as application flow AP with application layer language LL7, be deployed in the application engine AE of elementary cell IU and carry out.
In sum, the present invention relates to set up application layer language LL7(LL7:Language Level-7 for concrete application) and form bus on chip and interconnected mechanism thereof etc." blank chip " (asic chip) for concrete application definition is equivalent to an application layer language LL7, comprises " field instruction " collection (LL7.PS) and application flow engine (LL7.PI) two parts; Bus on chip structure and interconnected mechanism thereof realize cloud framework in sheet, comprise resource access protocol (application layer), unified Atomic component access protocal UACAP(network layer) and unified node interface access protocal UNIAP(link layer).The syntactic element of application layer language LL7 is embodied as to the functional integrated circuit IP kernel, is packaged into Atomic component AC(AC:Atom Component), such design has reduced the interconnected complicacy of pin between module, finally by interface, based on message, accesses; The various scenes of specifically application are described as take with application layer language LL7 the semantic flow process that Atomic component AC is instruction set, design special flow engine and drive execution, but introduce the semantic flow process of flexible configuration in the reconfigurable asic chip design of syntactic element, make " blank chip " also there is such " engine driving " ability of universal cpu, all can be by user program reconstruct on syntactic element and two dimensions of semantic flow process.
In the sheet the present invention relates to, the cloud architectural framework will be expanded out a class new type integrated circuit chip: the produce market of " blank chip ".Bring the division of labor again in integrated circuit (IC) design field, some people is absorbed in development and the exploitation of the componentization IP kernel of " field is general ", and another part people only need consider the application flow design, the personnel of application design needn't understand the background knowledge of integrated circuit, to " blank chip " programming, just can directly produce the target integrated circuit (IC) chip.The present invention is organically combined togather the order executive capability of traditional von Neumann general processor and the parallel processing capability of functional integrated circuit, greatly improve the system applies designed capacity, expand and excavate the IC technological level space bonus that Moore's Law is brought.
The accompanying drawing explanation
Fig. 1 is of the present invention interior cloud SOA three-tier architecture model.
Fig. 2 is Atomic component AC structural representation of the present invention.
A write bus BoW topology diagram in unidirectional serial sheet in Fig. 3 sheet.
Fig. 4 is message passing mechanism of the present invention.
Fig. 5 is sequencer SEQ structural representation of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
Cloud framework in a kind of ASIC sheet, comprise an interior cloud basic framework IF of sheet that meets SOA three-tier architecture model, for concrete application, cloud basic framework IF instantiation in sheet formed to asic chip, as shown in Figure 1, SOA three-tier architecture model comprises demand layer conceptual model, semantic layer logical model and service layer's physical model, the demand layer is asic chip and extraneous interface, extension and the intension of the concrete application of definition, establish whole value that asic chip can provide, produce and describe relevant basic semantic concept and the grammatical feature of application scenarios, semantic layer has defined application layer language LL7 for concrete application, concrete application scenarios is described as semantic flow process with application layer language LL7, paying application engine AE processes, application layer language LL7 is comprised of the irrelevant part LL7-PI of problem and contact problem part LL7-PS two parts, the irrelevant part LL7-PI of problem is essential to all applications, the irrelevant part LL7-PI of problem realizes the grammatical feature of application engine AE, and contact problem part LL7-PS relates to the concrete concept of concrete application and is the set that realizes corresponding atomic operation AO, service layer is the set of the atomic operation AO that in the ASIC sheet, cloud provides, comprises flow process control operation and calculation process operation, is packaged into the instruction set that Atomic component AC forms cloud basic framework IF in sheet, in sheet, cloud basic framework IF comprises a write bus BoW and corresponding message passing mechanism in elementary cell IU, sheet, described elementary cell IU comprises a main processing node MPN and several are from processing node SPN
1, SPN
2..., SPN
n, main processing node MPN and several are from processing node SPN
1, SPN
2..., SPN
nunified node interface UNI by separately be connected in sheet, on a write bus BoW, realize interconnected, as shown in Figure 3, in described, a write bus BoW comprises two transmission of messages passages and a bar state bus FLAG, main processing node MPN exclusively enjoys a piece of news transmission channel, make the processing node MPN of winner send message frame from processing node SPN to all, several are from processing node SPN
1, SPN
2..., SPN
nshare another transmission of messages passage, make several from processing node SPN
1, SPN
2..., SPN
ncan distinguish independently and send message frame to main processing node MPN, status bus FLAG is with solving several from processing node SPN
1, SPN
2..., SPN
nsend the conflict that message frame causes simultaneously, when certain from processing node SPN
xfirst detected state bus FLAG while sending message frame, the default setting of status bus FLAG is idle condition " 0 ", when detected state bus FLAG is idle condition " 0 ", first status bus FLAG is set to busy condition " 1 ", then send message frame, message frame is set to status bus FLAG idle condition " 0 " after sending and finishing again, when detected state bus FLAG is busy condition " 1 ", according to priority and algorithmic characteristic arrange one time delay △ T, △ T time delay detected state bus FLAG again after finishing, until status bus FLAG is while being idle condition " 0 ", first status bus FLAG is set to busy condition " 1 ", then send message frame, message frame is set to status bus FLAG idle condition " 0 " after sending and finishing again, the application engine AE that described main processing node MPN is elementary cell IU, it adopts general processor CPU, described is Atomic component AC from processing node SPN, as shown in Figure 2, Atomic component AC is comprised of Atomic component name AC-NAME and Atomic component entity A C-ENTITY two parts, wherein Atomic component entity A C-ENTITY consists of unified node interface UNI and atomic operation AO two parts, atomic operation AO is independently functional integrated circuit module or one IP kernel independently, for concrete application, completely specified output is arranged under given input, as shown in Figure 4, corresponding message passing mechanism comprises unified node interface access protocal UNIAP and unified Atomic component access protocal UACAP, unified node interface access protocal UNIAP belongs to link layer protocol, be responsible for message at main processing node MPN with from error free transmission between processing node SPN, unified Atomic component access protocal UACAP belongs to network layer protocol, be from defining in logic sign or the address of each Atomic component AC node, according to the access mode of Atomic component AC, formulate the message packing rule.
Further, described main processing node MPN selects sequencer SEQ to replace the application engine AE of general processor CPU as elementary cell IU, as shown in Figure 5, the parts that sequencer SEQ comprises have flow process queue, flow process counter, member queue, member counter and member code translator, and the flow process queue is used for storing the sign ID of the semantic flow process corresponding with the different application demand; The flow process counter is used to refer to the process identification ID be activated to current; The member queue is used for storing the application flow AP corresponding with sign ID; application flow AP is the instruction sequence of basic framework IF; it is the sequence of Atomic component name AC-NAME; Atomic component name AC-NAME comprises atomic operation name AO-NAME and interface message IM, and specific definition is: AC-NAME=AO-NAME& IM; The member counter is used for determining the execution sequence of application flow AP, and the member counter points to the next Atomic component name AC-NAME that will carry out in the member queue; The message that generates access atomic operation AO resolved current Atomic component name AC-NAME process according to the syntax rule of application layer language LL7 by the member code translator, send in sheet a write bus BoW and activate corresponding Atomic component entity A C-ENTITY and implement concrete operations by unified node interface UNI, the member counter points to the next Atomic component name AC-NAME that will carry out simultaneously.
Describedly can also continue to connect elementary cell IU from processing node SPN, when from processing node SPN, connecting an elementary cell IU, this processing node SPN is as the main processing node MPN of the elementary cell IU that reconnects again.
A kind of ASIC method for designing based on cloud framework in described ASIC sheet, be exactly by the concept atom of software field member, and be embodied as the instruction set of coarseness with logic semiconductor, utilize the interconnected Atomic component AC of a write bus BoW in sheet, form cloud basic framework IF in sheet, by definition application layer language, LL7 realizes basic framework IF, support the restructural of language view flow process, the customizability of ASIC is extended to syntactic element and two dimensions of meaning of one's words flow process, for specifically being used for defining application layer language LL7, then the use-case scene that will specifically apply is described as application flow AP with application layer language LL7, be deployed in the application engine AE of elementary cell IU and carry out.
Below design the AVS scrambler by cloud framework in ASIC sheet of the present invention and based on this framework ASIC method for designing, it should be noted that, this embodiment is only illustrative, the present invention is not done to any restriction.
This embodiment designs the AVS scrambler by cloud framework in ASIC sheet of the present invention and based on this framework ASIC method for designing, comprises 6 steps:
Step 1: AVS scrambler standard is carried out to system requirement analysis, set up three layers of SOA model, i.e. conceptual model, logical model and physical model, wherein conceptual model is used for defining the intension of AVS coding application, describing whole value that ASIC can provide, is the demand layer of cloud in sheet; Physical model is determined computing that the AVS scrambler is related or the set of operation, is the service layer of cloud in sheet; Logical model is mapped to physical model by conceptual model, specifically use-case is described as to the semantic flow process of scene, is the semantic layer of cloud in sheet;
Step 2: definition AVS encoder applies layer language avsLL7, wherein control member adopts general LL7-PI, be embodied as application engine avsEngine with VHDL, and the computing member is avsLL7-PS, be embodied as atomic operation set avsAO with VHDL, and be packaged into basic building block;
The basic building block set of AVS scrambler is:
avsBC={(8×8)X
1；
X
2 αγδ；
αλδ；
X
3⊕X
4⊕X
5；
X
8⊕X
7⊕X
2⊕
αβX
6}；
Wherein
α=pixel,
β=motion,
γ=brightness,
λ=colourity,
δ=interpolation,
1/4
α λ δ=1/4 pixel chroma interpolation;
Make X
1=(quantizing inverse quantization, DCT, IDCT, reconstruct, prediction), X
2=(whole, Asia, 1/4), X
3=(filtering, prediction, entropy coding), X
4=(in frame, interframe), X
5=(brightness, colourity), X
6=(search, compensation), X
7=(16 * 16,16 * 8,8 * 16,8 * 8), X
8=(P frame, B frame);
Have
(8 * 8) X
1=(8 * 8 quantize, 8 * 8 inverse quantizations, 8 * 8DCT, 8 * 8IDCT, 8 * 8 reconstruct, 8 * 8 predictions);
X
2 α γ δ=(whole pixel intensity interpolation, sub-pix brightness interpolating, 1/4 pixel intensity interpolation);
βx
6 =(motion search, motion compensation);
Order
y=X
4⊕ X
5=
; X
3⊕ Y=
X
8⊕ X
7⊕ X
2⊕
α βx
6 = 
Here variable
xvalue be concept, claim
xfor the concept variable.Product
xymean the concept variable
xwith
ythe connection of value.Each component value is concept
nn dimensional vector n X is called the concept vector, similar definable concept matrix
aand two concept vector X
=?<
x 1 , x 2 ..., x n and
y=
y 1 , y 2 ..., y m product X ⊕ Y
Wherein
a i =
a i1
,
a i2
...,
a i m , 1≤
i≤
kfor the concept vector; Concept vector X and concept matrix
aproduct X ⊕
afor
Step 3: describe each application scenarios demand of AVS scrambler with application layer language avsLL7, obtain the semantic flow process set avsPRO of AVS scrambler;
Step 4: according to AVS scrambler computational complexity, the parallel scale of application deployment engine avsEngine and atomic operation avsAO, the grammatical feature of generation AVS scrambler;
Step 5: by the semantic flow process set of the AVS scrambler avsPRO flow process queue of packing into, drive and carry out, debug and optimize;
Step 6: placement-and-routing, simulating, verifying, flow, test and production.
According to different application demands, the AVS scrambler is divided into to AVS benchmark demand, AVS and stretches that demand, AVS move demand, AVS strengthens demand and AVS3D demand, describes respectively the semantic flow process of different demands with avsLL7, the internal memory of the asic chip of packing into is standby.
Claims (4)
1. the interior cloud framework of ASIC sheet, is characterized in that: comprise an interior cloud basic framework IF of sheet that meets SOA three-tier architecture model, for concrete application, cloud basic framework IF instantiation in sheet is formed to asic chip, SOA three-tier architecture model comprises demand layer conceptual model, semantic layer logical model and service layer's physical model, the demand layer is asic chip and extraneous interface, extension and the intension of the concrete application of definition, establish whole value that asic chip can provide, produce and describe relevant basic semantic concept and the grammatical feature of application scenarios, semantic layer has defined application layer language LL7 for concrete application, and concrete application scenarios is described as semantic flow process with application layer language LL7, pays application engine AE and processes, application layer language LL7 is comprised of the irrelevant part LL7-PI of problem and contact problem part LL7-PS two parts, the irrelevant part LL7-PI of problem is essential to all applications, the irrelevant part LL7-PI of problem realizes the grammatical feature of application engine AE, and contact problem part LL7-PS relates to the concrete concept of concrete application and is the set that realizes corresponding atomic operation AO, service layer is the set of the atomic operation AO that in the ASIC sheet, cloud provides, comprises flow process control operation and calculation process operation, is packaged into the instruction set that Atomic component AC forms cloud basic framework IF in sheet, in sheet, cloud basic framework IF comprises a write bus BoW and corresponding message passing mechanism in elementary cell IU, sheet, described elementary cell IU comprises a main processing node MPN and several are from processing node SPN
1, SPN
2..., SPN
n, main processing node MPN and several are from processing node SPN
1, SPN
2..., SPN
nunified node interface UNI by separately be connected in sheet, on a write bus BoW, realize interconnected, in described, a write bus BoW comprises two transmission of messages passages and a bar state bus FLAG, main processing node MPN exclusively enjoys a piece of news transmission channel, make the processing node MPN of winner send message frame from processing node SPN to all, several are from processing node SPN
1, SPN
2..., SPN
nshare another transmission of messages passage, make several from processing node SPN
1, SPN
2..., SPN
ncan distinguish independently and send message frame to main processing node MPN, status bus FLAG is with solving several from processing node SPN
1, SPN
2..., SPN
nsend the conflict that message frame causes simultaneously, when certain from processing node SPN
xfirst detected state bus FLAG while sending message frame, the default setting of status bus FLAG is idle condition " 0 ", when detected state bus FLAG is idle condition " 0 ", first status bus FLAG is set to busy condition " 1 ", then send message frame, message frame is set to status bus FLAG idle condition " 0 " after sending and finishing again, when detected state bus FLAG is busy condition " 1 ", according to priority and algorithmic characteristic arrange one time delay △ T, △ T time delay detected state bus FLAG again after finishing, until status bus FLAG is while being idle condition " 0 ", first status bus FLAG is set to busy condition " 1 ", then send message frame, message frame is set to status bus FLAG idle condition " 0 " after sending and finishing again, the application engine AE that described main processing node MPN is elementary cell IU, it adopts general processor CPU, described is Atomic component AC from processing node SPN, Atomic component AC is comprised of Atomic component name AC-NAME and Atomic component entity A C-ENTITY two parts, wherein Atomic component entity A C-ENTITY consists of unified node interface UNI and atomic operation AO two parts, atomic operation AO is independently functional integrated circuit module or one IP kernel independently, for concrete application, completely specified output is arranged under given input, corresponding message passing mechanism comprises unified node interface access protocal UNIAP and unified Atomic component access protocal UACAP, unified node interface access protocal UNIAP belongs to link layer protocol, be responsible for message at main processing node MPN with from error free transmission between processing node SPN, unified Atomic component access protocal UACAP belongs to network layer protocol, be from defining in logic sign or the address of each Atomic component AC node, according to the access mode of Atomic component AC, formulate the message packing rule.
2. cloud framework in ASIC sheet according to claim 1, it is characterized in that: described main processing node MPN selects sequencer SEQ to replace the application engine AE of general processor CPU as elementary cell IU, the parts that sequencer SEQ comprises have flow process queue, flow process counter, member queue, member counter and member code translator, and the flow process queue is used for storing the sign ID of the semantic flow process corresponding with the different application demand; The flow process counter is used to refer to the process identification ID be activated to current; The member queue is used for storing the application flow AP corresponding with sign ID; application flow AP is the instruction sequence of basic framework IF; it is the sequence of Atomic component name AC-NAME; Atomic component name AC-NAME comprises atomic operation name AO-NAME and interface message IM, and specific definition is: AC-NAME=AO-NAME& IM; The member counter is used for determining the execution sequence of application flow AP, and the member counter points to the next Atomic component name AC-NAME that will carry out in the member queue; The message that generates access atomic operation AO resolved current Atomic component name AC-NAME process according to the syntax rule of application layer language LL7 by the member code translator, send in sheet a write bus BoW and activate corresponding Atomic component entity A C-ENTITY and implement concrete operations by unified node interface UNI, the member counter points to the next Atomic component name AC-NAME that will carry out simultaneously.
3. cloud framework in ASIC sheet according to claim 1 and 2, it is characterized in that: describedly can also continue to connect elementary cell IU from processing node SPN, when from processing node SPN, connecting an elementary cell IU, this processing node SPN is as the main processing node MPN of the unit IU that reconnects again.
4. the ASIC method for designing based on cloud framework in ASIC sheet claimed in claim 1, it is characterized in that: by the concept atom of software field member, and be embodied as the instruction set of coarseness with logic semiconductor, the IP kernel that circuit is connected is packaged into the member that message connects, utilize the interconnected Atomic component AC of a write bus BoW in sheet, form cloud basic framework IF in sheet, by definition application layer language, LL7 realizes basic framework IF, support the restructural of semantic flow process, the customizability of ASIC is extended to syntactic element and two dimensions of semantic flow process, for specifically being used for defining application layer language LL7, then the use-case scene that will specifically apply is described as application flow AP with application layer language LL7, be deployed in the application engine AE of elementary cell IU and carry out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310074630.9A CN103136162B (en) | 2013-03-07 | 2013-03-07 | Cloud framework and the method for designing based on this framework in ASIC sheet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310074630.9A CN103136162B (en) | 2013-03-07 | 2013-03-07 | Cloud framework and the method for designing based on this framework in ASIC sheet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103136162A true CN103136162A (en) | 2013-06-05 |
| CN103136162B CN103136162B (en) | 2015-07-29 |
Family
ID=48496004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310074630.9A Active CN103136162B (en) | 2013-03-07 | 2013-03-07 | Cloud framework and the method for designing based on this framework in ASIC sheet |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103136162B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104123249A (en) * | 2014-07-22 | 2014-10-29 | 山西达鑫核科技有限公司 | Novel dynamic memory SDDR architecture array based on serial access |
| CN108027806A (en) * | 2015-09-22 | 2018-05-11 | 高通股份有限公司 | Configuration coarseness configurable arrays (CGRA) perform for data flow instruction block in block-based data flow instruction collection framework (ISA) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101710311A (en) * | 2009-12-30 | 2010-05-19 | 太原理工大学 | Asymmetric multivariate resource node architecture |
| US20110035718A1 (en) * | 2009-04-06 | 2011-02-10 | Vhdl, Inc | Integrated circuit design system and method |
-
2013
- 2013-03-07 CN CN201310074630.9A patent/CN103136162B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110035718A1 (en) * | 2009-04-06 | 2011-02-10 | Vhdl, Inc | Integrated circuit design system and method |
| CN101710311A (en) * | 2009-12-30 | 2010-05-19 | 太原理工大学 | Asymmetric multivariate resource node architecture |
Non-Patent Citations (1)
| Title |
|---|
| 常青等: "SOA三层架构在嵌入式文件系统上的实现", 《太原理工大学学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104123249A (en) * | 2014-07-22 | 2014-10-29 | 山西达鑫核科技有限公司 | Novel dynamic memory SDDR architecture array based on serial access |
| CN104123249B (en) * | 2014-07-22 | 2018-03-09 | 山西达鑫核科技有限公司 | A kind of new dynamic memory SDDR architecture arrays of serial access |
| CN108027806A (en) * | 2015-09-22 | 2018-05-11 | 高通股份有限公司 | Configuration coarseness configurable arrays (CGRA) perform for data flow instruction block in block-based data flow instruction collection framework (ISA) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103136162B (en) | 2015-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| So et al. | A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH | |
| Wolf et al. | Multiprocessor system-on-chip (MPSoC) technology | |
| CN107392308B (en) | Convolutional neural network acceleration method and system based on programmable device | |
| Beretta et al. | A mapping flow for dynamically reconfigurable multi-core system-on-chip design | |
| Maqsood et al. | Dynamic task mapping for network-on-chip based systems | |
| Catthoor et al. | Application-specific architectural methodologies for high-throughput digital signal and image processing | |
| Lee et al. | A systematic design space exploration of MPSoC based on synchronous data flow specification | |
| US11782725B2 (en) | Mask field propagation among memory-compute tiles in a reconfigurable architecture | |
| CN101727423B (en) | System capable of preempting multiple hardware tasks on reconfigurable FPGA and implementing method thereof | |
| Wildermann et al. | Symbolic design space exploration for multi-mode reconfigurable systems | |
| Bezati et al. | An heterogeneous compiler of dataflow programs for zynq platforms | |
| CN103136162B (en) | Cloud framework and the method for designing based on this framework in ASIC sheet | |
| US11789790B2 (en) | Mechanism to trigger early termination of cooperating processes | |
| JP2003534596A (en) | Programmable single-chip device and related development environment | |
| Yang et al. | An Asynchronous Adaptive Priority Round‐Robin Arbiter Based on Four‐Phase Dual‐rail Protocol | |
| Sahlbach et al. | A system-level FPGA design methodology for video applications with weakly-programmable hardware components | |
| Wildermann et al. | Symbolic system-level design methodology for multi-mode reconfigurable systems | |
| Yang et al. | Effective Task Scheduling and IP Mapping Algorithm for Heterogeneous NoC-Based MPSoC. | |
| Stripf et al. | A compilation-and simulation-oriented architecture description language for multicore systems | |
| CN107665281B (en) | FPGA-based processor simulation method | |
| Zhai | Adaptive streaming applications: analysis and implementation models | |
| Caspi | Design automation for streaming systems | |
| Bayar et al. | A dynamically reconfigurable communication architecture for multicore embedded systems | |
| Göhringer | Reconfigurable multiprocessor systems: Handling hydras heads--a survey | |
| US11829733B2 (en) | Synthesis flow for data processing engine array applications relying on hardware library packages |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |