CN103136128A - Circuit and method of local serial rapid input and output (SRIO) node Device identity (ID) configuration of processor - Google Patents
Circuit and method of local serial rapid input and output (SRIO) node Device identity (ID) configuration of processor Download PDFInfo
- Publication number
- CN103136128A CN103136128A CN2011103878688A CN201110387868A CN103136128A CN 103136128 A CN103136128 A CN 103136128A CN 2011103878688 A CN2011103878688 A CN 2011103878688A CN 201110387868 A CN201110387868 A CN 201110387868A CN 103136128 A CN103136128 A CN 103136128A
- Authority
- CN
- China
- Prior art keywords
- processor
- local
- deviceid
- configuration
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The invention relates to a circuit and a method of local serial rapid input and output (SRIO) node Device identity (ID) configuration of a processor. The circuit of local SRIO node Device ID configuration of the processor comprises the processor, a processor bus which is matched with the processor, a serial Rapid input and output (IO) core and a client-side interface, wherein the processor is connected with the client-side interface through the processor bus, and the serial Rapid IO core is connected with the client-side interface. The circuit and the method of local SRIO node Device ID configuration of the processor are simple in process, safe and reliable.
Description
Technical field
The invention belongs to the computer control field, relate to a kind of processor to configuring circuit and the method for local SRIO node DeviceID.
Background technology
Present various processor can not to local SRIO node DeviceID be configured or layoutprocedure loaded down with trivial details, use very inconvenient.
Summary of the invention
In order to solve the above-mentioned technical matters that exists in background technology, the invention provides circuit and the method for the simple and safe and reliable local SRIO node DeviceID of processor configuration of a kind of layoutprocedure.
Technical solution of the present invention is: the invention provides the circuit of the local SRIO node DeviceID of a kind of processor configuration, its special character is: processor bus, serial RapidIO core and client-side interface that the circuit of the local SRIO node DeviceID of described processor configuration comprises processor, is complementary with processor; Described processor accesses client-side interface by processor bus; Described serial RapidIO core is connected with client-side interface.
Above-mentioned serial RapidIO core is the circuit module of realizing serial RapidIO Physical layer, transport layer and logical layer protocol; Described serial RapidIO core comprises Initiator port, Target port and Maintenance interface; Described Initiator port, Target port and Maintenance interface are connected with client-side interface respectively; Described Initiator port is that the ireq_local signal need to be provided, and expression is initiated is operating as the local maintenance bag, and is sent to maintenance port.
The processing module of the action type that above-mentioned client-side interface is used for realizing that the relative clients end needs, and interface with processor bus is provided; Described client-side interface comprises that configuring local DeviceID enable register, local DeviceID register and configuration completes flag register.
Above-mentioned local DeviceID register has 16 bit widths at least; The local DeviceID enable register of described configuration has 1 bit width at least, and described configuration is completed flag register and had 17 bit widths at least.
Above-mentioned processor is the processor of ARM series, the processor of PowerPC series or the processor of Intel series.
When above-mentioned processor was the processor of ARM series, described processor bus was the AMBA bus; When processor was the processor of PowerPC series, described processor bus was the CoreConnect bus.
The collocation method of the local SRIO node DeviceID of a kind of processor configuration, its special character is: said method comprising the steps of:
1) processor is write the local DeviceID register of client-side interface by processor bus, and the DeviceID of needs configuration is write in register;
2) processor by processor bus, is write the local DeviceID enable register of configuration, enable operation;
3) value of the local DeviceID enable register of client-side interface electric circuit inspection configuration, when this value was 1, expression can need to start the client-side interface state machine and initiatively initiate a maintenance package operation; When this value is non-1, do not carry out any processing;
4) safeguard that by what send the local maintenance bag write operation is to the configuration of local configuration space.
Above-mentioned steps 4) specific implementation is:
4.1) when client-side interface is initiated the maintenance package operation, start one of Initiator port initiation and safeguard write request and the ireq_local signal is set high;
4.2) step 4.1) and in the request that sends deliver to the register management module by maintenance request MREQ interface;
4.3) the corresponding address space of register management module accesses, write operation is divided into the operation of 32bit by the register management module;
4.4) after write operation completed, the register management module responded the MRESP interface by maintenance request and returns to the signal that state is write in indication; The signal that state is write in described indication becomes the user side interface to return by originating end request response IRESP interface conversion to safeguard the write response signal;
4.5) after client-side interface receives and complete response, put configuration to complete flag register be effective value and the DeviceID value of correspondence is write in this register.
Advantage of the present invention is: can configure local SRIO node DeviceID by processor, a kind of system configuration mode easily is provided.
Description of drawings
Fig. 1 is the frame diagram of circuit provided by the present invention;
Fig. 2 is the structural representation of SRIO core of the present invention;
Fig. 3 is the layoutprocedure schematic diagram that the present invention takes.
Embodiment
Referring to Fig. 1, the invention provides the circuit of the local SRIO node DeviceID of a kind of processor configuration, this circuit is minimum comprises following several circuit module:
1) processor.This processor can be the processor of ARM series, can be also the processor of PowerPC series, can be also the processor of Intel series, can be also other serial processors.
2) processor bus.Processor bus need to the type matching of processor.For example, if adopt arm processor, processor bus is the AMBA bus structure; If adopt the PowerPC processor, processor bus is the CoreConnect bus.
3) serial RapidIO (SRIO) core.Referring to Fig. 2, this IP kernel is the circuit module of realizing serial RapidIO Physical layer, transport layer and logical layer protocol.Initiator, Target and Maintenance interface are provided, interconnected with client-side interface is provided.The Initiator port need to provide the ireq_local signal, and expression is initiated is operating as the local maintenance bag, and is sent to maintenance port.
4) client-side interface.This interface is the processing module of the action type that realizes that the relative clients end needs, and the interface with processor bus is provided.In this interface, there are the local DeviceID enable register of configuration, local DeviceID register, configuration to complete three registers such as flag register.Local DeviceID register must have 16 bit widths at least, configures local DeviceID enable register and has 1 bit width at least, and configuration is completed flag register and had 17 bit widths at least.
Referring to Fig. 3, when the present invention was configured at the circuit that adopts the local SRIO node DeviceID of processor configuration, its layoutprocedure comprised following several step:
1) processor is write the local DeviceID register of client-side interface by processor bus, and the DeviceID of needs configuration is write in register;
2) processor by processor bus, is write the local DeviceID enable register of configuration, enable operation;
3) the client-side interface state machine detects the value of the local DeviceID enable register of configuration, and when this value was 1, expression can need to start the client-side interface state machine and initiatively initiate a maintenance package operation;
4) to the configuration of local configuration space, be to safeguard what write operation was realized by what send the local maintenance bag;
The flow process of the attended operation of 5) initiating is as shown below.When client-side interface is initiated the maintenance package operation, start one of Initiator port initiation and safeguard write request and the ireq_local signal is set high (the maintenance package operation of this signal indication initiation is the local maintenance operation).This request meeting is delivered to the register management module by the MREQ interface.Subsequently, the corresponding address space of register management module accesses.Write operation can be divided into by the register management module operation of 32bit.After write operation was completed, the register management module can be returned to the signal that state is write in indication by the MRESP interface.This response signal can become the user side interface to return by the IRESP interface conversion to safeguard the write response signal;
6) after client-side interface received and completes response, putting configuration, to complete flag register be effective value (and the DeviceID value of correspondence is write in this register), represents that whole layoutprocedure completes.
Claims (8)
1. the circuit of the local SRIO node DeviceID of processor configuration is characterized in that: processor bus, serial RapidIO core and client-side interface that the circuit of the local SRIO node DeviceID of described processor configuration comprises processor, is complementary with processor; Described processor accesses client-side interface by processor bus; Described serial RapidIO core is connected with client-side interface.
2. processor according to claim 1 configures the circuit of local SRIO node DeviceID, and it is characterized in that: described serial RapidIO core is the circuit module of realizing serial RapidIO Physical layer, transport layer and logical layer protocol; Described serial RapidIO core comprises Initiator port, Target port and Maintenance interface; Described Initiator port, Target port and Maintenance interface are connected with client-side interface respectively; Described Initiator port is that the ireq_local signal need to be provided, and expression is initiated is operating as the local maintenance bag, and is sent to maintenance port.
3. the circuit of the local SRIO node DeviceID of processor according to claim 2 configuration is characterized in that: described client-side interface is used for realizing the processing module of the action type of relative clients end needs, and the interface with processor bus is provided; Described client-side interface comprises that configuring local DeviceID enable register, local DeviceID register and configuration completes flag register.
4. processor according to claim 3 configures the circuit of local SRIO node DeviceID, and it is characterized in that: described local DeviceID register has 16 bit widths at least; The local DeviceID enable register of described configuration has 1 bit width at least, and described configuration is completed flag register and had 17 bit widths at least.
5. according to claim 1-4 described processors of arbitrary claim configure the circuit of local SRIO node DeviceID, and it is characterized in that: described processor is the processor of ARM series, the processor of PowerPC series or the processor of Intel series.
6. processor according to claim 5 configures the circuit of local SRIO node DeviceID, and it is characterized in that: when described processor was the processor of ARM series, described processor bus was the AMBA bus; When processor was the processor of PowerPC series, described processor bus was the CoreConnect bus.
7. Circnit Layout method based on the local SRIO node DeviceID of the described processor of the arbitrary claim of claim 1-6 configuration is characterized in that: said method comprising the steps of:
1) processor is write the local DeviceID register of client-side interface by processor bus, and the DeviceID of needs configuration is write in register;
2) processor by processor bus, is write the local DeviceID enable register of configuration, enable operation;
3) value of the local DeviceID enable register of client-side interface electric circuit inspection configuration, when this value was 1, expression can need to start the client-side interface state machine and initiatively initiate a maintenance package operation; When this value is non-1, do not carry out any processing;
4) safeguard that by what send the local maintenance bag write operation is to the configuration of local configuration space.
8. processor according to claim 7 configures the method for local SRIO node DeviceID, and it is characterized in that: specific implementation described step 4) is:
4.1) when client-side interface is initiated the maintenance package operation, start one of Initiator port initiation and safeguard write request and the ireq_local signal is set high;
4.2) step 4.1) and in the request that sends deliver to the register management module by maintenance request MREQ interface;
4.3) the corresponding address space of register management module accesses, write operation is divided into the operation of 32bit by the register management module;
4.4) after write operation completed, the register management module responded the MRESP interface by maintenance request and returns to the signal that state is write in indication; The signal that state is write in described indication becomes the user side interface to return by originating end request response IRESP interface conversion to safeguard the write response signal;
4.5) after client-side interface receives and complete response, put configuration to complete flag register be effective value and the DeviceID value of correspondence is write in this register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110387868.8A CN103136128B (en) | 2011-11-29 | 2011-11-29 | Processor configures circuit and the method for local SRIO node DeviceID |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110387868.8A CN103136128B (en) | 2011-11-29 | 2011-11-29 | Processor configures circuit and the method for local SRIO node DeviceID |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103136128A true CN103136128A (en) | 2013-06-05 |
| CN103136128B CN103136128B (en) | 2015-08-19 |
Family
ID=48495975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110387868.8A Active CN103136128B (en) | 2011-11-29 | 2011-11-29 | Processor configures circuit and the method for local SRIO node DeviceID |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103136128B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105530247A (en) * | 2015-12-08 | 2016-04-27 | 天津津航计算技术研究所 | Circuit and method of SRIO node for automatically matching different DeviceID widths based on FPGA |
| CN108156099A (en) * | 2017-11-15 | 2018-06-12 | 中国电子科技集团公司第三十二研究所 | Srio switching system |
-
2011
- 2011-11-29 CN CN201110387868.8A patent/CN103136128B/en active Active
Non-Patent Citations (3)
| Title |
|---|
| SKYLAR: "《http://blog.csdn.net/zzsfqiuyigui/article/details/6859997》", 10 October 2011 * |
| 张娟 等: "给予多处理器的高速RapidIO", 《计算机工程》 * |
| 黄克武 等: "基于TMS320C455的高速SRIO接口设计", 《电子测量技术》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105530247A (en) * | 2015-12-08 | 2016-04-27 | 天津津航计算技术研究所 | Circuit and method of SRIO node for automatically matching different DeviceID widths based on FPGA |
| CN105530247B (en) * | 2015-12-08 | 2019-01-08 | 天津津航计算技术研究所 | The circuit and method of the different DeviceID width of SRIO node Auto-matching based on FPGA |
| CN108156099A (en) * | 2017-11-15 | 2018-06-12 | 中国电子科技集团公司第三十二研究所 | Srio switching system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103136128B (en) | 2015-08-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9781055B2 (en) | Dynamic cascaded clustering for dynamic VNF | |
| CN107278299B (en) | Method, apparatus and system for implementing secondary bus functionality via a reconfigurable virtual switch | |
| US11372787B2 (en) | Unified address space for multiple links | |
| CN103180817B (en) | Memory expansion unit and server | |
| US20190042518A1 (en) | Platform interface layer and protocol for accelerators | |
| US9767067B2 (en) | Baseboard management systems and methods with distributed intelligence for multi-node platforms | |
| WO2018194845A1 (en) | Queue management for direct memory access | |
| TWI458314B (en) | Server system and management method thereof for transferring remote packet to host | |
| US20160350240A1 (en) | Serial peripheral interface host port | |
| US9898435B2 (en) | Aggregate baseboard management controller (BMC) controller | |
| US10614011B2 (en) | Apparatus, method, and electronic device for implementing solid-state drive data interaction | |
| CN111177065A (en) | Multi-chip interconnection method and device | |
| WO2017101080A1 (en) | Write request processing method, processor and computer | |
| WO2015106623A1 (en) | Method and apparatus for configuring and delivering flow table entry | |
| CN104881105A (en) | Electronic device | |
| CN103927233A (en) | Multi-node memory interconnection device and large-scale computer cluster | |
| CN103338125A (en) | Method for batch network device configuration | |
| CN103838588A (en) | Method for conducting online program updating on AT90 single-chip microcomputer through CAN interface | |
| CN105763488B (en) | Data center aggregation core switch and backboard thereof | |
| CN105607940A (en) | Method for transmitting information from BDK to UEFI BIOS in ARM platform | |
| CN103136128B (en) | Processor configures circuit and the method for local SRIO node DeviceID | |
| WO2012103768A1 (en) | Method and apparatus for data processing, pci-e bus system and server | |
| CN103678220A (en) | Design method for extending LBE bus from PCI bus | |
| CN102736908B (en) | System, the device and method of remotely located CMOS parameters | |
| WO2020107460A1 (en) | Computing method, chip, and system, readable storage medium, and computer program product |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221110 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 710068 No. 156 Taibai North Road, Shaanxi, Xi'an Patentee before: 631ST Research Institute OF AVIC |