CN103117671A - Inverter - Google Patents
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- CN103117671A CN103117671A CN2013100478127A CN201310047812A CN103117671A CN 103117671 A CN103117671 A CN 103117671A CN 2013100478127 A CN2013100478127 A CN 2013100478127A CN 201310047812 A CN201310047812 A CN 201310047812A CN 103117671 A CN103117671 A CN 103117671A
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Abstract
The invention relates to an inverter. The inverter can solve the problem of weak adjustability of output current of the inverter and is characterized by being power supplied by a power supply input circuit and comprising an interface circuit, a main control circuit, a feedback circuit, a former stage inverter circuit, a transformer circuit and an inverter output circuit. The main control circuit is in electric connection with a control end of the inverter output circuit through the interface circuit, and the main control circuit is further connected with a former stage inverter circuit control end. The power input circuit is in electric connection with the inverter output circuit through the former stage inverter circuit, the interface circuit and the voltage circuit respectively, and the main control circuit is further in electric connection with the interface circuit through the feedback circuit. The inverter is simple in structure, strong in transportability, full in expansion space and expansion capability, good in output waveform and large in adjustable range; has good circuit protection and isolation; and can automatically switch and is face and reliable.
Description
Technical field
The present invention is a kind of power supply change-over device, particularly relates to a kind of inverter.
Background technology
Inverter is that direct current energy such as battery, accumulator jar etc. are transformed into alternating current, is generally 220v50HZ sine or square wave.Popular says, inverter is a kind of device that direct current (DC) is converted into alternating current (AC).It is comprised of inverter bridge, control logic and filter circuit.Be widely used in air-conditioning, home theater, electric wheel, electric tool, sewing machine, DVD, VCD, computer, TV, washing machine, smoke exhaust ventilator, refrigerator, video tape recorder, massager, fan, illumination etc.
China Patent Publication No.: CN1149785A, open day on May 14th, 1997, a kind of inverter is disclosed, comprise input rectifier, input filter, output rectifier and output filter, be connected to the convertor circuit that is formed by electronic switch and two elementary intermediate frequency transformer between described input filter and output rectifier; Described convertor circuit comprise 4 electronic switch S1～S4,8 diode D1～D8,2 absorb network R1C1, R2C2 and by 2 armature winding N1, N2 and N the intermediate frequency transformer B that secondary winding consists of; The positive pole of the upper termination power of described switch S 1, the lower end of S1 connect respectively negative electrode, the D5 of diode D1 anode, transformer B armature winding N1 the upper end and absorb the left end of R1 in network R1C1, the negative electrode of diode D5 and D2 connects respectively the positive pole of power supply, the anode of diode D2 connect respectively negative electrode, the transformer B armature winding N1 of upper end, the diode D6 of switch S 2 the lower end, absorb the right-hand member of C1 in network R1C1, the lower end of the anode of diode D1, switch S 2, the anode of diode D6 connect respectively the negative pole of power supply; The positive pole of the upper termination power of described switch S 3, the lower end of S3 connect respectively anode, the transformer B armature winding N2 of negative electrode, the D7 of diode D3 the lower end, absorb the left end of R2 in network R2C2, the negative electrode of diode D7 and D4 connects respectively the positive pole of power supply, the anode of diode D4 connect respectively negative electrode, the transformer B armature winding N2 of upper end, the diode D8 of switch S 4 the upper end, absorb the right-hand member of C2 in network R2C2, the lower end of the anode of diode D3, switch S 4, the anode of diode D8 connect respectively the negative pole of power supply.Although this technical scheme can be carried out inversion output, the electric current controllability of its output is not strong.
Summary of the invention
The objective of the invention is to exist for solving present technical scheme the not strong problem of electric current controllability of its output, a kind of good output waveform that has is provided, adjustable extent is large, and circuit protection, isolation are preferably arranged, and can independently switch, safe and reliable inverter.
the technical solution adopted for the present invention to solve the technical problems is: a kind of inverter, powered by power supply input circuit, comprise interface circuit, governor circuit, feedback circuit, the preceding-stage inversion circuit, transformer circuit and inverter output circuit, described governor circuit is electrically connected to described inverter output circuit control end by interface circuit, described governor circuit also is connected with described preceding-stage inversion circuit control end, described power supply input circuit is successively by the preceding-stage inversion circuit, interface circuit and transformer circuit are electrically connected to described inverter output circuit, described governor circuit also is electrically connected to described interface circuit by described feedback circuit.The present invention is simple in structure, and is portable strong, and sufficient extending space and extended capability are arranged, and has good output waveform, and adjustable extent is large, and circuit protection, isolation are preferably arranged, and can independently switch, safe and reliable.
As preferably, described power supply input circuit comprises input power, pressurizer, capacitor C 13 and capacitor C 1, the input of described pressurizer is connected with input power, capacitor C 13 and capacitor C 1 ground connection that the output single-pass of described pressurizer is excessively in parallel, described output end of voltage stabilizer output electric current of voltage regulation.This circuit also has filter function except general power supply.
as preferably, described governor circuit comprises process chip, loudspeaker MIC, resistance R 81, resistance R 82, resistance R 83, resistance R 84, resistance R 85, resistance R 86, resistance R 87, resistance R 89, resistance R 88, resistance R 91, resistance R 90, resistance R 101, resistance R 103, triode Q16, triode Q15, triode Q14, electric capacity E11, capacitor C 29 and capacitor C 28, described process chip is the SN8P2711 process chip, the process chip vdd terminal connects power supply input circuit, process chip AIN1 mouth ground connection, process chip P0.3 mouth is connected with protective circuit by resistance R 88, process chip P0.3 mouth also is connected with the base stage of triode Q15 by resistance R 88, the collector electrode of triode Q15 is connected with interface circuit, the collector electrode of triode Q15 also is connected with input power by resistance R 90, the grounded emitter of triode Q15, process chip P0.2 mouth is connected with protective circuit by resistance R 89, process chip P0.2 mouth also is connected with the base stage of triode Q16 by resistance R 89, the collector electrode of triode Q16 is connected with interface circuit, the collector electrode of triode Q16 also is connected with input power by resistance R 91, the grounded emitter of triode Q16, the P0.1 mouth of process chip is connected with interface circuit, and the P0.1 mouth of process chip also is connected with power supply input circuit by resistance R 101, the AIN4 mouth of process chip is connected with resistance R and is connected with interface circuit by resistance R 103, and the AIN4 mouth of process chip passes through resistance R 103, resistance R 82 and resistance R 83 ground connection successively, and the AIN4 mouth of process chip also passes through capacitor C 29 ground connection, process chip AIN3 mouth is by capacitor C 28 ground connection, and process chip AIN3 mouth is connected with power supply input circuit by resistance R 84, process chip AIN2 mouth is connected with interface circuit by resistance R 85, process chip AIN1 mouth is connected with interface circuit, process chip AIN1 mouth is also by electric capacity E11 ground connection, process chip AIN1 mouth is connected with the first end of resistance R 86, the second end of resistance R 86 is connected with the emitter of triode Q14, the collector electrode of triode Q14 is connected with power supply input circuit by loudspeaker MIC, and the base stage of triode Q14 is connected with the P0.0 mouth by resistance R 87, process chip P5.3 mouth is connected with process chip P5.4 mouth and is controlled output circuit and be connected, and process chip P4.0 mouth is connected with interface circuit.The present invention arranges simple in structure like this, and is portable strong, and sufficient extending space and extended capability are arranged, and has good output waveform, and adjustable extent is large, and circuit protection, isolation are preferably arranged, and can independently switch, safe and reliable.
as preferably, described feedback circuit comprises resistance R 92, resistance R 93, resistance R 94, resistance R 95, resistance R 96, resistance R 97, resistance R 98, resistance R 99, resistance R 100, resistance 102, triode Q17, triode Q18, the first amplifier, the second amplifier, electric capacity E12, capacitor C 2, capacitor C 4, capacitor C 5, capacitor C 6, diode D27, diode D28 and rheostat VR1, the positive input terminal of described the first amplifier is connected with interface circuit by resistance R 98, the positive input terminal of the first amplifier is also by electric capacity E12 ground connection, the negative input end of the first amplifier is connected with power supply input circuit by resistance R 99, the negative input end of the first amplifier is also respectively by rheostat VR1 and capacitor C 6 ground connection, the output of the first amplifier is connected with power supply input circuit by resistance R 100, the output of the first amplifier also is connected with the positive input terminal of the second amplifier by diode D27, the negative input end of the second amplifier is respectively by resistance R 96 and capacitor C 2 ground connection, the negative input end of the second amplifier is connected with power supply input circuit by resistance R 95, the positive input terminal of the second amplifier respectively with the first end of resistance R 97, the first end that the first end of resistance R 102 is connected with capacitor C connects, the second end of resistance R 97 is connected with interface circuit, the second end that the second end of resistance R 102 is connected with capacitor C all is connected with power supply input circuit by resistance R 94, the second end that the second end of resistance R 102 is connected with capacitor C also is connected with the first end of resistance R 92 and the output of the second amplifier, the second end of resistance R 92 is connected with the base stage of triode Q17, the grounded emitter of triode Q17, the collector electrode of triode Q17 is connected with main control chip P0.2 by resistance R 89, the output of the second amplifier also is connected with process chip AIN4 mouth by diode D28, the output of the second amplifier is connected with the base stage of triode Q18 by resistance R 93, the collector electrode of triode Q18 is connected with process chip P0.3 mouth by resistance R 88, the grounded emitter of triode Q18.The setting of feedback circuit is conveniently carried out from main regulation and parameter acquisition.
as preferably, described preceding-stage inversion circuit comprises resistance R 105, resistance R 16, resistance R 76, resistance R 77, resistance R 78, resistance R 79, resistance R 80, capacitor C 3, the 3rd amplifier, four high guaily unit, triode Q8, triode Q11, triode Q12 and triode Q13, the positive input terminal of the 3rd amplifier is connected with process chip P5.3 mouth by resistance R 78, the positive input terminal of the 3rd amplifier is also by resistance R 104 ground connection, the negative input end of the 3rd amplifier is respectively by resistance R 76 and C3 ground connection, the negative input end of the 3rd amplifier is connected with power supply input circuit by resistance R 16, the negative input end of the 3rd amplifier also is connected with the negative input end of four high guaily unit, the output of the 3rd amplifier is connected with input power by resistance R 79, the output of the 3rd amplifier also is connected with the base stage of triode Q8 and triode Q12, the collector electrode of triode Q8 is connected with input power, the output of triode Q8 is connected with interface circuit, the emitter of triode Q12 is connected with the emitter of triode Q8, the grounded collector of triode Q12, the 4th positive input terminal is connected with process chip P5.4 mouth by resistance R 77, the positive input terminal of four high guaily unit is also by resistance R 105 ground connection, the output of four high guaily unit is connected with input power by resistance R 80, the output of four high guaily unit also is connected with the base stage of triode Q11 and triode Q13, the collector electrode of triode Q11 is connected with input power, the emitter of triode Q11 is connected with interface circuit, the emitter of triode Q13 is connected with the emitter of triode Q11, the grounded collector of triode Q13.
as preferably, described interface circuit comprises interface JP1 and electric capacity E15, and the port of interface JP1 comprises the P1 mouth, the P2 mouth, the DC mouth, the GND mouth, the power supply input port, the RT mouth, the FEN mouth, the AC_AD mouth, the H-DC mouth, the SWICH mouth, the LED mouth, the H1 mouth, the H2 mouth, SHORT mouth and LOAN mouth, the P1 mouth of interface JP1 is connected with the emitter of triode Q8, the P2 mouth of interface JP1 is connected with the emitter of triode Q11, the DC mouth of interface JP1 is connected with resistance R and is connected with process chip AIN1 mouth by resistance R 8 successively, the GND mouth ground connection of interface JP1, the power supply input port of interface JP1 is by electric capacity E15 ground connection, the power supply input port of interface JP1 also is connected with input power, the RT mouth of interface JP1 is connected with process chip AIN3 mouth, the FEN mouth of interface JP1 is connected with process chip AIN2 mouth by resistance R 85, the AC_AD mouth of interface JP1 is connected with process chip AIN1, the H-DC mouth of interface JP1 is connected with process chip P4.0 mouth, the SWICH mouth of interface JP1 is connected with process chip P0.4 mouth, the LED mouth of interface JP1 is connected with process chip P0.1 mouth, the H1 mouth of interface JP1 is connected with the collector electrode of triode Q15, the H2 mouth of interface JP1 is connected with the collector electrode of triode Q16, the SHORT mouth of interface JP1 is connected with the positive input terminal of the second amplifier by resistance R 97, and the LOAN mouth of interface JP1 is connected with the positive input terminal of the first amplifier by resistance R 98.Interface of the present invention is reserved more, can add as one sees fit various indications and feedback, sample circuit, and Function Extension is abundant
as preferably, described transformer circuit comprises field effect transistor VT1, field effect transistor VT2, field effect transistor VT3, field effect transistor VT6, field effect transistor VT7, field effect transistor VT8, transformer T1, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 14, triode Q103, triode Q104, triode Q105, triode Q106, resistance R 6, resistance R 7, resistance R 8, resistance R 17, resistance R 18, resistance R 19, transformer T1 and rectifier bridge, the collector electrode of triode Q103 connects input power, the base stage of triode Q103 is connected base stage and is connected with the P1 mouth with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT1 by resistance R 6 with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT2 by resistance R 7 with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT3 by resistance R 8 with triode Q105, the grounded collector of triode Q105, the drain electrode of field effect transistor VT1, the drain electrode of field effect transistor VT2 is connected drain electrode and all is connected with the first input end of transformer T1 with field effect transistor VT3, the drain electrode of field effect transistor VT1, the drain electrode of the drain electrode of field effect transistor VT2 and field effect transistor VT3 all connects by capacitor C 10 and resistance R 11 successively and exchanges ground, the source electrode of field effect transistor VT1, the source electrode of the source electrode of field effect transistor VT2 and field effect transistor VT3 also all connects and exchanges ground, the collector electrode of triode Q104 connects input power, the base stage of triode Q104 is connected base stage and is connected with the P2 mouth with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT16 by resistance R 17 with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT17 by resistance R 18 with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT18 by resistance R 19 with triode Q106, the grounded collector of triode Q106, the drain electrode of field effect transistor VT6, the drain electrode of field effect transistor VT7 is connected drain electrode and all is connected with the first input end of transformer T1 with field effect transistor VT8, the drain electrode of field effect transistor VT6, the drain electrode of the drain electrode of field effect transistor VT7 and field effect transistor VT8 all connects by capacitor C 14 and resistance R 12 successively and exchanges ground, the source electrode of field effect transistor VT6, the source electrode of the source electrode of field effect transistor VT7 and field effect transistor VT8 also all connects and exchanges ground, first level coil output of transformer T1 is connected with the input of rectifier bridge, and the output of rectifier bridge is respectively by capacitor C 11 and capacitor C 12 ground connection.
as preferably, described inverter output circuit comprises voltage stabilizing didoe D11, triode Q101, triode Q102, diode D3, diode D4, diode D5, diode D6, diode D7, diode D8, capacitor C 13, capacitor C 15, capacitor C 17, capacitor C 19, capacitor C 20, field effect transistor VT4, field effect transistor VT5, field effect transistor VT9, field effect transistor VT10, resistance R 9, resistance R 10, resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 21, resistance R 22, resistance R 23, resistance R 24, resistance R 25, resistance R 28, resistance R 29, resistance R 33, resistance R 34, resistance R 40, resistance R 41, resistance R 36, resistance R 37, resistance R 42, resistance R 43 and rheostat VT11, the drain electrode of the drain electrode of field effect transistor VT4 and field effect transistor V5 all is connected with the output of rectifier bridge, the grid of field effect transistor VT4 is connected with the second end of resistance R 9, the first end of resistance R 9 is connected with the collector electrode of triode Q101, the base stage of triode Q101 is by resistance R 36 ground connection, the base stage of triode Q101 also is connected with the H1 mouth by resistance R 37, the grounded emitter of triode Q101, the grid of field effect transistor VT4 also is connected with the negative electrode of diode D3, the anode of diode D3 is connected with the source electrode of field effect transistor VT4, the first end of resistance R 14 is connected with the first end of resistance R 9, the second end of resistance R 14 is connected with the first end of resistance R 15, the second end of resistance R 15 is connected with the source electrode of field effect transistor VT4, the first end of resistance R 15 also is connected with the negative electrode of diode D6, the anode of diode D6 is connected with input power, the negative electrode of diode D6 is connected with the drain electrode of field effect transistor VT10 by capacitor C 15 successively, the source electrode of the source electrode of field effect transistor VT10 and field effect transistor VT9 is respectively by resistance R 24, resistance R 25, resistance R 28 and resistance R 29 ground connection, the source electrode of field effect transistor VT10 is connected source electrode and also is connected with the SHORT mouth by resistance R 23 with field effect transistor VT9, the grid of field effect transistor VT10 is connected with process chip P5.3 mouth by diode D7, and the two ends of diode D7 are parallel with resistance R 21, the grid of field effect transistor VT5 is connected with the second end of resistance R 10, the first end of resistance R 10 is connected with the collector electrode of triode Q102, the base stage of triode Q102 is by resistance R 43 ground connection, the base stage of triode Q102 also is connected with the H2 mouth by resistance R 43, the grounded emitter of triode Q102, the grid of field effect transistor VT5 also is connected with the negative electrode of diode D4, the anode of diode D4 is connected with the source electrode of field effect transistor VT9, the first end of resistance R 13 is connected with the first end of resistance R 10, the second end of resistance R 13 is connected with the first end of resistance R 16, the second end of resistance R 16 is connected with the source electrode of field effect transistor VT9, the first end of resistance R 16 also is connected with the negative electrode of diode D5, the anode of diode D5 is connected with input power, the negative electrode of diode D5 is connected with the drain electrode of field effect transistor VT9 by capacitor C 13 successively, the grid of field effect transistor VT9 is connected with process chip P5.4 mouth by diode D8, the two ends of diode D8 are parallel with resistance R 20, be in series with capacitor C 19 between the anode of the anode of diode D3 and diode D4, the first end of resistance R 34 is connected with the negative electrode of voltage stabilizing didoe D11, the anode of voltage stabilizing didoe D11 is respectively by capacitor C 17 and resistance R 33 ground connection, the first end of resistance R 34 also is connected with the AC_AD mouth, the second end of resistance R 34 and the anodic bonding of diode D3, the first end of resistance R 41 is connected with the second end of rheostat VT11, the first end of rheostat VT11 is by capacitor C 20 ground connection, the second end of rheostat VT11 is by resistance R 40 ground connection, the first end of resistance R 41 also is connected with the negative electrode of voltage stabilizing didoe D11, the second end of resistance R 41 and the anodic bonding of diode D4, the anode of described diode D3 is inverter the first output, the anode of described diode D4 is inverter the second output.Arrange like this, inverter has automatic adjustable effect.
As preferably, described inverter also comprises failure indicating circuit, described failure indicating circuit comprises overload sample circuit, frequency switching circuit, battery management circuit, busbar voltage loop circuit, faulty indication circuit for lamp, input power indicator light circuit and reset circuit, described overload sample circuit is connected with the LOAN mouth, frequency switching circuit is connected with the SWICH mouth, battery management circuit is connected with the DC mouth, the faulty indication circuit for lamp is connected with the LED mouth, the input power indicator light circuit is connected with input power, and reset circuit is connected with the RT mouth.
As preferably, described inverter also comprises the blower fan circuit, and the second subprime coil output of transformer T1 is connected with the inlet circuit of blower fan circuit, and the control end of blower fan circuit is connected with the FEN mouth.The effect of auxiliary temperature-reducing is played in the setting of blower fan circuit.
Substantial effect of the present invention is: the present invention is simple in structure, and is portable strong, and sufficient extending space and extended capability are arranged, and has good output waveform, and adjustable extent is large, and circuit protection, isolation are preferably arranged, and can independently switch, safe and reliable.
Description of drawings
Fig. 1 is circuit block diagram of the present invention;
Fig. 2 is the circuit theory diagrams of preceding-stage inversion circuit in the present invention;
Fig. 3 is the circuit theory diagrams of feedback circuit in the present invention;
Fig. 4 is the circuit theory diagrams of interface circuit in the present invention;
Fig. 5 is the circuit theory diagrams of power supply input circuit in the present invention;
Fig. 6 is the circuit theory diagrams of governor circuit in the present invention;
Fig. 7 is the circuit theory diagrams of transformer circuit in the present invention;
Fig. 8 is the circuit theory diagrams of inverter output circuit second portion in the present invention;
Fig. 9 is the circuit theory diagrams of inverter output circuit first in the present invention.
In figure: 1, governor circuit, 2, power supply input circuit, 3, the preceding-stage inversion circuit, 4, transformer circuit, 5, inverter output circuit, 6, feedback circuit, 7, the blower fan circuit, 8, failure indicating circuit, 9, interface circuit.
Embodiment
Below by specific embodiment, and by reference to the accompanying drawings, technical scheme of the present invention is described in further detail.
Embodiment:
a kind of inverter (referring to accompanying drawing 1), by power supply input circuit 2 power supplies, comprise interface circuit 9, governor circuit 1, feedback circuit 6, preceding-stage inversion circuit 3, transformer circuit 4 and inverter output circuit 5, described governor circuit 1 is electrically connected to described inverter output circuit 5 control ends by interface circuit 9, described governor circuit 1 also is connected with described preceding-stage inversion circuit 3 control ends, described power supply input circuit 2 is successively by preceding-stage inversion circuit 3, interface circuit 9 and transformer circuit 4 are electrically connected to described inverter output circuit 5, described governor circuit 1 also is electrically connected to described interface circuit 9 by described feedback circuit 6.Described interface circuit also is electrically connected to blower fan circuit 7 and failure indicating circuit 8.
Described power supply input circuit (referring to accompanying drawing 5) comprises input power, pressurizer, capacitor C 13 and capacitor C 1, the input of described pressurizer is connected with input power, capacitor C 13 and capacitor C 1 ground connection that the output single-pass of described pressurizer is excessively in parallel, described output end of voltage stabilizer output electric current of voltage regulation.
described governor circuit (referring to accompanying drawing 6) comprises process chip, loudspeaker MIC, resistance R 81, resistance R 82, resistance R 83, resistance R 84, resistance R 85, resistance R 86, resistance R 87, resistance R 89, resistance R 88, resistance R 91, resistance R 90, resistance R 101, resistance R 103, triode Q16, triode Q15, triode Q14, electric capacity E11, capacitor C 29 and capacitor C 28, described process chip is the SN8P2711 process chip, the process chip vdd terminal connects power supply input circuit, process chip AIN1 mouth ground connection, process chip P0.3 mouth is connected with protective circuit by resistance R 88, process chip P0.3 mouth also is connected with the base stage of triode Q15 by resistance R 88, the collector electrode of triode Q15 is connected with interface circuit, the collector electrode of triode Q15 also is connected with input power by resistance R 90, the grounded emitter of triode Q15, process chip P0.2 mouth is connected with protective circuit by resistance R 89, process chip P0.2 mouth also is connected with the base stage of triode Q16 by resistance R 89, the collector electrode of triode Q16 is connected with interface circuit, the collector electrode of triode Q16 also is connected with input power by resistance R 91, the grounded emitter of triode Q16, the P0.1 mouth of process chip is connected with interface circuit, and the P0.1 mouth of process chip also is connected with power supply input circuit by resistance R 101, the AIN4 mouth of process chip is connected with resistance R and is connected with interface circuit by resistance R 103, and the AIN4 mouth of process chip passes through resistance R 103, resistance R 82 and resistance R 83 ground connection successively, and the AIN4 mouth of process chip also passes through capacitor C 29 ground connection, process chip AIN3 mouth is by capacitor C 28 ground connection, and process chip AIN3 mouth is connected with power supply input circuit by resistance R 84, process chip AIN2 mouth is connected with interface circuit by resistance R 85, process chip AIN1 mouth is connected with interface circuit, process chip AIN1 mouth is also by electric capacity E11 ground connection, process chip AIN1 mouth is connected with the first end of resistance R 86, the second end of resistance R 86 is connected with the emitter of triode Q14, the collector electrode of triode Q14 is connected with power supply input circuit by loudspeaker MIC, and the base stage of triode Q14 is connected with the P0.0 mouth by resistance R 87, process chip P5.3 mouth is connected with process chip P5.4 mouth and is controlled output circuit and be connected, and process chip P4.0 mouth is connected with interface circuit.
described feedback circuit (referring to accompanying drawing 3) comprises resistance R 92, resistance R 93, resistance R 94, resistance R 95, resistance R 96, resistance R 97, resistance R 98, resistance R 99, resistance R 100, resistance 102, triode Q17, triode Q18, the first amplifier, the second amplifier, electric capacity E12, capacitor C 2, capacitor C 4, capacitor C 5, capacitor C 6, diode D27, diode D28 and rheostat VR1, the positive input terminal of described the first amplifier is connected with interface circuit by resistance R 98, the positive input terminal of the first amplifier is also by electric capacity E12 ground connection, the negative input end of the first amplifier is connected with power supply input circuit by resistance R 99, the negative input end of the first amplifier is also respectively by rheostat VR1 and capacitor C 6 ground connection, the output of the first amplifier is connected with power supply input circuit by resistance R 100, the output of the first amplifier also is connected with the positive input terminal of the second amplifier by diode D27, the negative input end of the second amplifier is respectively by resistance R 96 and capacitor C 2 ground connection, the negative input end of the second amplifier is connected with power supply input circuit by resistance R 95, the positive input terminal of the second amplifier respectively with the first end of resistance R 97, the first end that the first end of resistance R 102 is connected with capacitor C connects, the second end of resistance R 97 is connected with interface circuit, the second end that the second end of resistance R 102 is connected with capacitor C all is connected with power supply input circuit by resistance R 94, the second end that the second end of resistance R 102 is connected with capacitor C also is connected with the first end of resistance R 92 and the output of the second amplifier, the second end of resistance R 92 is connected with the base stage of triode Q17, the grounded emitter of triode Q17, the collector electrode of triode Q17 is connected with main control chip P0.2 by resistance R 89, the output of the second amplifier also is connected with process chip AIN4 mouth by diode D28, the output of the second amplifier is connected with the base stage of triode Q18 by resistance R 93, the collector electrode of triode Q18 is connected with process chip P0.3 mouth by resistance R 88, the grounded emitter of triode Q18.
described preceding-stage inversion circuit (referring to accompanying drawing 2) comprises resistance R 105, resistance R 16, resistance R 76, resistance R 77, resistance R 78, resistance R 79, resistance R 80, capacitor C 3, the 3rd amplifier, four high guaily unit, triode Q8, triode Q11, triode Q12 and triode Q13, the positive input terminal of the 3rd amplifier is connected with process chip P5.3 mouth by resistance R 78, the positive input terminal of the 3rd amplifier is also by resistance R 104 ground connection, the negative input end of the 3rd amplifier is respectively by resistance R 76 and C3 ground connection, the negative input end of the 3rd amplifier is connected with power supply input circuit by resistance R 16, the negative input end of the 3rd amplifier also is connected with the negative input end of four high guaily unit, the output of the 3rd amplifier is connected with input power by resistance R 79, the output of the 3rd amplifier also is connected with the base stage of triode Q8 and triode Q12, the collector electrode of triode Q8 is connected with input power, the output of triode Q8 is connected with interface circuit, the emitter of triode Q12 is connected with the emitter of triode Q8, the grounded collector of triode Q12, the 4th positive input terminal is connected with process chip P5.4 mouth by resistance R 77, the positive input terminal of four high guaily unit is also by resistance R 105 ground connection, the output of four high guaily unit is connected with input power by resistance R 80, the output of four high guaily unit also is connected with the base stage of triode Q11 and triode Q13, the collector electrode of triode Q11 is connected with input power, the emitter of triode Q11 is connected with interface circuit, the emitter of triode Q13 is connected with the emitter of triode Q11, the grounded collector of triode Q13.
described interface circuit (referring to accompanying drawing 4) comprises interface JP1 and electric capacity E15, and the port of interface JP1 comprises the P1 mouth, the P2 mouth, the DC mouth, the GND mouth, the power supply input port, the RT mouth, the FEN mouth, the AC_AD mouth, the H-DC mouth, the SWICH mouth, the LED mouth, the H1 mouth, the H2 mouth, SHORT mouth and LOAN mouth, the P1 mouth of interface JP1 is connected with the emitter of triode Q8, the P2 mouth of interface JP1 is connected with the emitter of triode Q11, the DC mouth of interface JP1 is connected with resistance R and is connected with process chip AIN1 mouth by resistance R 8 successively, the GND mouth ground connection of interface JP1, the power supply input port of interface JP1 is by electric capacity E15 ground connection, the power supply input port of interface JP1 also is connected with input power, the RT mouth of interface JP1 is connected with process chip AIN3 mouth, the FEN mouth of interface JP1 is connected with process chip AIN2 mouth by resistance R 85, the AC_AD mouth of interface JP1 is connected with process chip AIN1, the H-DC mouth of interface JP1 is connected with process chip P4.0 mouth, the SWICH mouth of interface JP1 is connected with process chip P0.4 mouth, the LED mouth of interface JP1 is connected with process chip P0.1 mouth, the H1 mouth of interface JP1 is connected with the collector electrode of triode Q15, the H2 mouth of interface JP1 is connected with the collector electrode of triode Q16, the SHORT mouth of interface JP1 is connected with the positive input terminal of the second amplifier by resistance R 97, and the LOAN mouth of interface JP1 is connected with the positive input terminal of the first amplifier by resistance R 98.
described transformer circuit (referring to accompanying drawing 7) comprises field effect transistor VT1, field effect transistor VT2, field effect transistor VT3, field effect transistor VT6, field effect transistor VT7, field effect transistor VT8, transformer T1, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 14, triode Q103, triode Q104, triode Q105, triode Q106, resistance R 6, resistance R 7, resistance R 8, resistance R 17, resistance R 18, resistance R 19, transformer T1 and rectifier bridge, the collector electrode of triode Q103 connects input power, the base stage of triode Q103 is connected base stage and is connected with the P1 mouth with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT1 by resistance R 6 with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT2 by resistance R 7 with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT3 by resistance R 8 with triode Q105, the grounded collector of triode Q105, the drain electrode of field effect transistor VT1, the drain electrode of field effect transistor VT2 is connected drain electrode and all is connected with the first input end of transformer T1 with field effect transistor VT3, the drain electrode of field effect transistor VT1, the drain electrode of the drain electrode of field effect transistor VT2 and field effect transistor VT3 all connects by capacitor C 10 and resistance R 11 successively and exchanges ground, the source electrode of field effect transistor VT1, the source electrode of the source electrode of field effect transistor VT2 and field effect transistor VT3 also all connects and exchanges ground, the collector electrode of triode Q104 connects input power, the base stage of triode Q104 is connected base stage and is connected with the P2 mouth with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT16 by resistance R 17 with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT17 by resistance R 18 with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT18 by resistance R 19 with triode Q106, the grounded collector of triode Q106, the drain electrode of field effect transistor VT6, the drain electrode of field effect transistor VT7 is connected drain electrode and all is connected with the first input end of transformer T1 with field effect transistor VT8, the drain electrode of field effect transistor VT6, the drain electrode of the drain electrode of field effect transistor VT7 and field effect transistor VT8 all connects by capacitor C 14 and resistance R 12 successively and exchanges ground, the source electrode of field effect transistor VT6, the source electrode of the source electrode of field effect transistor VT7 and field effect transistor VT8 also all connects and exchanges ground, first level coil output of transformer T1 is connected with the input of rectifier bridge, and the output of rectifier bridge is respectively by capacitor C 11 and capacitor C 12 ground connection.
described inverter output circuit is (referring to accompanying drawing 8, Fig. 9) comprise voltage stabilizing didoe D11, triode Q101, triode Q102, diode D3, diode D4, diode D5, diode D6, diode D7, diode D8, capacitor C 13, capacitor C 15, capacitor C 17, capacitor C 19, capacitor C 20, field effect transistor VT4, field effect transistor VT5, field effect transistor VT9, field effect transistor VT10, resistance R 9, resistance R 10, resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 21, resistance R 22, resistance R 23, resistance R 24, resistance R 25, resistance R 28, resistance R 29, resistance R 33, resistance R 34, resistance R 40, resistance R 41, resistance R 36, resistance R 37, resistance R 42, resistance R 43 and rheostat VT11, the drain electrode of the drain electrode of field effect transistor VT4 and field effect transistor V5 all is connected with the output of rectifier bridge, the grid of field effect transistor VT4 is connected with the second end of resistance R 9, the first end of resistance R 9 is connected with the collector electrode of triode Q101, the base stage of triode Q101 is by resistance R 36 ground connection, the base stage of triode Q101 also is connected with the H1 mouth by resistance R 37, the grounded emitter of triode Q101, the grid of field effect transistor VT4 also is connected with the negative electrode of diode D3, the anode of diode D3 is connected with the source electrode of field effect transistor VT4, the first end of resistance R 14 is connected with the first end of resistance R 9, the second end of resistance R 14 is connected with the first end of resistance R 15, the second end of resistance R 15 is connected with the source electrode of field effect transistor VT4, the first end of resistance R 15 also is connected with the negative electrode of diode D6, the anode of diode D6 is connected with input power, the negative electrode of diode D6 is connected with the drain electrode of field effect transistor VT10 by capacitor C 15 successively, the source electrode of the source electrode of field effect transistor VT10 and field effect transistor VT9 is respectively by resistance R 24, resistance R 25, resistance R 28 and resistance R 29 ground connection, the source electrode of field effect transistor VT10 is connected source electrode and also is connected with the SHORT mouth by resistance R 23 with field effect transistor VT9, the grid of field effect transistor VT10 is connected with process chip P5.3 mouth by diode D7, and the two ends of diode D7 are parallel with resistance R 21, the grid of field effect transistor VT5 is connected with the second end of resistance R 10, the first end of resistance R 10 is connected with the collector electrode of triode Q102, the base stage of triode Q102 is by resistance R 43 ground connection, the base stage of triode Q102 also is connected with the H2 mouth by resistance R 43, the grounded emitter of triode Q102, the grid of field effect transistor VT5 also is connected with the negative electrode of diode D4, the anode of diode D4 is connected with the source electrode of field effect transistor VT9, the first end of resistance R 13 is connected with the first end of resistance R 10, the second end of resistance R 13 is connected with the first end of resistance R 16, the second end of resistance R 16 is connected with the source electrode of field effect transistor VT9, the first end of resistance R 16 also is connected with the negative electrode of diode D5, the anode of diode D5 is connected with input power, the negative electrode of diode D5 is connected with the drain electrode of field effect transistor VT9 by capacitor C 13 successively, the grid of field effect transistor VT9 is connected with process chip P5.4 mouth by diode D8, the two ends of diode D8 are parallel with resistance R 20, be in series with capacitor C 19 between the anode of the anode of diode D3 and diode D4, the first end of resistance R 34 is connected with the negative electrode of voltage stabilizing didoe D11, the anode of voltage stabilizing didoe D11 is respectively by capacitor C 17 and resistance R 33 ground connection, the first end of resistance R 34 also is connected with the AC_AD mouth, the second end of resistance R 34 and the anodic bonding of diode D3, the first end of resistance R 41 is connected with the second end of rheostat VT11, the first end of rheostat VT11 is by capacitor C 20 ground connection, the second end of rheostat VT11 is by resistance R 40 ground connection, the first end of resistance R 41 also is connected with the negative electrode of voltage stabilizing didoe D11, the second end of resistance R 41 and the anodic bonding of diode D4, the anode of described diode D3 is inverter the first output, the anode of described diode D4 is inverter the second output.
Described inverter also comprises failure indicating circuit, described failure indicating circuit comprises overload sample circuit, frequency switching circuit, battery management circuit, busbar voltage loop circuit, faulty indication circuit for lamp, input power indicator light circuit and reset circuit, described overload sample circuit is connected with the LOAN mouth, frequency switching circuit is connected with the SWICH mouth, battery management circuit is connected with the DC mouth, the faulty indication circuit for lamp is connected with the LED mouth, the input power indicator light circuit is connected with input power, and reset circuit is connected with the RT mouth.
Described inverter also comprises the blower fan circuit, and the second subprime coil output of transformer T1 is connected with the inlet circuit of blower fan circuit, and the control end of blower fan circuit is connected with the FEN mouth.
Above-described embodiment is a kind of better scheme of the present invention, is not that the present invention is done any pro forma restriction, also has other variant and remodeling under the prerequisite that does not exceed the technical scheme that claim puts down in writing.
Claims (10)
1. inverter, powered by power supply input circuit, it is characterized in that: comprise interface circuit, governor circuit, feedback circuit, the preceding-stage inversion circuit, transformer circuit and inverter output circuit, described governor circuit is electrically connected to described inverter output circuit control end by interface circuit, described governor circuit also is connected with described preceding-stage inversion circuit control end, described power supply input circuit is successively by the preceding-stage inversion circuit, interface circuit and transformer circuit are electrically connected to described inverter output circuit, described governor circuit also is electrically connected to described interface circuit by described feedback circuit.
2. inverter according to claim 1, it is characterized in that: described power supply input circuit comprises input power, pressurizer, capacitor C 13 and capacitor C 1, the input of described pressurizer is connected with input power, capacitor C 13 and capacitor C 1 ground connection that the output single-pass of described pressurizer is excessively in parallel, described output end of voltage stabilizer output electric current of voltage regulation.
3. inverter according to claim 2, it is characterized in that: described governor circuit comprises process chip, loudspeaker MIC, resistance R 81, resistance R 82, resistance R 83, resistance R 84, resistance R 85, resistance R 86, resistance R 87, resistance R 89, resistance R 88, resistance R 91, resistance R 90, resistance R 101, resistance R 103, triode Q16, triode Q15, triode Q14, electric capacity E11, capacitor C 29 and capacitor C 28, described process chip is the SN8P2711 process chip, the process chip vdd terminal connects power supply input circuit, process chip AIN1 mouth ground connection, process chip P0.3 mouth is connected with protective circuit by resistance R 88, process chip P0.3 mouth also is connected with the base stage of triode Q15 by resistance R 88, the collector electrode of triode Q15 is connected with interface circuit, the collector electrode of triode Q15 also is connected with input power by resistance R 90, the grounded emitter of triode Q15, process chip P0.2 mouth is connected with protective circuit by resistance R 89, process chip P0.2 mouth also is connected with the base stage of triode Q16 by resistance R 89, the collector electrode of triode Q16 is connected with interface circuit, the collector electrode of triode Q16 also is connected with input power by resistance R 91, the grounded emitter of triode Q16, the P0.1 mouth of process chip is connected with interface circuit, and the P0.1 mouth of process chip also is connected with power supply input circuit by resistance R 101, the AIN4 mouth of process chip is connected with resistance R and is connected with interface circuit by resistance R 103, and the AIN4 mouth of process chip passes through resistance R 103, resistance R 82 and resistance R 83 ground connection successively, and the AIN4 mouth of process chip also passes through capacitor C 29 ground connection, process chip AIN3 mouth is by capacitor C 28 ground connection, and process chip AIN3 mouth is connected with power supply input circuit by resistance R 84, process chip AIN2 mouth is connected with interface circuit by resistance R 85, process chip AIN1 mouth is connected with interface circuit, process chip AIN1 mouth is also by electric capacity E11 ground connection, process chip AIN1 mouth is connected with the first end of resistance R 86, the second end of resistance R 86 is connected with the emitter of triode Q14, the collector electrode of triode Q14 is connected with power supply input circuit by loudspeaker MIC, and the base stage of triode Q14 is connected with the P0.0 mouth by resistance R 87, process chip P5.3 mouth is connected with process chip P5.4 mouth and is controlled output circuit and be connected, and process chip P4.0 mouth is connected with interface circuit.
4. inverter according to claim 3, it is characterized in that: described feedback circuit comprises resistance R 92, resistance R 93, resistance R 94, resistance R 95, resistance R 96, resistance R 97, resistance R 98, resistance R 99, resistance R 100, resistance 102, triode Q17, triode Q18, the first amplifier, the second amplifier, electric capacity E12, capacitor C 2, capacitor C 4, capacitor C 5, capacitor C 6, diode D27, diode D28 and rheostat VR1, the positive input terminal of described the first amplifier is connected with interface circuit by resistance R 98, the positive input terminal of the first amplifier is also by electric capacity E12 ground connection, the negative input end of the first amplifier is connected with power supply input circuit by resistance R 99, the negative input end of the first amplifier is also respectively by rheostat VR1 and capacitor C 6 ground connection, the output of the first amplifier is connected with power supply input circuit by resistance R 100, the output of the first amplifier also is connected with the positive input terminal of the second amplifier by diode D27, the negative input end of the second amplifier is respectively by resistance R 96 and capacitor C 2 ground connection, the negative input end of the second amplifier is connected with power supply input circuit by resistance R 95, the positive input terminal of the second amplifier respectively with the first end of resistance R 97, the first end that the first end of resistance R 102 is connected with capacitor C connects, the second end of resistance R 97 is connected with interface circuit, the second end that the second end of resistance R 102 is connected with capacitor C all is connected with power supply input circuit by resistance R 94, the second end that the second end of resistance R 102 is connected with capacitor C also is connected with the first end of resistance R 92 and the output of the second amplifier, the second end of resistance R 92 is connected with the base stage of triode Q17, the grounded emitter of triode Q17, the collector electrode of triode Q17 is connected with main control chip P0.2 by resistance R 89, the output of the second amplifier also is connected with process chip AIN4 mouth by diode D28, the output of the second amplifier is connected with the base stage of triode Q18 by resistance R 93, the collector electrode of triode Q18 is connected with process chip P0.3 mouth by resistance R 88, the grounded emitter of triode Q18.
5. inverter according to claim 4, it is characterized in that: described preceding-stage inversion circuit comprises resistance R 105, resistance R 16, resistance R 76, resistance R 77, resistance R 78, resistance R 79, resistance R 80, capacitor C 3, the 3rd amplifier, four high guaily unit, triode Q8, triode Q11, triode Q12 and triode Q13, the positive input terminal of the 3rd amplifier is connected with process chip P5.3 mouth by resistance R 78, the positive input terminal of the 3rd amplifier is also by resistance R 104 ground connection, the negative input end of the 3rd amplifier is respectively by resistance R 76 and C3 ground connection, the negative input end of the 3rd amplifier is connected with power supply input circuit by resistance R 16, the negative input end of the 3rd amplifier also is connected with the negative input end of four high guaily unit, the output of the 3rd amplifier is connected with input power by resistance R 79, the output of the 3rd amplifier also is connected with the base stage of triode Q8 and triode Q12, the collector electrode of triode Q8 is connected with input power, the output of triode Q8 is connected with interface circuit, the emitter of triode Q12 is connected with the emitter of triode Q8, the grounded collector of triode Q12, the 4th positive input terminal is connected with process chip P5.4 mouth by resistance R 77, the positive input terminal of four high guaily unit is also by resistance R 105 ground connection, the output of four high guaily unit is connected with input power by resistance R 80, the output of four high guaily unit also is connected with the base stage of triode Q11 and triode Q13, the collector electrode of triode Q11 is connected with input power, the emitter of triode Q11 is connected with interface circuit, the emitter of triode Q13 is connected with the emitter of triode Q11, the grounded collector of triode Q13.
6. inverter according to claim 5, it is characterized in that: described interface circuit comprises interface JP1 and electric capacity E15, and the port of interface JP1 comprises the P1 mouth, the P2 mouth, the DC mouth, the GND mouth, the power supply input port, the RT mouth, the FEN mouth, the AC_AD mouth, the H-DC mouth, the SWICH mouth, the LED mouth, the H1 mouth, the H2 mouth, SHORT mouth and LOAN mouth, the P1 mouth of interface JP1 is connected with the emitter of triode Q8, the P2 mouth of interface JP1 is connected with the emitter of triode Q11, the DC mouth of interface JP1 is connected with resistance R and is connected with process chip AIN1 mouth by resistance R 8 successively, the GND mouth ground connection of interface JP1, the power supply input port of interface JP1 is by electric capacity E15 ground connection, the power supply input port of interface JP1 also is connected with input power, the RT mouth of interface JP1 is connected with process chip AIN3 mouth, the FEN mouth of interface JP1 is connected with process chip AIN2 mouth by resistance R 85, the AC_AD mouth of interface JP1 is connected with process chip AIN1, the H-DC mouth of interface JP1 is connected with process chip P4.0 mouth, the SWICH mouth of interface JP1 is connected with process chip P0.4 mouth, the LED mouth of interface JP1 is connected with process chip P0.1 mouth, the H1 mouth of interface JP1 is connected with the collector electrode of triode Q15, the H2 mouth of interface JP1 is connected with the collector electrode of triode Q16, the SHORT mouth of interface JP1 is connected with the positive input terminal of the second amplifier by resistance R 97, and the LOAN mouth of interface JP1 is connected with the positive input terminal of the first amplifier by resistance R 98.
7. inverter according to claim 6, it is characterized in that: described transformer circuit comprises field effect transistor VT1, field effect transistor VT2, field effect transistor VT3, field effect transistor VT6, field effect transistor VT7, field effect transistor VT8, transformer T1, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 14, triode Q103, triode Q104, triode Q105, triode Q106, resistance R 6, resistance R 7, resistance R 8, resistance R 17, resistance R 18, resistance R 19, transformer T1 and rectifier bridge, the collector electrode of triode Q103 connects input power, the base stage of triode Q103 is connected base stage and is connected with the P1 mouth with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT1 by resistance R 6 with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT2 by resistance R 7 with triode Q105, triode Q103 is connected emitter and is connected with the grid of field effect transistor VT3 by resistance R 8 with triode Q105, the grounded collector of triode Q105, the drain electrode of field effect transistor VT1, the drain electrode of field effect transistor VT2 is connected drain electrode and all is connected with the first input end of transformer T1 with field effect transistor VT3, the drain electrode of field effect transistor VT1, the drain electrode of the drain electrode of field effect transistor VT2 and field effect transistor VT3 all connects by capacitor C 10 and resistance R 11 successively and exchanges ground, the source electrode of field effect transistor VT1, the source electrode of the source electrode of field effect transistor VT2 and field effect transistor VT3 also all connects and exchanges ground, the collector electrode of triode Q104 connects input power, the base stage of triode Q104 is connected base stage and is connected with the P2 mouth with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT16 by resistance R 17 with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT17 by resistance R 18 with triode Q106, triode Q104 is connected emitter and is connected with the grid of field effect transistor VT18 by resistance R 19 with triode Q106, the grounded collector of triode Q106, the drain electrode of field effect transistor VT6, the drain electrode of field effect transistor VT7 is connected drain electrode and all is connected with the first input end of transformer T1 with field effect transistor VT8, the drain electrode of field effect transistor VT6, the drain electrode of the drain electrode of field effect transistor VT7 and field effect transistor VT8 all connects by capacitor C 14 and resistance R 12 successively and exchanges ground, the source electrode of field effect transistor VT6, the source electrode of the source electrode of field effect transistor VT7 and field effect transistor VT8 also all connects and exchanges ground, first level coil output of transformer T1 is connected with the input of rectifier bridge, and the output of rectifier bridge is respectively by capacitor C 11 and capacitor C 12 ground connection.
8. inverter according to claim 7, it is characterized in that: described inverter output circuit comprises voltage stabilizing didoe D11, triode Q101, triode Q102, diode D3, diode D4, diode D5, diode D6, diode D7, diode D8, capacitor C 13, capacitor C 15, capacitor C 17, capacitor C 19, capacitor C 20, field effect transistor VT4, field effect transistor VT5, field effect transistor VT9, field effect transistor VT10, resistance R 9, resistance R 10, resistance R 13, resistance R 14, resistance R 15, resistance R 16, resistance R 21, resistance R 22, resistance R 23, resistance R 24, resistance R 25, resistance R 28, resistance R 29, resistance R 33, resistance R 34, resistance R 40, resistance R 41, resistance R 36, resistance R 37, resistance R 42, resistance R 43 and rheostat VT11, the drain electrode of the drain electrode of field effect transistor VT4 and field effect transistor V5 all is connected with the output of rectifier bridge, the grid of field effect transistor VT4 is connected with the second end of resistance R 9, the first end of resistance R 9 is connected with the collector electrode of triode Q101, the base stage of triode Q101 is by resistance R 36 ground connection, the base stage of triode Q101 also is connected with the H1 mouth by resistance R 37, the grounded emitter of triode Q101, the grid of field effect transistor VT4 also is connected with the negative electrode of diode D3, the anode of diode D3 is connected with the source electrode of field effect transistor VT4, the first end of resistance R 14 is connected with the first end of resistance R 9, the second end of resistance R 14 is connected with the first end of resistance R 15, the second end of resistance R 15 is connected with the source electrode of field effect transistor VT4, the first end of resistance R 15 also is connected with the negative electrode of diode D6, the anode of diode D6 is connected with input power, the negative electrode of diode D6 is connected with the drain electrode of field effect transistor VT10 by capacitor C 15 successively, the source electrode of the source electrode of field effect transistor VT10 and field effect transistor VT9 is respectively by resistance R 24, resistance R 25, resistance R 28 and resistance R 29 ground connection, the source electrode of field effect transistor VT10 is connected source electrode and also is connected with the SHORT mouth by resistance R 23 with field effect transistor VT9, the grid of field effect transistor VT10 is connected with process chip P5.3 mouth by diode D7, and the two ends of diode D7 are parallel with resistance R 21, the grid of field effect transistor VT5 is connected with the second end of resistance R 10, the first end of resistance R 10 is connected with the collector electrode of triode Q102, the base stage of triode Q102 is by resistance R 43 ground connection, the base stage of triode Q102 also is connected with the H2 mouth by resistance R 43, the grounded emitter of triode Q102, the grid of field effect transistor VT5 also is connected with the negative electrode of diode D4, the anode of diode D4 is connected with the source electrode of field effect transistor VT9, the first end of resistance R 13 is connected with the first end of resistance R 10, the second end of resistance R 13 is connected with the first end of resistance R 16, the second end of resistance R 16 is connected with the source electrode of field effect transistor VT9, the first end of resistance R 16 also is connected with the negative electrode of diode D5, the anode of diode D5 is connected with input power, the negative electrode of diode D5 is connected with the drain electrode of field effect transistor VT9 by capacitor C 13 successively, the grid of field effect transistor VT9 is connected with process chip P5.4 mouth by diode D8, the two ends of diode D8 are parallel with resistance R 20, be in series with capacitor C 19 between the anode of the anode of diode D3 and diode D4, the first end of resistance R 34 is connected with the negative electrode of voltage stabilizing didoe D11, the anode of voltage stabilizing didoe D11 is respectively by capacitor C 17 and resistance R 33 ground connection, the first end of resistance R 34 also is connected with the AC_AD mouth, the second end of resistance R 34 and the anodic bonding of diode D3, the first end of resistance R 41 is connected with the second end of rheostat VT11, the first end of rheostat VT11 is by capacitor C 20 ground connection, the second end of rheostat VT11 is by resistance R 40 ground connection, the first end of resistance R 41 also is connected with the negative electrode of voltage stabilizing didoe D11, the second end of resistance R 41 and the anodic bonding of diode D4, the anode of described diode D3 is inverter the first output, the anode of described diode D4 is inverter the second output.
9. inverter according to claim 8, it is characterized in that: described inverter also comprises failure indicating circuit, described failure indicating circuit comprises the overload sample circuit, frequency switching circuit, battery management circuit, the busbar voltage loop circuit, the faulty indication circuit for lamp, input power indicator light circuit and reset circuit, described overload sample circuit is connected with the LOAN mouth, frequency switching circuit is connected with the SWICH mouth, battery management circuit is connected with the DC mouth, the faulty indication circuit for lamp is connected with the LED mouth, the input power indicator light circuit is connected with input power, reset circuit is connected with the RT mouth.
10. inverter according to claim 9, it is characterized in that: described inverter also comprises the blower fan circuit, and the second subprime coil output of transformer T1 is connected with the inlet circuit of blower fan circuit, and the control end of blower fan circuit is connected with the FEN mouth.
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| CN201310047812.7A CN103117671B (en) | 2013-02-06 | 2013-02-06 | Inverter |
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| CN104362866A (en) * | 2014-11-10 | 2015-02-18 | 纽福克斯光电科技（上海）有限公司 | Inverter device |
| CN104506061A (en) * | 2014-11-12 | 2015-04-08 | 宁波中博电器有限公司 | Low no-load current inverter |
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| CN103117671B (en) | 2014-12-10 |
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