CN103117307A - Silicon transverse double-diffusion field effect transistor on high-reliability P-type insulator - Google Patents
Silicon transverse double-diffusion field effect transistor on high-reliability P-type insulator Download PDFInfo
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- CN103117307A CN103117307A CN2013100253373A CN201310025337A CN103117307A CN 103117307 A CN103117307 A CN 103117307A CN 2013100253373 A CN2013100253373 A CN 2013100253373A CN 201310025337 A CN201310025337 A CN 201310025337A CN 103117307 A CN103117307 A CN 103117307A
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Abstract
A silicon transverse double-diffusion field effect transistor on a high-reliability P-type insulator comprises a P-type substrate, wherein a buried oxide layer is arranged on the P-type substrate, a N-trap is arranged on the buried oxide layer, a N trap and a P trap are arranged inside the N-trap, a N-shaped-body contact zone and a P-type source zone are arranged inside the N trap, field oxide layers are arranged on the surfaces of the N-trap, the N trap, and the P trap, polysilicon gates are arranged on the surfaces of field oxide layers, passivation layers are arranged on the surfaces of the N-shaped-body contact zone, the P-type source zone, the polysilicon gates, the field oxide layers, and a P-type leak zone, the P-trap is arranged below the P-type leak zone and part of field oxide layers, and the bottom end of the P-trap penetrates through the P trap and is connected with the buried oxide layer. The structure can effectively restrain the influence of kirk effect, lowers an electric field of the P-type leak zone, and therefore capacity of breakdown voltage in a fired state and bleeder current of a device is raised.
Description
Technical field
The present invention relates generally to the reliability field of high-voltage power semiconductor device, specifically, be a kind of P type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor with high reliability, be applicable to plasma flat-plate display device, half-bridge drive circuit and automobile production field.
Background technology
Developing rapidly of power integrated circuit industry makes power device obtain develop rapidly, and its market is used also and progressively enlarged, and demand grows with each passing day.Power lateral double-diffused metal-oxide-semiconductor transistor (Lateral double diffused metal oxide semiconductor, LDMOS) because the advantage such as simplicity of design, processing compatibility be good is widely used in high-voltage power integrated circuit.
SOI(Silicon-On-Insulator, the silicon on dielectric substrate) technology is to have introduced one deck between at the bottom of top layer silicon and backing to bury oxide layer.By forming semiconductive thin film on insulator, the SOI material had advantages of body silicon incomparable: can realize the medium isolation of components and parts in integrated circuit, thoroughly eliminate the parasitic latch-up in the Bulk CMOS circuit; Adopt the integrated circuit that this material is made also to have the advantages such as parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little.
Silicon-on-insulator lateral bilateral diffusion field-effect tranisistor (SOI-LDMOS) is that a kind of it combines both advantages typically based on the device of SOI technique, has the advantages such as withstand voltage height, current drive capability are strong, is widely applied in power integrated circuit.But be operated in due to power device under the environment of high voltage, large electric current, be faced with very severe integrity problem, when having large electric current to pass through in the silicon-on-insulator lateral bilateral diffusion field-effect tranisistor, because the base broadening can occur the Kirk effect, cause electric current to enlarge markedly, puncture.Simultaneously, when horizontal dual pervasion field effect transistor is used in when releasing large electric current in electrostatic discharge protection circuit, also can due to Kirk effect generation base broadening, cause the ability of leakage current significantly to descend.At present, Chinese scholars has proposed many SOI-LDMOS device reliabilities of improving one's methods to improve from device architecture.For example, extend device drift region length and effectively avoid the Kirk effect, thereby reduced the risk of device breakdown and leakage current ability.Similarly method has a lot, but they improving under the advantage of integrity problem, also have not enough place, such as the current capacity of device normal operation descends, the enlarging markedly and technique release's complexity raising etc. of device area.
Round the requirement of high-pressure process to high ON state puncture voltage, high leakage current ability and lower cost, the present invention proposes a kind of P type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor with high reliability, compare with general silicon-on-insulator lateral bilateral diffusion field-effect tranisistor structure, its ON state puncture voltage and leakage current ability are significantly improved.
Summary of the invention
The present invention is exactly for the problems referred to above, has proposed a kind of P type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor that can improve the high reliability of device ON state puncture voltage and leakage current ability.
the present invention adopts following technical scheme: P type substrate, be provided with on P type substrate and bury oxide layer, be provided with the N-trap on oxide layer burying, be provided with N trap and P trap in the inside of N-trap, be provided with N-type body contact zone and P type source region in the inside of N trap, the inside of P trap is provided with P type drain region, at the N-trap, the surface of N trap and P trap is provided with field oxide, and an end in an end of field oxide and P type source region offsets, the other end of described field oxide extends and terminates in the border in P type drain region to P type drain region, surface at field oxide is provided with polysilicon gate, in N-type body contact zone, P type source region, polysilicon gate, the surface in field oxide and P type drain region is provided with passivation layer, surface in N-type body contact zone and P type source region is connected with the first metal layer, be connected with the second metal level on the surface of polysilicon gate, surface in P type drain region is connected with the 3rd metal level, be provided with the P-trap below P type drain region and part field oxide, described P-trap bottom pass the P trap and with bury oxide layer and join
The overlapping parts transversely length of P-trap and P trap is 3-5 μ m, and the vertical degree of depth of overlapping part is 3-5 μ m.The doping content of P-trap is a times to two times of P trap doping content, and the Implantation Energy of P-trap is two to three times of Implantation Energy of P trap.
Compared with prior art, the present invention has following advantage:
(1), device of the present invention is provided with P-trap 15 below P type drain region 6 and part field oxide 12, and P-trap 15 bottoms with bury oxide layer 2 and join, the appearance of P-trap 15 makes Electric Field Distribution be tending towards device inside, hole current path under the ON state condition disperses more, therefore the Kirk effect that is caused by large injection and high electric field can be suppressed well, and then boost device ON state puncture voltage effectively.Can find out with reference to Fig. 3, the ON state breakdown potential of structure of the present invention has been pressed with obvious lifting.
(2), device of the present invention is provided with P-trap 15 below P type drain region 6 and part field oxide 12, and P-trap 15 bottoms with bury oxide layer 2 and join, hole current path when the introducing of P-trap 15 is opened parasitic transistor on the one hand extends near oxygen buried layer, make CURRENT DISTRIBUTION more disperse, under the identical condition of total current, lattice temperature is lower; Optimized on the other hand the electric field between N-trap 3 and P trap 5, the distribution of electric field is more even, and the Joule heat that produces under identical current condition still less.Thereby the introducing of P-trap 15 has improved the ability of parasitic transistor leakage current, and the antistatic capacity of device promotes greatly.Can find out with reference to Fig. 4, in the situation that junction temperature is identical, structure of the present invention can the more electric current of bleeding ratio general structure.
(3), device of the present invention adopts silicon (Silicon-On-Insulator on high voltage insulator, SOI) technique, in technique, the injection of P-trap 15 can utilize the anti-version of the lithography mask version of N-trap 3 injections, and namely two traps can share a lithography mask version, thereby can not increase extra cost.
(4), the manufacture craft of device of the present invention can with existing CMOS process compatible, be easy to preparation.
Description of drawings
Fig. 1 is the device profile structure of the P type horizontal dual pervasion field effect transistor under general silicon-on-insulator process.
Fig. 2 is the P type horizontal dual pervasion field effect transistor device profile structure under silicon-on-insulator process after the present invention improves.
The comparison diagram of the current-voltage correlation when Fig. 3 is the horizontal dual pervasion field effect transistor ON state of device of the present invention and general structure.The ON state puncture voltage that can find out structure of the present invention is greatly improved compared to general structure.
Electric current when Fig. 4 is the horizontal dual pervasion field effect transistor OFF state of device of the present invention and general structure and the comparison diagram of junction temperature relation.Can find out in the situation that junction temperature is identical, device of the present invention can the more electric current of the general device of bleeding ratio.
Embodiment
below in conjunction with accompanying drawing 2, the present invention is elaborated, a kind of high reliability P type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor, comprise: P type substrate 1, be provided with on P type substrate 1 and bury oxide layer 2, be provided with N-trap 3 on oxide layer 2 burying, be provided with N trap 4 and P trap 5 in the inside of N-trap 3, be provided with N-type body contact zone 7 and P type source region 8 in the inside of N trap 4, the inside of P trap 5 is provided with P type drain region 6, at N-trap 3, the surface of N trap 4 and P trap 5 is provided with field oxide 12, and an end in an end of field oxide 12 and P type source region 8 offsets, the other end of described field oxide is 6 borders of extending and terminate in P type drain region 6 to P type drain region, be provided with polysilicon gate 11 on the surface of field oxide 12, in N-type body contact zone 7, P type source region 8, polysilicon gate 11, the surface in field oxide 12 and P type drain region 6 is provided with passivation layer 9, in N-type body contact zone 7 and the surface in P type source region 8 be connected with the first metal layer 10, be connected with the second metal level 13 on the surface of polysilicon gate 11, 6 surface is connected with the 3rd metal level 14 in P type drain region, , be provided with P-trap 15 below P type drain region 6 and part field oxide 12, described P-trap 15 bottoms pass P trap 5 and with bury oxide layer 2 and join.
Described P-trap 15 is 3-5 μ m with the overlapping parts transversely length of P trap 5, and the vertical degree of depth of overlapping part is 3-5 μ m.
The doping content of described P-trap 15 is times to two times of P trap 5 doping contents, and the Implantation Energy of P-trap 15 is two to three times of Implantation Energy of P trap 5.
The dopant dose of described P-trap 15 is 6e12cm
-2, Implantation Energy is 120Kev, the dopant dose of P trap 5 is 3e12cm
-2, Implantation Energy is 40Kev.
The present invention adopts following method to prepare:
At first be that SOI makes, wherein epitaxial loayer adopts the doping of P type.Ensuing is the making of horizontal dual pervasion field effect transistor, is included on P type extension and forms N-trap 3 by injecting phosphonium ion, and the dopant dose of N-trap 3 is 2.5e12cm
-2, Implantation Energy is 120Kev, and then forms P-trap 15 by the boron Implantation on P type extension, the dopant dose of P-trap 15 is 6e12cm
-2, Implantation Energy is 120Kev.Next injects N trap 4 and P trap 5, and the dopant dose of N trap 4 is 1.8e12cm
-2, Implantation Energy is 140Kev, the dopant dose of P trap 5 is 3e12cm
-2, Implantation Energy is 40Kev.Then be field oxide 12, depositing polysilicon 11 afterwards, and etching forms grid, then make heavily doped N-type body contact zone 7, P type source region 8 and P type drain region 6.Deposit silicon dioxide, depositing metal behind etching electrode contact district, then etching metal and extraction electrode carry out Passivation Treatment at last.
Claims (4)
1. high reliability P type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor, comprise: P type substrate (1), be provided with on P type substrate (1) and bury oxide layer (2), be provided with N-trap (3) on oxide layer (2) burying, be provided with N trap (4) and P trap (5) in the inside of N-trap (3), be provided with N-type body contact zone (7) and P type source region (8) in the inside of N trap (4), the inside of P trap (5) is provided with P type drain region (6), in N-trap (3), the surface of N trap (4) and P trap (5) is provided with field oxide (12), and an end in an end of field oxide (12) and P type source region (8) offsets, the other end of described field oxide extends and terminates in the border in P type drain region (6) to P type drain region (6), be provided with polysilicon gate (11) on the surface of field oxide (12), in N-type body contact zone (7), P type source region (8), polysilicon gate (11), the surface in field oxide (12) and P type drain region (6) is provided with passivation layer (9), surface in N-type body contact zone (7) and P type source region (8) is connected with the first metal layer (10), be connected with the second metal level (13) on the surface of polysilicon gate (11), be connected with the 3rd metal level (14) on the surface in P type drain region (6), it is characterized in that, below at P type drain region (6) and part field oxide (12) is provided with P-trap (15), described P-trap (15) bottom pass P trap (5) and with bury oxide layer (2) and join.
2. a kind of high reliability P type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor according to claim 1, is characterized in that P-trap (15) and the overlapping parts transversely length of P trap (5) are 3-5 μ m, and the vertical degree of depth of overlapping part is 3-5 μ m.
3. a kind of high reliability P type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor according to claim 1, the doping content that it is characterized in that P-trap (15) is a times to two times of P trap (5) doping content, and the Implantation Energy of P-trap (15) is two to three times of Implantation Energy of P trap (5).
4. a kind of high reliability P type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor according to claim 3, the dopant dose that it is characterized in that P-trap (15) is 6e12cm
-2, Implantation Energy is 120Kev, the dopant dose of P trap (5) is 3e12cm
-2, Implantation Energy is 40Kev.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11251597A (en) * | 1998-02-27 | 1999-09-17 | Denso Corp | Semiconductor device |
| US20020043699A1 (en) * | 2000-10-18 | 2002-04-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
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- 2013-01-24 CN CN2013100253373A patent/CN103117307A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11251597A (en) * | 1998-02-27 | 1999-09-17 | Denso Corp | Semiconductor device |
| US20020043699A1 (en) * | 2000-10-18 | 2002-04-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
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Application publication date: 20130522 |