CN103107545A - Pulse-width modulation (PWM) signal generation device of scalable vector graphics (SVG) reactive power compensation generator - Google Patents
Pulse-width modulation (PWM) signal generation device of scalable vector graphics (SVG) reactive power compensation generator Download PDFInfo
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- CN103107545A CN103107545A CN2011103523943A CN201110352394A CN103107545A CN 103107545 A CN103107545 A CN 103107545A CN 2011103523943 A CN2011103523943 A CN 2011103523943A CN 201110352394 A CN201110352394 A CN 201110352394A CN 103107545 A CN103107545 A CN 103107545A
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Abstract
The invention provides a pulse-width modulation (PWM) signal generation device of a scalable vector graphics (SVG) reactive power compensation generator and aims at overcoming the defect that PWM signal output pins of a digital signal processor (DSP) digital signal generator are insufficient in quantity. According to the PWM signal generation device, a DSP digital signal processor, a field programmable gate array (FPGA), a complex programmable logic device (CPLD) and other programmable logic devices are adopted and form a hardware platform with an insulated gate bipolar translator (IGBT) power module provided with twelve H-bridge power units, and a plurality of isolation transformers. The PWM signal generation device is combined with a relevant phase shift processing algorithm to generate controllable multilevel PWM signals so that output PWM modulating waves pass through twelve windings and the isolation transformers with three-phase windings and are fed back to a power distribution network to finally carry out compensation to the reactive power amount generated by load. The PWM signal generation device has the advantages of being simple in relative control, high in operational reliability, and good in universality and expandability, enabling most of switching harmonic waves to be capable of offsetting each other, and the like.
Description
Technical field
Patent of the present invention relates to a kind of SVG reactive power compensation generator pwm signal generation device.
Background technology
The basic principle of SVG reactive power compensation generator is to utilize to turn-off device for high-power power electronic, for example use that the IGBT large power semiconductor device forms from the commutation bridge circuit, be connected in parallel on electrical network through reactor, suitably regulate amplitude and the phase place of bridge circuit AC output voltage, perhaps directly control its ac-side current, just can make this circuit absorb or send the reactive current that meets the demands, realize the purpose of dynamic passive compensation.The core of conventional SVG reactive power compensation generator inside mainly is comprised of DSP digital signal processor and IGBT large power semiconductor device drive circuit and other auxiliary protection circuit.Pwm pulse bandwidth modulation signals output pin restricted number due to traditional DSP digital signal processor self, tend to unable to do what one wishes if a fairly large number of IGBT device is carried out pwm signal control, if it is often barely satisfactory aspect control flexibility and autgmentability to adopt professional pwm signal to generate element, and it is also often larger to control cost.
Summary of the invention
Patent of the present invention is the pwm signal generation device that adopts on a kind of SVG reactive power compensation generator apparatus, this device adopts programmable logic device to consist of hardware platform together with the light-coupled isolation driving element, and generate controlled multiplex PWM ripple signal in conjunction with relevant phase shift Processing Algorithm, have that relative control is simple, most of switch harmonic can be cancelled out each other, functional reliability is high, and Universal and scalability is the characteristics such as better all.By the problem of this device with regard to the pwm signal output lazy weight of the traditional DSP digital signal processor of the fine solution of energy.
The technical scheme of patent of the present invention is as follows: a kind of SVG reactive power compensation generator pwm signal generation device is comprised of FPGA control unit, CPLD interface processing unit, H bridge power unit and multichannel isolating transformer, it is characterized in that: the FPGA control unit is connected with the CPLD interface processing unit signal of telecommunication, CPLD interface processing unit is connected with the H bridge power unit signal of telecommunication, and the H bridge power unit is connected with the multichannel isolating transformer signal of telecommunication.
Described FPGA control unit connects the FPGA main control chip by the RAM data storage and becomes with the DSP bank of digital signal processors, wherein the main control chip model of RAM data storage is IS61LV51216, FPGA main control chip model is EP1C6Q240, and DSP digital signal processor main control chip model is TMS28335.
Described CPLD interface processing unit is comprised of CPLD main control chip EPM570T100C5 connection light-coupled isolation driving element, multichannel isolation power supply circuits.
Described H bridge power unit is comprised of the IGBT power model.
in patent scheme of the present invention, the calculation process of carrying out the SVG Arithmetic for Reactive Power Compensation after the DSP digital signal processor is processed the analog data acquisitions such as power distribution network and load voltage electric current generates the three phase sine first-harmonic, data are transferred to the FPGA control unit by parallel bus and set low an IO mouth line notice FPGA control unit and fetch data, the dual port RAM data Caching Mechanism has been adopted in FPGA control unit inside, when the FPGA control unit receive DSP set low status signal after just remove the data buffer zone reading out data, data being carried out the three-phase first-harmonic data that obtain after Error detection is processed compares with inner triangular wave and generates multi-channel PWM ripple signal, the PWM ripple signal that generates is transferred to CPLD interface processing unit by the data flat cable, CPLD interface processing unit is prevented straight-through process and adding the dead band processing then to export to the light-coupled isolation driving element to PWM ripple signal, the light-coupled isolation driving element drives the IGBT power model in the H bridge power unit, the isolating transformer that each H bridge power unit output PWM modulating wave turns three phase windings through 12 windings feeds back to power distribution network and the idle amount that finally load produced compensates.
Patent of the present invention has following advantage:
1. adopt the programmable logic devices such as conventional FPGA and CPLD to consist of hardware platform together with the light-coupled isolation driving element, had a hardware cost relatively cheap and be convenient to secondary development.
2. adopt the phase shift Processing Algorithm to generate controlled multiplex PWM ripple signal, have that relative control is simple, most of switch harmonic can be cancelled out each other, functional reliability is high.
3. adopted the inner dual port RAM data buffering of FPGA function, simplified development cost, and expand after also being connected other universal I/O ports being convenient to as the redundancy of function outside having kept conventional and parallel data bus line that DSP is connected, also increase the detection and removal function of error code at the parallel data receiving unit, made the more stable work of device reliable.
4. adopted PWM dead band control and prevented the direct conducting control logic of IGBT, further having increased reliability and the fail safe of pwm signal output.
5. the method that has adopted FPGA and CPLD hardware circuit to separate, adopt flat mouthful of bus cable to come transmission of digital signals, be convenient to so the later ports-Extending of total system, get final product if need the outlet line of increase or change pwm signal only need change corresponding CPLD plate, be convenient to later Function Extension and secondary development.
Description of drawings
Accompanying drawing is hardware circuit and the control logic schematic diagram of patent of the present invention, wherein: 1, be the FPGA control unit, 2, be CPLD interface processing unit, 3, be the H bridge power unit, 4, be the multichannel isolating transformer.
Embodiment
Below in conjunction with accompanying drawing, patent of the present invention is described in further detail:
A kind of SVG reactive power compensation generator pwm signal generation device is comprised of FPGA control unit, CPLD interface processing unit, H bridge power unit and multichannel isolating transformer as shown in drawings, wherein the FPGA control unit is connected with the CPLD interface processing unit signal of telecommunication, CPLD interface processing unit is connected with the H bridge power unit signal of telecommunication, and the H bridge power unit is connected with the multichannel isolating transformer signal of telecommunication.
Described FPGA control unit connects the FPGA main control chip by the RAM data storage and becomes with the DSP bank of digital signal processors, wherein the main control chip model of RAM data storage is IS61LV51216, FPGA main control chip model is EP1C6Q240, and DSP digital signal processor main control chip model is TMS28335.
Described CPLD interface processing unit is comprised of CPLD main control chip EPM570T100C5 connection light-coupled isolation driving element, multichannel isolation power supply circuits.
Described H bridge power unit is comprised of the IGBT power model.
after processing the analog data acquisitions such as power distribution network and load voltage electric current, the DSP digital signal processor carries out the calculation process of SVG Arithmetic for Reactive Power Compensation, generate the three phase sine first-harmonic, data are transferred to the FPGA control unit by parallel bus, and set low IO mouth line notice FPGA control unit and fetch data, the dual port RAM data Caching Mechanism has been adopted in FPGA control unit inside, when the FPGA control unit receive the DSP digital signal processor set low status signal after just remove the data buffer zone reading out data, data being carried out the three-phase first-harmonic data that obtain after Error detection is processed compares with inner triangular wave and generates multi-channel PWM ripple signal.Here adopted the processing method of multiplex, it is every that to adopt mutually 4 H bridge unit to carry out parallel connection be namely every phase four H bridges with one pole frequency multiplication phase-shifting carrier wave technology, generate 50Hz sinusoidal reference waveform by FPGA control unit self, per cycles 1024 point, triangular carrier 3kHz, for a certain phase, carrier wave corresponding to 4 H bridge power unit left arms is since 0 ° of 45 ° of phase shift successively, carrier wave corresponding to H bridge power unit right arm is since 180 ° of 45 ° of phase shifts successively, 120 ° of three-phase mutual deviations.The PWM ripple signal that generates is transferred to CPLD interface processing unit by the data flat cable, CPLD interface processing unit is prevented straight-through process and adding the dead band processing then to export to the light-coupled isolation driving element to PWM ripple signal, the light-coupled isolation driving element drives the IGBT power module circuit of H bridge power unit, and the isolating transformer that each H bridge power unit output PWM modulating wave turns three phase windings through 12 windings feeds back to power distribution network and the idle amount that finally load produced compensates.
when patent of the present invention is used, need to carry out the programming of analogue data sampling processing and SVG control algolithm aspect for the DSP digital signal processor, its output three phase sine first-harmonic data are transferred to the FPGA control unit by parallel bus, its multi-channel PWM ripple signal generating algorithm produces by FPGA control unit device, because having kept, the FPGA control unit connected the outside PWM ripple of DSP digital signal processor pin, therefore also can adopt DSP digital signal processor internal logic to produce PWM ripple signal, the method of this signal being carried out secondary phase shift expansion in FPGA control unit inside equally can realize the generation output of multi-channel PWM ripple signal, flexibility due to the programming of FPGA control unit, we just can be to the generation quantity of PWM ripple signal, modulating frequency, modulation rate, multiplex mode etc. defines flexibly.The method of this patent of invention has been expanded the limitation of traditional DSP DSP chip PWM ripple signal modulation, has reduced R﹠D costs.dead band treatment mechanism that CPLD interface processing unit chip internal is integrated, output is connected with the light-coupled isolation driving element, therefore can directly connect and drive the IGBT power model, because having adopted FPGA control unit and CPLD interface, this device processes the method that the unit hardware circuit separates, adopt flat mouthful of bus cable to come transmission of digital signals, be convenient to so the later ports-Extending of total system, if needing the outlet line of increase or change pwm signal only need change corresponding CPLD plate gets final product, be convenient to later Function Extension and secondary development, the H bridge power unit has partly adopted the technology of multiplex parallel connection to reduce greatly the relative harmonic content of system, the employing of multichannel isolating transformer has also increased fail safe and the adaptability of equipment simultaneously.
Claims (4)
1.SVG reactive power compensation generator pwm signal generation device is comprised of FPGA control unit, CPLD interface processing unit, H bridge power unit and multichannel isolating transformer, it is characterized in that: the FPGA control unit is connected with the CPLD interface processing unit signal of telecommunication, CPLD interface processing unit is connected with the H bridge power unit signal of telecommunication, and the H bridge power unit is connected with the multichannel isolating transformer signal of telecommunication.
2. SVG reactive power compensation generator pwm signal generation device according to claim 1, it is characterized in that: described FPGA control unit connects the FPGA main control chip by the RAM data storage and becomes with the DSP bank of digital signal processors, wherein the main control chip model of RAM data storage is IS61LV51216, FPGA main control chip model is EP1C6Q240, and DSP digital signal processor main control chip model is TMS28335.
3. SVG reactive power compensation generator pwm signal generation device according to claim 1 is characterized in that: described CPLD interface processing unit by CPLD main control chip EPM570T100C5 connect the light-coupled isolation driving element, multichannel isolation power supply circuits form.
4. SVG reactive power compensation generator pwm signal generation device according to claim 1, it is characterized in that: described H bridge power unit is comprised of the IGBT power model.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104375448A (en) * | 2014-11-29 | 2015-02-25 | 安徽鑫龙电器股份有限公司 | Reactive compensation control system with dual-core framework |
| CN110247549A (en) * | 2019-06-13 | 2019-09-17 | 东北电力大学 | A kind of reduction voltage circuit and control method based on switching Affine Systems |
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| CN101459335A (en) * | 2008-11-03 | 2009-06-17 | 天津理工大学 | Control apparatus for three level dynamic voltage recovery device |
| CN102004455A (en) * | 2010-09-25 | 2011-04-06 | 天津理工大学 | STATCOM (Static Synchronous Compensator) control system based on mixed chaotic sequence generator |
| CN102096407A (en) * | 2011-01-28 | 2011-06-15 | 中电普瑞科技有限公司 | Chain type STATCOM control system based on EtherCA technology |
| CN202285334U (en) * | 2011-11-09 | 2012-06-27 | 哈尔滨九洲电气股份有限公司 | Pulse-width modulation (PWM) signal generator of scalable vector graphics (SVG) reactive power compensation generator |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1937349A (en) * | 2006-10-25 | 2007-03-28 | 北京四方清能电气电子有限公司 | Comprehensive dynamic compensating device for distribution network |
| CN101459335A (en) * | 2008-11-03 | 2009-06-17 | 天津理工大学 | Control apparatus for three level dynamic voltage recovery device |
| CN102004455A (en) * | 2010-09-25 | 2011-04-06 | 天津理工大学 | STATCOM (Static Synchronous Compensator) control system based on mixed chaotic sequence generator |
| CN102096407A (en) * | 2011-01-28 | 2011-06-15 | 中电普瑞科技有限公司 | Chain type STATCOM control system based on EtherCA technology |
| CN202285334U (en) * | 2011-11-09 | 2012-06-27 | 哈尔滨九洲电气股份有限公司 | Pulse-width modulation (PWM) signal generator of scalable vector graphics (SVG) reactive power compensation generator |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104375448A (en) * | 2014-11-29 | 2015-02-25 | 安徽鑫龙电器股份有限公司 | Reactive compensation control system with dual-core framework |
| CN110247549A (en) * | 2019-06-13 | 2019-09-17 | 东北电力大学 | A kind of reduction voltage circuit and control method based on switching Affine Systems |
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Application publication date: 20130515 |