CN103097902A

CN103097902A - Improving at-speed test access port operations

Info

Publication number: CN103097902A
Application number: CN2011800371468A
Authority: CN
Inventors: L·D·威特赛
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2010-07-29
Filing date: 2011-07-29
Publication date: 2013-05-08
Anticipated expiration: 2031-07-29
Also published as: JP5832535B2; CN103097902B; JP2013545963A

Abstract

An integrated circuit's 1149.1 TAP performs at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.; In a third embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment the at-speed operations are achieved by detecting the TAP's ExitlDR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit.

Description

Improve test access port operation at full speed

Background technology

IEEE1149.1 test access port (TAP) is widely used as controlling the IC interface of being permitted eurypalynous embedded IC circuit in semi-conductor industry, such as but not limited to, test circuit, debug circuit, programmed circuit, equipment circuit and tracking circuit.It is effective to the operation of controlling embedded IC circuit that TAP was proved to be in 20 years.Yet TAP is not proved to be control is depended on Geng Xin ﹠amp at full speed; Catch and and ﹠amp; Catch (at speed Update﹠amp; Capture and Shift﹠amp; Capture) operation of the embedded IC circuit of operation is effective.Geng Xin ﹠amp has at full speed described in first of the present disclosure (Fig. 1-7); Catch and and ﹠amp; Trapped problems.Second portion of the present disclosure (Fig. 8-41) has been described the new solution to this problem of using various example implementation.

Summary of the invention

The disclosure has been described new solution, and it upgrades ﹠amp by TAP being expanded the full speed that has extra circuit to solve TAP; Catch and and ﹠amp; Trapped problems.In first disclosed solution of Fig. 8-28, by with the cmd signal time division multiplexing to the input of TAP and cmd signal is input to order (CMD) circuit of the full-speed operation of controlling data register, realize full-speed operation with this.In the second disclosed solution of Figure 29 A-33, thereby the ExitlDR state by detecting TAP produces cmd signal to the CMD circuit of the full-speed operation of controlling data register, realizes full-speed operation with this.In the 3rd the disclosed solution of Figure 34 A-38, thereby produce by ExitlDR and the PauseDR state that detects TAP full speed renewal and the lock-on signal that is imported into data register via programmable switch (PSW) circuit, realize full-speed operation with this.In the 4th disclosed solution of Figure 39-41, thereby produce by ExitlDR and the PauseDR state that detects TAP full speed renewal and the lock-on signal that is imported into data register via two-port router, realize full-speed operation with this.Whole disclosed solutions can expand renewal and the lock-on signal that accessible outside is arranged, thereby allow tester directly to control the full-speed operation of data register.

Description of drawings

Fig. 1 illustrates the IEEE1149.1TAP framework.

Fig. 2 illustrates for Tap state machine (TSM) data register is controlled the router circuit that (DRC) signal is routed to data register.

Fig. 3 illustrates the constitutional diagram of TSM.

Fig. 4 illustrates by TSM and controls asynchronous CSU data register via router.

Fig. 5 illustrates by TSM and controls synchronous CSU data register via router.

Fig. 6 illustrates by TSM and controls asynchronous CS data register via router.

Fig. 7 illustrates by TSM and controls synchronous CS data register via router.

Fig. 8 illustrates the IEEE1149.1TAP that order (CMD) circuit and two-port router are arranged according to expansion of the present disclosure.

Fig. 9 illustrates according to of the present disclosure for drc signal is routed to the two-port router circuit of data register from TSM or CMD circuit.

Figure 10 illustrates according to of the present disclosure for using the CMD circuit to carry out the sequential chart of CS or CSU operation.

Figure 11 illustrates the asynchronous CSU data register of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 12 illustrates the synchronous CSU data register of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 13 illustrates the asynchronous CS data register of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 14 illustrates the synchronous CS data register of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 15 illustrates the asynchronous CS data register of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 16 illustrates the first test compression framework of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 17 illustrates the second test compression framework of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 18 illustrates IEEE1500 shell (wrapper) framework of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 19 illustrates the read/write circuits framework of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 20 illustrates the IEEE P1687 Instrument structure of being controlled via two-port router by TSM or CMD circuit according to of the present disclosure.

Figure 21 illustrates the first daisy chain device according to execution external testing operation of the present disclosure.

Figure 22 illustrates the second daisy chain device according to execution close beta operation of the present disclosure.

Figure 23 illustrates the JTAG/1149.1 bus controller.

Figure 24 illustrates the JTAG/1149.1 bus that the control of CMD circuit is arranged according to expansion of the present disclosure.

Figure 25 illustrates the example implementation according to jtag controller CMD circuit of the present disclosure.

Figure 26 illustrates according to of the present disclosure can being connected to via two-port router has additional Capture and the TSM of Update input or CSU or the CS circuit of CMD circuit.

Figure 27 illustrates the CMD circuit according to the Capture of having input of the present disclosure.

Figure 28 illustrates the CMD circuit according to the Capture of having of the present disclosure and Update input.

Figure 29 A illustrates according to expansion of the present disclosure the IEEE1149.1TAP that receives the CMD circuit of cmd signal from TSM.

Figure 29 B illustrates the gating circuit that cmd signal is outputed to the CMD circuit when TSM is in the ExitlDR state according to of the present disclosure.

Figure 30 illustrates according to TSM of the present disclosure cmd signal is outputed to the CMD circuit to carry out the sequential chart of CSOP, CSUOP and B2BCSOP operation.

Figure 31 illustrates the data register of controlling according to the CMD circuit by receiving the cmd signal that is used for TSM of the present disclosure.

Figure 32 illustrates according to of the present disclosure and is being used for the circuit of clocking in the ClockDR of TSM output during some TSM state.

Figure 33 illustrate according to of the present disclosure can be connected to have via two-port router additional catch and upgrade the TSM of input or CSU or the CS circuit of CMD circuit.

Figure 34 A illustrates according to expansion of the present disclosure to be had from the IEEE1149.1TAP of programmable switch (PSW) circuit of TSM reception control signal.

Figure 34 B illustrates the gating circuit that control signal is outputed to PSW when TSM is in ExitlDR or PauseDR state according to of the present disclosure.

Figure 35 illustrates according to TSM of the present disclosure control signal is outputed to the PSW circuit to carry out the sequential chart of CSOP, CSUOP and B2BCSOP operation.

Figure 36 illustrates the data register of being controlled by the PSW from the TSM reception control signal according to of the present disclosure.

Figure 37 illustrates according to of the present disclosure can being connected to via two-port router has additional Capture and the TSM of Update input or CSU or the CS circuit of PSW circuit.

Figure 38 illustrates the PSW circuit according to the Capture of having of the present disclosure and Update input.

Figure 39 illustrates the IEEE1149.1TAP that TSM ExitlDR and PauseDR state detection circuit and two-port router are arranged according to expansion of the present disclosure.

Figure 40 illustrates the IEEE1149.1TAP that TSM ExitlDR and PauseDR state detection circuit, multiplexer and two-port router are arranged according to expansion of the present disclosure.

Figure 41 illustrates CSU or the CS circuit that can be connected to the DRC multiplexer via two-port router according to of the present disclosure.

Embodiment

Fig. 1 illustrates the example TAP framework 100 of prior art, and it comprises TAP state machine (TSM) 102, order register 104, data register 106, data register control (DRC) signal router 108 and TDO multiplexer (MX) 110.Thereby TSM is by state of operation shown in Figure 3; (1) TAP is placed in the test logic reset mode, (2) are placed in the operation test/ldle with TAP, and (3) carry out instruction register scan, perhaps (4) executing data register scan operation.Order register output data register enables (DRE) signal, and this signal is selected the drc signal of TSM to arrive through router and wanted accessed data register.Fig. 2 illustrates router one 08, and it comprises routing circuit 202, and these routing circuits 202 are connected to the DRC output of TSM the DRC input of data register (DR) 106.In case connect, can be by the TAP state machine be selected data register (SelectDR), capture-data register (CaptureDR), shifted data register (ShiftDR), is withdrawed from 1 data register (ExitlDR) and upgrade between data register (UpdateDR) state and change at it, export (TDO) visit data register from test data input (TDI) to test data with this, as shown in the TSM constitutional diagram of the TAP of Fig. 3.

Fig. 4 illustrates asynchronous (CSU) data register 402 of catching, be shifted and upgrade, and it is connected to TSM102 via routing circuit 108.In other routing circuit examples of this routing circuit example and back, routing circuit 108 comprises gating circuit, so that during DRE instruction input reference, this gating circuit allows TSM to control data register 402 when selecting data register 402.Asynchronously mean that data register provides sequential by the gate ClockDR of TSM output.CSU categorical data register, for example the IEEE1149.1 boundary scan register, be well-known.As all known in this area, in response to the DRE input, the gating circuit of router circuit is connected to data register ClockDR, ShiftDR and UpdateDR input with ClockDR, ShiftDR and the UpdateDR output of TSM.In case connect, TSM is by its SelectDR, CaptureDR, ShiftDR, ExitlDR and the conversion of UpdateDR state of Fig. 3, thus the service data register.When data register not access by TSM, the gating circuit of routing circuit 108 is set by the DRE input, ClockDR, the ShiftDR of data register and UpdateDR are inputted be placed in inactive state.

Fig. 5 illustrates the synchronous CSU data register 502 that is connected to TSM102 via routing circuit 108.Mean that synchronously data register provides sequential by tck signal.Synchronous operation needs the scanning element of data register that hold mode is provided, and makes when data register do not carrying out when catching (Capture), be shifted (Shift) or upgrade (Update) operation, keeps its current state.Capture signal designation TSM is in the CaptureDR state of Fig. 3, and Shift signal designation TSM is in the ShiftDR state of Fig. 3, and Update signal designation TSM is in the UpdateDR state of Fig. 3.In response to DRE input, routing circuit is connected to catching (Capture), displacement (Shift) and upgrading (Update) State-output of TSM data register and catches (Capture), displacement (Shift) and renewal (Update) and input.In case connect, TSM is by the conversion of its SelectDR, CaptureDR, ShiftDR, ExitlDR and the UpdateDR state of Fig. 3, thus the service data register.When data register not access by TSM, the gating circuit of routing circuit 108 is set by the DRE input, Capture, the Shift of data register and Update are inputted be placed in inactive state.

Fig. 6 illustrates asynchronous (CS) data register 602 of catching and be shifted, and it is connected to TSM102 via routing circuit 108.CS categorical data register, for example inner scanning path register, be well-known.In response to the DRE input, routing circuit is connected to data register ClockDR and ShiftDR input with ClockDR and the ShifDR output of TSM.In case connect, TSM is by the conversion of its SelectDR, CaptureDR, ShiftDR, ExitlDR and the UpdateDR state of Fig. 3, thus the service data register.When data register not access by TSM, the gating circuit of routing circuit 108 is set by the DRE input, the ClockDR of data register and ShiftDR are inputted be placed in inactive state.

Fig. 7 illustrates synchronous CS data register 702, and it is connected to TSM102 via routing circuit 108.In response to the DRE input, routing circuit is connected to data register Capture and Shift input with Capture and the Shift State-output of TSM.In case connect, TSM is by the conversion of its SelectDR, CaptureDR, ShiftDR, ExitlDR and the UpdateDR state of Fig. 3, thus the service data register.When data register not access by TSM, the gating circuit of routing circuit 108 is set by the DRE input, the Capture of data register and Shift are inputted be placed in inactive state.

The TSM state conversion of the CSU scan cycle of Fig. 4 and Fig. 5 has illustrated problematic dead state SelectDR and ExitlDR in dashed rectangle.When upgrading operation and occur in the UpdateDR state, need to spend 2.5 TCK catch operation in the CaptureDR state before.This has stoped Geng Xin ﹠amp at full speed; Catch scan operation.The TSM state conversion of the CS scan cycle of Fig. 6 and Fig. 7 has illustrated problematic dead state SelectDR, ExitlDR and UpdateDR in dashed rectangle.When last shifting function occurs in the ShiftDR state, need to spend 4 TCK catch operation in the CaptureDR state before.This has stoped at full speed ﹠amp at full speed; Catch scan operation.

The prevention full speed CSU of Fig. 4-7 and the dead state of CS scan operation are well-known in the industry.Having proposed many solutions addresses this problem.The following describes and with reference to some early stage solutions.

Solution 1 is the 18th chapter of the Maunder that publishes of IEEE Computer Society Press1990 " The Test Access Port and Boundary Scan Architecture ".This solution has defined the ScanTest instruction, and it can be loaded into the TAP order register, and this register TSM state assignment " reprogramming " can occur catch at full speed the situation of operation after in the end shifting function.This solution has been eliminated the dead state in the CS scan operation, but does not eliminate the dead state in the CSU scan operation.Equally, this solution only is applied to independently device detection, and namely it can not be used in when this device links with other device chrysanthemums.

Solution 2 is papers " Built-In-Test Using Boundary Scan " of Whetsel, ATE﹠amp; Instrumentation Conference, 1989, pg15-22.This solution has defined BIST and DelayTest instruction, and it can be loaded into the TAP order register and carry out in the operation test/ldle, upgrades at full speed and catches operation thereby carry out.This solution does not solve the dead state problem in CSU and CS scan operation.

Solution 3 is papers " Early Capture for Boundary Scan Timing Measurements " of Lofstrom, IEEE International Test Conference, 1996.This solution has defined the EarlyCapture instruction, and it can be loaded into the TAP order register, operates the clock of catching that can be employed afterwards thereby allow tms signal to be used as renewal.This solution provides to be upgraded at full speed and catches operation, but it does not eliminate the needs that solve dead state.It is also only useful to the CSU scan operation, rather than the CS scan operation.Solution 4 is IEEE Standard1149.6, " A Standard for Boundary Scan Testing of Advanced Digital Networks ".This solution is based on new standard (IEEE1149.6), this standard definition new instruction (ExtestPulse﹠amp; ExtestTrain), these instructions allow to carry out in the operation test/ldle and upgrade at full speed and catch operation.Similar solutions 2, this solution do not solve the dead state problem in CSU and CS scan operation.

First disclosed solution-Fig. 8-33

First solution of the problematic dead state of elimination Fig. 4-7 described in the disclosure relates to command circuit and two-port router expansion TAP100.Command circuit and two-port router can be worked as when TSM102 is in the ShiftDR state of Fig. 3 and operated, and upgrade at full speed and catch operation thereby the CSU data register is carried out, and the CS data register is carried out at full speed being shifted and catching operation.

Fig. 8 illustrates TAP800, and it has expanded order (CMD) circuit 802 and two-port router 804, and in addition, TAP800 is identical with the TAP100 of Fig. 1.CMD circuit 802 has input and the DRC output that is connected to TCK, TMS, DRE.A port of two-port router 804 is connected to the DRC output of CMD circuit, and another port is connected to the DRC output of TSM.DRE signal from order register enables or forbids the CMD circuit.The DRE signal is also controlled two-port router, makes router can foregoingly be controlled by TSM102 to the DRC output of data register 106, is perhaps controlled by CMD circuit 804.

Fig. 9 illustrates example two-port router 804, it comprises routing circuit 902, input in response to DRE, routing circuit 902 will be connected to the DRC input of selected data register 106 from the DRC output of TSM, perhaps the DRC output of CMD circuit is connected to the DRC input of selected data register 106.If data register is connected to the DRC output of TSM, it can be accessed, in order to carry out CSU or CS scan operation by TSM control, as previously mentioned.If data register is connected to the DRC output of CMD circuit, it can be accessed, in order to carry out CSU or CS scan operation by the control of CMD circuit.

Figure 10 illustrates the sequential of using the CMD circuit to carry out CSU scan operation (CSUOP) 1002 or CS scan operation (CSOP) 1004.When the CMD circuit is being used to the visit data register, TSM will be transformed into ShiftDR state 1006 and remain on this state.In the ShiftDR state, data register is displaced to TDO with data from TDI.Proper time during being shifted, cmd signal 1008 is imported into the CMD circuit via tms signal at the falling edge of TCK.Between the cmd signal input, be imported into CMD circuit via TMS at the falling edge of TCK without operation (NOP) signal 1010.During CMD access control data register, TSM continues the normal TMS input 1012 of rising edge place's reception at TCK, thereby TSM is maintained the ShiftDR state.When the scan operation end that the CMD circuit is controlled, TSM will receive the TMS input, leave the ShiftDR state with conversion, thereby stop the data register accesses operation.

As shown in Figure 10, if CSU categorical data register just accessed, will be carried out CSUOP in response to the cmd signal input.Carry out after an in the end displacement (displacement N) operation of CSUOP and upgrade operation 1014, carry out and catch operation 1016, then restart shifting function.When each cmd signal is transfused on TMS, repeat this renewal, catch and the displacement order.Due to when the CMD circuit is controlled the CSU data register, TSM remains on the ShiftDR state, so there is no dead state in the CSUOP of Figure 10 circulation.Equally as shown in Figure 10, if CS categorical data register just accessed, will be carried out CSOP in response to the cmd signal input.Carry out after an in the end displacement (displacement N) operation of CSOP and catch operation 1018, then restart shifting function.When each cmd signal is transfused on TMS, repeats this and catch and the displacement order.Due to when the CMD circuit is controlled the CS data register, TSM remains on the ShiftDR state, so there is no dead state in the CSOP of Figure 10 circulation.

The asynchronous CSU data register 402 that Figure 11 illustrates Fig. 4 is connected to TSM and CMD circuit via example two-port router 804.DRE input control two-port router, thus allow described in data register such as Fig. 4 by the TSM access, perhaps as being accessed by the CMD circuit described in Figure 10.CMD circuit in this example is only two FF that are connected in series, and they are at the cmd signal of the falling edge of TCK input from TMS.Two-port router 804 in this example is only multiplexer and the door that connects as shown in the figure, and they are by the DRE input control from order register.When data register will be controlled by TSM, the DRE input will be routed to ClockDR, ShiftDR and the UpdateDR input of data register from ClockDR, ShiftDR and the UpdateDR output of TSM by two-port router.When data register will be controlled by the CMD circuit, the DRE input will catching (C) and upgrade (U) signal and input by ClockDR, ShiftDR and the UpdateDR that two-port router is routed to data register from the ClockDR signal of TSM from the CMD circuit.ClockDR output from TSM will move, because TSM will be in the ShiftDR state.It is ClockDR, ShiftDR from TSM and UpdateDR input that the first port of this example two-port router is defined as.The second port of this example two-port router is defined as to be from the catching of CMD circuit (C) and to upgrade (U) input and from the ClockDR input of TSM.

By the CMD circuit during the visit, a FF inputs from the cmd signal of TMS and will upgrade (U) signal and outputs to two-port router, and this two-port router outputs to data register with the UpdateDR signal, data register is carried out upgraded operation.Be gate from renewal (U) signal of CMD circuit with ClockDR signal from TSM, be in generation refresh clock pulse in the UpdateDR input of data register with the rising edge at TCK.Then cmd signal is displaced in the 2nd FF, the 2nd FF will catch (C) signal and output to two-port router, this two-port router outputs to data register with the logic level on the ShiftDR signal, make data register catch operation in next rising edge place's execution of ClockDR, this is driven by TCK.This renewal (U) and to catch (C) signal be stable in rising edge ClockDR operating period is because they are in the falling edge of TCK is deposited at FF.When each cmd signal is imported into the CMD circuit, repeats this renewal and catch sequence of operation.Although this example two-port router is in rising edge place's generation refresh clock pulse of ClockDR, if expectation, another example two-port router can produce the refresh clock pulse at the falling edge of ClockDR.

Although not shown in Figure 11, but as shown in Figure 9, the FF of the CMD circuit of this CMD examples of circuits and other CMD examples of circuits subsequently will be by the DRE input initialization when data register test access operation beginning, making renewal (U) and catching (C) output is not effectively, until receive cmd signal.

The synchronous CSU data register 502 that Figure 12 illustrates Fig. 5 is connected to TSM102 and CMD circuit 802 via example two-port router 804.DRE input control two-port router, thus allow data register as described in Figure 5 by the TSM access, perhaps accessed by the CMD circuit as described in Figure 10.Data register provides clock by free-running operation TCK.

Two-port router 804 in this example is only multiplexer and the door that connects as shown in the figure, and they are by the DRE input control from order register.When data register will be controlled by TSM, the DRE input will be routed to catching (Capture), displacement (Shift) and upgrading (Update) input of data register by two-port router from catch (Capture), displacement (Shift) and renewal (Update) State-output of TSM.When TSM is in the CaptureDR state, make the trapped state signal effective, when TSM is in the ShiftDR state, make the displaced condition signal effective, when TSM is in the UpdateDR state, make the update mode signal effective.When data register will be controlled by the CMD circuit, DRE input will from the CMD circuit catch (C) and renewal (U) signal is routed to catching, be shifted and upgrading input of data register by two-port router.From the catching of TSM (C) input with data register catch and the input that is shifted is configured such that the state of data register shift or capture-data.In this example, if it is low catching (C), to data register catch and be shifted the input be set to respectively low and high, thereby make data register that data are displaced to TDO from TDI, and if it is high catching (C), to data register catch and the input that is shifted be set to respectively high and low, thereby make the data register capture-data.It is from the catching of TSM, displacement and update mode output that the first port of this example two-port router is defined as.It is catching (C) and upgrading (U) input from the CMD circuit that the second port of this example two-port router is defined as.By the CMD circuit during the visit, a FF inputs from the cmd signal of TMS and will upgrade (U) signal and outputs to two-port router, and this two-port router output update signal is upgraded operation thereby data register is carried out.Then, cmd signal is displaced in the 2nd FF, and the 2nd FF will catch (C) signal and output to two-port router, and this router output is caught and shift signal, catches operation thereby data register is carried out.Catching, be shifted and upgrading data register of this example operates the rising edge place that occurs in free-running operation TCK.If expectation, by arriving simply the TCK input inversion of refresh circuit, the refresh circuit in data register can be designed as in response to the update signal on the negative edge of TCK and operates.When each cmd signal is imported into the CMD circuit, repeats this renewal and catch sequence of operation.

The asynchronous CS data register 602 that Figure 13 illustrates Fig. 6 is connected to TSM102 and CMD circuit 802 via two-port router 804.The two-port router of this example comprises multiplexer and the door that connects as shown in the figure.The multiplexer of DRE input control two-port router and door, thus allow data register as described in Figure 6 by the TSM access, perhaps accessed by the CMD circuit as described in Figure 10.The first port of two-port router comprises from the ClockDR of TSM and ShiftDR output.The second port of two-port router comprises from the catching of CMD circuit (C) output with from the ClockDR output of TSM.CMD circuit in this example is only FF, and its falling edge at TCK is inputted the cmd signal from TMS.By the CMD circuit during the visit, FF inputs from the cmd signal of TMS and will catch (C) signal and outputs to two-port router, two-port router is via the logic state on multiplexer and door output ShiftDR signal, catches operation thereby data register is carried out at the rising edge place from the ClockDR of TSM.The ClockDR signal is effectively, because TSM is in the ShiftDR state.After catching operation, the ShiftDR signal turns back to its previous state, thereby restarts this shifting function at the next rising edge place of ClockDR.When each cmd signal is imported into the CMD circuit, repeats this and catch operation.

The synchronous CS data register 702 that Figure 14 illustrates Fig. 7 is connected to TSM102 and the CMD circuit 802 of Figure 12 via two-port router.The two-port router of this example comprises multiplexer and the door that connects as shown in the figure.The multiplexer of DRE input control two-port router and door, thus allow data register as described in Figure 7 by the TSM access, perhaps accessed by the CMD circuit as described in Figure 10.The first port of two-port router comprises from catching with displaced condition of TSM to be exported.The second port of two-port router comprises that catch (C) from the CMD circuit exports.This data register provides clock by the free-running operation tck signal.DRE input control two-port router, thus allow data register as described in Figure 7 by the TSM access, perhaps accessed by the CMD circuit as described in Figure 10.By the CMD circuit during the visit, FF inputs from the cmd signal of TMS and will catch (C) signal and outputs to two-port router, this two-port router is exported, will arrive data register catch and the input that is shifted is configured such that data register carries out the state of catching operation at the rising edge place of TCK.After this catches operation, catch with shift signal and turn back to its previous state, thereby restart shifting function at the next rising edge place of TCK.When each cmd signal is imported into the CMD circuit, repeat to catch operation.

The asynchronous CS data register 602 that Figure 15 illustrates Fig. 6 is connected to TSM102 and CMD circuit 802 via the two-port router 804 of Figure 13.As described in Figure 13, DRE input control two-port router, thus allow data register as described in Figure 6 by the TSM access, perhaps accessed by the CMD circuit.In this example, the CMD circuit is designed to control data register execution back-to-back (back to back) and catches operation.The CMD circuit of this example comprises the first and second FF that are connected in series.The output of FF is imported into door, for example rejection gate.The output of door is imported into two-port router.In response to the CMD input signal from TMS, (C) signal is caught in a FF output first of CMD circuit, and then cmd signal is displaced in the 2nd FF of CMD circuit, CMD circuit output the second lock-on signal.Both are input to two-port router to the CMD circuit via goalkeeper's the first and second lock-on signals (C).Catch (C) signal in response to first, the ShiftDR input that two-port router will arrive data register is configured such that data register carries out the first state of catching operation at the rising edge place of ClockDR.Catch (C) signal in response to second, two-port router is kept the trapped state in the ShiftDR input, catches operation thereby make data register carry out second at the next rising edge place of ClockDR.Back-to-back catch operation after, turn back to its previous state to the ShiftDR of data register input, thereby restart shifting function.

Although Fig. 8-15 illustrate the various types of simple data register of being controlled by TSM or CMD circuit, these data registers form the structure module of the more complicated test structure in device usually.These more complicated test structures also can be controlled by TSM or CMD circuit, described in following Figure 16-17.

Equally, although Fig. 8-15 illustrate the arranged in series that the CMD circuit is single trigger or two triggers, the CMD circuit can with many different modes designs, comprise that the CMD circuit is designed to state machine.

Figure 16 illustrates the single input of the known type in device and the simple examples of single output test compression framework 1602.This framework comprises decompressor (D) circuit, parallel C S categorical data register (DR) and compressor reducer (C) circuit.Decompressor is controlled by the DRC of two-port router output, thus input from the excited data of the compression of TDI, this excited data of decompress(ion) and the excited data that decompresses is outputed to the CS data register.Compressor reducer is controlled by the DRC output of two-port router, thereby input is compressed this response data from the response data of CS data register, and the response data of compression is outputed in TDO output.The CS data register is controlled by the DRC output of two-port router, catches and shifting function thereby carry out.DRE input control two-port router, thus allow test compression framework such as Fig. 6 or 7 described DRC outputs by TSM to control, and perhaps the DRC output by the CMD circuit as described in Figure 13 and 14 is controlled.

Figure 17 illustrates a plurality of inputs of the known type in device and the simple examples of a plurality of output test compression frameworks 1702.Identical with described in Figure 16 of the structure of this framework and operation be used to input the excited data of compression except a plurality of TDI inputs, and a plurality of TDO output is used to the response data of output squeezing.A plurality of output test compression of a plurality of inputs framework can as described in Figure 16 by TSM or CMD circuit selective control.

Figure 18 is illustrated in the simple examples of IEEE1500 core shell framework 1802 in device, and this framework is connected to the DRC output of two-port router.This framework comprises shell boundary register (WBR) and parallel C S categorical data register (DR).Although not shown, this framework also comprises the order register of controlling its test mode of operation.

The shell boundary register mainly is used to provide interconnecting test between a plurality of core shell frameworks in device.It may be implemented as CSU or CS categorical data register.During interconnecting test, the shell boundary register passes through the shell boundary register by the DRC output control of two-port router thereby via shell serial input (WSI) and shell serial output (WSO), data are shifted, and then carries out renewal and catches operation.In this example, WSI is illustrated as being connected to TDI, and WSO is illustrated as being connected to TDO.If the DRE input selection TSM to two-port router controls interconnecting test, TSM will cycle through the data register scan state, thus the output drc signal, to control the shell boundary register.If the DRE input selection CMD circuit to two-port router is controlled interconnecting test, TSM will change and keep the ShiftDR state, the drc signal of CMD circuit output simultaneously, thus control the shell boundary register.

Parallel C S data register is used for carrying out the parallel scan test of core logic.At the parallel scan test period, control the CS data register by the DRC output of two-port router, thereby via the parallel input of shell (WPI) and shell parallel output (WPO), data are shifted by the CS data register, then carry out and catch operation.If the DRE input selection TSM to two-port router controls the parallel scan test, TSM will cycle through the data register scan state, thus the output drc signal, to control parallel C S data register.If the DRE input selection CMD circuit to two-port router is controlled interconnecting test, TSM will change and keep the ShiftDR state, the drc signal of CMD circuit output simultaneously, thus control parallel C S data register.

Usually with the device detection framework shown in TSM control chart 16-18, problematic dead state can occur during scan operation.Control these dead states during test structure has advantageously been eliminated scan operation with the CMD circuit.

How can be for improvement of scanning or the sweep compression test of device although the example of Figure 16-18 shows CMD circuit and two-port router, the CMD circuit also can be used to improve accesses the scanning of the flush type circuit of the other types that are connected with the TAP interface in device.Two this flush type circuits are described below.

Figure 19 illustrates and arranges 1900, and it comprises the addressable R/W circuit 1902 that is connected to R/W data register 1904, R/W data register 1904 via two-port router 804 by TSM102 or by CMD circuit 802 selective control.The R/W circuit can be memory circuitry, test circuit, debug circuit or follow the trail of circuit.The R/W circuit is from data register receiver address (ADDRESS) input and R/W control inputs, thereby allow to connect via the data between R/W circuit and data register (DATA) bus, data are write addressed location in the R/W circuit, and/or from the addressed location reading out data.

When access to the R/W circuit is controlled in expectation by TSM, DRE input control two-port router will be connected to from the DRC output of TSM the DRC input of data register.In case connect, TSM is transformed into the ShiftDR state, thereby address, data and R/W control bit are moved into and shift out data register.If the R/W control bit arranges for write operation, when TSM was transformed into the UpdateDR state, the data in data register were written to the addressed location of R/W circuit.If the R/W control bit is for reading setting, when TSM was transformed into the CaptureDR state, the data in the addressed location of R/W circuit were loaded into data register.If the R/W control bit arranges for reading with write operation, read in the addressed location of CaptureDR state from the R/W circuit, and write in the addressed location of UpdateDR state to the R/W circuit.

When access to the R/W circuit was controlled in expectation by the CMD circuit, DRE input control two-port router was connected to the DRC output of CMD circuit the DRC input of data register.In case connect, TSM is transformed into the ShiftDR state and keeps this state, thereby address, data and R/W control bit are moved into and shift out data register.Proper time during shifting function, the CMD input is imported into the CMD circuit, thereby makes the CMD circuit that drc signal is outputed to two-port router.If the R/W control bit arranges for write operation, in response to the drc signal of CMD circuit, the data in data register are written to addressed location.If the R/W control bit arranges for read operation, in response to the drc signal of CMD circuit, the data in addressed location are loaded into data register.If the R/W control bit arranges for reading with write operation, in response to the drc signal of CMD circuit, read and write.

The advantage of the R/W operation of being controlled by the CMD circuit is, TSM does not need conversion to leave the ShiftDR state to read and/or write operation with execution.Read and/or write operation is when address, data and RW control bit are moved into continuously and shift out data register, carried out by the CMD input.If this data register is 50 bit long, read and/or write operation can by the order for to carry out after every the 50 shifting function.

Figure 20 illustrates the instrument data register framework 2002 by ieee standard P1687 exploitation, and it is used for the embedded instrumentation of access device.Instrument data register framework comprises segmentation insertion bit (SIB) element, and it can be controlled by scan operation, thereby connects in the path between TDI and TDO or the disconnection instrument.This instrument data register framework imitates by United States Patent (USP) 4,872, the operation of certainly controlling the variable-length scanning pattern that at first Whetsel describes in 169.This instrument data register framework is embodied in and comprises the DRC control inputs, thereby allows it be connected to from the DRC output of TSM and controlled by DRC output.In this example, CMD circuit and two-port router are increased, and also can how to be controlled by the CMD circuit so that the instrument data register to be shown.

When access to the instrument data register is controlled in expectation by TSM, DRE input control two-port router will be connected to from the DRC output of TSM the DRC input of data register.In case connect, TSM is transformed into the ShiftDR state, thereby data are moved into and shift out the instrument data register.Be connected in data register if SIB is set to the instrument that it is related, can at the UpdateDR state, data be write instrument with for the described identical mode of the R/W circuit of Figure 19, and at the CaptureDR state from the instrument reading out data.

When access to the instrument data register was controlled in expectation by the CMD circuit, DRE input control two-port router was connected to the DRC output of CMD circuit the DRC input of data register.In case connect, TSM is transformed into the ShiftDR state, thereby data are moved into and shift out data register.If being set to the instrument that it is related, SIB is connected in data register, can be with for the described identical mode of the R/W circuit of Figure 19, in response to the CMD input to the CMD circuit, data are write instrument and from the instrument reading out data.

The advantage of the instrument accessing operation of being controlled by the CMD circuit is with identical by the advantage of the R/W circuit accessing operation of CMD circuit control, that is to say, TSM does not need conversion to leave the ShiftDR state and read and/or write operation with execution, because when data are moved into and shift out the instrument data register continuously, read with write operation and carried out by the CMD input.

The operation of improvement board level test

Figure 21 illustrates the layout 2102 of the daisy chain device that is connected to jtag controller.This device can be IC on plate or the flush type circuit in IC.Each device has can order TAP(CTAP), namely each device TAP comprises CMD circuit of the present disclosure and two-port router.In this example, device CTAP has been loaded the IEEE1149.1 interconnecting test boundary scan instructions that CMD controls, and it makes it possible to carry out full speed and upgrades and catch operation in interconnection.As finding out, carry out in response to the CMD input from TMS the boundary scan testing operation of upgrading, catch and be shifted, as previously mentioned in sequential chart.In this example, upgrade the rising edge place's generation that operates in TCK, and catch the rising edge place's generation subsequently that operates in TCK.This upgrades the interconnecting test boundary scan and catches and operates in interior generation of a TCK cycle, and conventional interconnecting test boundary scan upgrades and catch generation in the two and half TCK cycles that operated in.

If expectation, by the design two-port router, this renewals operation can be delayed to its falling edge at TCK and occur, and catches the rising edge place subsequently that operates in TCK and occur, thus make renewal and catch between only have the TCK cycle half.This renewal and the sequential of catching between operation are tightened up the CSU data register that can be applied to any type.

During the full speed boundary scan testing, input normal tms signal at the rising edge place of TCK, thereby CTAP is maintained the ShiftDR state.CTAP also can be set to use the conversion of TSM state to carry out the conventional interconnecting test boundary scan testing of interconnection.Yet this test is not upgrade and catch test at full speed, because can introduce the TSM dead state.

Developed ieee standard 1149.6 with provide can test component between the boundary scan testing of AC coupled interconnection.1149.6 need, because whole AC coupled interconnections can not be fully tested in 1149.1 interconnecting test instructions, this is to have two and half TCK to postpone between operation owing to upgrading and catching.Due to the interconnecting test operation of being controlled by CMD as above can one or even half TCK upgrade in the cycle and catch data in interconnection, so it makes it possible to test the incompetent AC coupled interconnection of test of Application standard 1149.1 interconnecting test instructions.

Figure 22 illustrates the layout 2202 of the daisy chain device that is connected to jtag controller.These devices can be IC on plate or the flush type circuit in IC.In this example, the expectation access is arranged in CS or the CSU type circuit of intermediary device.CS or CSU circuit can be foregoing any types of only using TDI and TDO to transmit data.In order to set up the access to middle device, the device of front and the device of back have been loaded the IEEE1149.1 instruction, be 1149.1Bypass, Clamp or HighZ instruction, its bypass of these Instruction Selection (BYP) register, and intermediary device is loaded the CS that selects expectation or CSU type circuit so that the instruction of access.

If use normal JTAG scan operation to carry out access to CS or the CSU circuit of middle device, the instruction meeting that is loaded in intermediary device is connected to CS or CSU circuit with the TSM of device.Carry out routine data registers capture, displacement and renewal operation by jtag controller, carry out access to middle device with this.Catching operating period, bypass register is load logic 0 conformably, and during next shifting function, the intermediary device circuit loads the data that will output to controller.Then shifting function is carried out and is upgraded operation, thereby upgrades the data that have been displaced in intermediate circuit, supposes that intermediate circuit is CSU type circuit.During each data register scan operations, jtag controller must be with the bypass register of data displacement by the device of bypass register, intermediary device circuit and the back of the device of front.If the device of 50 fronts is arranged, the device of 50 back and intermediary device circuit sweep length are 50 bits, and each data register scan circulation will be 150 bit long.If need a large amount of scan cycle visit the intermediary device circuit, must be repeatedly with the data displacement bypass register of the device of the device by the front and back, this can waste a large amount of time.

If use the execution of CMD circuit to the access of CS or the CSU circuit of middle device, the meaning is that the TAP of intermediate circuit has CMD circuit of the present disclosure and two-port router with expansion, and the instruction meeting that is loaded in intermediary device is connected to CS or CSU circuit with the CMD circuit of device.By jtag controller, whole devices are placed in the ShiftDR state, with data from TDI to the TDO continuous displacement by device, carry out access to middle device circuitry with this.Appropriate time during being shifted, jtag controller are input to cmd signal the CMD circuit of intermediary device via tms signal.In response to the CMD input, the CS circuit is caught operation with execution, then restarts shifted data, as shown in the CSOP sequential of Figure 22.In response to the CMD input, the CSU circuit will be carried out and upgrade operation, be to catch operation subsequently, then restart shifted data, as shown in the CSUOP sequential of Figure 22.Because the bypass register of the device of the device of front and back does not respond the CMD input, so they are operating as the streamline bit simply, data are displaced to intermediary device and get back to jtag controller from middle device displacement from jtag controller.

To middle device during the visit, the unique time that must pass bypass register and waste, it is once the beginning in access, when from the bypass register of the device of the data stuffing front of jtag controller, once the end in access, when the bypass register from the data device from behind of intermediary device is flushed into jtag controller.Reuse the device of the device of 50 fronts of example, 50 back and the intermediary device circuit length of 50 bits, extend 50 bits displacements when the access of middle device only is extended 50 bits displacements and the end in access when the beginning of access.

Make jtag controller be suitable for CMD output

The disclosure uses the method for tms signal input CMD need to revise traditional jtag controller.There are jtag controller, the i.e. jtag controller of software control and the jtag controller of hardware controls of two kinds of fundamental types.The jtag controller of software control uses software operation TMS, TCK, TDI and TDO signal with computer printer port simply.The jtag controller of hardware controls uses the jtag interface circuit to control TMS, TCK, TDI and TDO signal.By the software of change control parallel port simply, realized making the jtag controller of software control to be suitable for providing cmd signal on TMS.It is more difficult making the jtag controller of hardware controls be suitable for providing cmd signal on TMS, because it need to revise hardware.Thereby a kind of jtag controller of revising hardware controls provides cmd signal on TMS plain mode is described below.

Figure 23 illustrates the jtag controller 2302 that exemplary hardware is controlled, and it comprises computing machine 2306 and jtag interface circuit 2304.The jtag interface circuit has for the TMS control circuit of output tms signal, is used for the TCK control circuit of output tck signal, the TDO storer that is used for exporting the TDI storer of TDI signal and is used for input TDO signal.The computing machine execution being read and writing the jtag interface circuit, thereby makes jtag interface circuit operation TMS, TCK, TDI and TDO signal.

Figure 24 illustrates exemplary arrangement 2402, and how its jtag controller that Figure 23 is shown can expand CMD circuit 2404 and multiplexer 2406, thereby optionally allows it to provide on TMS or cmd signal is not provided.The CMD circuit has computer interface, the input of ShiftDR state, TCK input, enables (ENABLE) output and CMD output.TCK is input as the CMD circuit sequential is provided, and the input of ShiftDR state enables the operation of CMD circuit.Multiplexer have be connected to enabling of enabling to export input, be connected to the data input of CMD output, be connected to TMS output the data input, be connected to the selection input of TCK output and be connected to the output of TMS output.When jtag controller layout 2402 is set to not provide cmd signal on TMS, enable signal will be set to make multiplexer only to export tms signal, thereby copy the operation of traditional jtag controller of Figure 23.When jtag controller layout 2402 is set to provide cmd signal on TMS, enable signal will be set to make multiplexer in response to inputting and replace between output tms signal and cmd signal from the selection (SELECT) of tck signal.

Figure 25 illustrates the example implementation of the CMD circuit 2404 of Figure 24, and it comprises register 2502 sum counters 2504.Register contains shift count bit field and enable bit.When the jtag controller of Figure 24 arranged that will carry out normal JTAG operates, the computer installation enable bit made multiplexer only export tms signal.When jtag controller layout 2402 will be carried out the CMD operation, computing machine was written to register with shift count, and enable bit is set, and makes multiplexer alternately export TMS and cmd signal in response to selecting signal, and shift count is loaded in counter.Shift count is set to the bit length of the data register that equals accessing.In CMD operating period, the input of ShiftDR state be set to make counter can be when each rising edge TCK shifting function counting once.When shift count expired, counter output counting was completed (CC) signal, and this signal cmd signal is set to height.Cmd signal is output on TMS via multiplexer, to trigger the CMD operation in target devices.As shown in the sequential chart of Figure 25, the NOP signal is output on TMS, until cmd signal occurs.The CC signal also loads (LD) with shift count and enters in counter, is used for next CMD shift cycle.Repetitive operation until the test complete.When in the cmd signal output mode, the jtag controller of Figure 24 arrange 2402 before the TCK rising edge for tms signal provides the TCK setup times half, and provided the TCK setup times half for cmd signal before the TCK negative edge.

Figure 26 illustrates the circuit block 2602 that contains one or more CSU and/or CS data register element.Circuit block 2602 can be the circuit of any type, includes but not limited to test circuit, debug circuit, tracking circuit, artificial circuit, read/write circuits and equipment circuit.Some examples of this class circuit have been described with reference to figure 16-20.Circuit block is controlled by the DRC output of two-port router 804, catches and shifting function thereby carry out, and perhaps catches, is shifted and upgrade operation.DRE input control two-port router, thus allow circuit block 2602 to be controlled by the DRC output of TSM102 or CMD circuit 2604, as previously mentioned.The CMD circuit 2604 of this example has the extra input for lock-on signal and update signal.In response to the DRE input, can select to catch with update signal to control the DRC output of CMD circuit 2604.During the device manufacturing test of wafer scale or package level, may expect to allow external test to use and catch the DRC output of directly controlling the CMD circuit with update signal, these signals are addressable at test period on device pin.Allow tester via catching the DRC output of controlling the CMD circuit with update signal, this makes it possible to control more flexibly the DRC output of CMD circuit.Equally, it allows the TMS input of TSM only need input tms signal, rather than TMS and cmd signal, and this has simplified the tester interface to TAP102.Further, only need in TMS input the input tms signal that TCK can be moved with clock frequency faster, because can apply better setting and retention time on tms signal.Catch test period with update signal in use, velometer is transformed into the ShiftDR state with TAP, thereby via TDI and TDO signal, data are moved into and shift out circuit block 2602, and the appropriate time during being shifted, operation is caught with update signal to realize test circuit block 2602.

Figure 27 illustrates an example implementation of CMD circuit 2604, and it comprises previous described CMD circuit 804 and the multiplexer 2702 of Figure 13 and Figure 14.When CMD circuit 2604 is set to allow 804 controls of CMD circuit to catch (C) output, the DRE input will be set the output that multiplexer will be coupled to CMD circuit 804 will catch (C) output, the ﹠amp thereby the full speed of permission described in Figure 13 and 14 is shifted; Catch operation.When CMD circuit 2604 is set to allow lock-on signal control to catch (C) output, the DRE input will be set multiplexer and catch (C) output so that lock-on signal is coupled to, thereby allow tester directly to control full speed control ﹠amp; Catch operation.When device has in the system of other devices, for example shown in Figure 21 and 22, will advantageously use CMD circuit 804 to control and catch (C) output.When during by the tester test component, advantageously using lock-on signal to control and catch (C) output in wafer scale or package level device detection.

Figure 28 illustrates another example implementation of CMD circuit 2604, and it comprises previous described CMD circuit 804 and multiplexer 2702 and 2802 of Figure 11 and Figure 12.When CMD circuit 2604 is set to allow CMD circuit 804 to control renewal (U) and catches (C) output, DRE input will arrange multiplexer will upgrade (U) and to catch the output that CMD circuit 804 is coupled in (C) output, thereby permission is as the full speed renewal ﹠amp described in Figure 11 and 12; Catch and and ﹠amp; Catch operation.When CMD circuit 2604 is set to allow renewal and lock-on signal to control renewal (U) and catches (C) output, the DRE input will arrange multiplexer and be coupled to renewal (U) with lock-on signal and catch (C) output upgrading, thereby allow tester directly to control Geng Xin ﹠amp at full speed; Catch and and ﹠amp; Catch operation.When device has in the system of other devices, for example shown in Figure 21 and 22, will advantageously use CMD circuit 804 to control and upgrade (U) and catch (C) and export.When in wafer scale or package level device detection during by the tester test component, will advantageously use and upgrade and lock-on signal is controlled and upgraded (U) and catch (C) and export.

Figure 29 A illustrates TAP2902, and its TAP800 with Fig. 8 is consistent, except to the output 2904 of the CMD of CMD circuit 802 input from TSM102, rather than inputs from TMS.When TSM was in the ExitlDR state, the CMD output 2904 from TSM occured.When TSM is in the ExitlDR state is realized by detecting with the state decode door for this, as shown in Figure 29 B.

Figure 30 illustrates TSM conversion by ExitlDR state (shade) thereby cmd signal is outputed to the sequential chart of the CMD circuit of Figure 29 A.As shown, the next negative edge from the negative edge of TCK to TCK, the CMD circuit is deposited cmd signal (shade), and is as described in the CMD circuit for Fig. 8.CMD operates rising edge 3008 places of the TCK between two negative edges that occur in TCK.If CMD operation is used the example CMD circuit 802 of Figure 13 and Figure 14 to carry out and caught and shifting function (CSOP) 3002, catch at rising edge 3008 places of TCK.If CMD operation is used the example CMD circuit 802 of Figure 11 or Figure 12 to carry out to catch, be shifted and upgraded operation (CSUOP) 3004, occur to upgrade operating at rising edge 3008 places of TCK, and catch operation at next rising edge 3010 places of TCK.If the CMD operation uses the example CMD circuit 802 of Figure 15 to carry out back-to-back catching and shifting function (B2BCSOP) 3006, at rising edge 3008 places of TCK, first occuring and catch operation, and occurs second at next rising edge 3010 places of TCK and catch operation.

As shown in the sequential chart of Figure 30, different from the sequential chart of Figure 10, TSM must change the ShiftDR state that leaves, through the ExitlDR state, cmd signal is offered CMD circuit 802.For CSOP3002, this means restart the ShiftDR state after catching operation before, must be through two dead states (being the attonity state), time-out data register (PauseDR) and withdraw from 2 data registers (Exit2DR).For CSUOP3004, this means restart the ShiftDR state after upgrading and catching operation before, must be through a dead state Exit2DR.For B2BCSOP3006, this means restart the ShiftDR state after first and second catch operation before, must be through a dead state Exit2DR.Although use ExitlDR state-detection cmd signal to introduce dead state, dead state occur in the full speed displacement of expectation and catch operation (CSOP) 3002, at full speed upgrade and catch operation (CSUOP) 3004 with full speed is back-to-back catch operation (B2BCSOP) 3006 after.

As everyone knows, when the ShiftDR state was left in the TSM102 conversion, it stopped or gate is closed in clock signal in its ClockDR output.As shown in the sequential chart of Figure 30, CSOP operation 3002 needs clock to be used to catch operation in the ExitlDR state, CSUOP operation 3004 needs clock to be used for upgrading and catching operation in ExitlDR and PauseDR state, and B2BCSOP operation 3006 needs clock to be used for the back-to-back operation of catching in ExitlDR and PauseDR state.Figure 31 and 32 following description will be illustrated in the example how these clocks are provided during these states on ClockDR.

Figure 31 illustrates asynchronous register 3102, two-port router 804, CMD circuit 802 and TSM102.Asynchronous data register 3102 can be asynchronous CSU data register 402 or asynchronous CS data register 602.If asynchronous CSU data register 402, the 802 general's operations as described in Figure 11 of CMD circuit are to provide ClockDR, ShiftDR and update signal to data register via two-port router 804.If asynchronous CS data register 602, CMD circuit 802 will be as Figure 13 or the described operation of Figure 15 to provide ClockDR and ShiftDR signal to data register via two-port router 804.Unique difference between the layout of the use CMD circuit 802 of describing before the layout of Figure 31 and other is, to the cmd signal of the CMD circuit of Figure 31 from TSM, rather than from tms signal.TSM comprises the gating circuit 2904 of Figure 29 B and comprises further ClockDR gating circuit 3102, gating circuit 2904 provides cmd signal during the ExitlDR state, ClockDR gating circuit 3102 provides clock signal on ClockDR, as above described for CSOP, CSUOP and B2BCSOP operation.

Figure 32 illustrates the example of the ClockDR gating circuit 3102 of TSM, and it comprises gating circuit (G) 3204-3208 and multiplexer (MUX) 3202, all connects as shown in the figure.The one of four states signal of each gating circuit 3204-3208 input tck signal and indication TSM state.When TSM was in CaptureDR or ShiftDR state, gating circuit 3204 was delivered to multiplexer with TCK.When TSM was in CaptureDR, ShiftDR or ExitlDR state, gating circuit 3206 was delivered to multiplexer with TCK.When TSM was in CaptureDR, ShiftDR, ExitlDR or PauseDR state, gating circuit 3208 was delivered to multiplexer with TCK.Multiplexer receives the DRE input from order register, thereby selects which gating circuit output to be delivered to ClockDR output.

When TSM is controlling to the drc signal of data register 3102, the output of gating circuit 3204 will be multiplexed into the ClockDR output of multiplexer 3202, thereby allow catching with shifting function or catching, be shifted and upgrade operation of conventional IEEE1149.1TSM control.When during the CSOP of Figure 30 operation 3002, when the CMD circuit is controlling to the drc signal of data register 3102, the output of gating circuit 3206 will be multiplexed into the ClockDR output of multiplexer 3202, thereby during the ExitlDR state, provide the needed extra clock of catching on ClockDR.When during the CSUOP of Figure 30 operation 3004, when the CMD circuit is controlling to the drc signal of data register 3102, the output of gating circuit 3208 will be multiplexed into the ClockDR output of multiplexer 3202, thereby during the ExitlDR state, needed extra refresh clock is being provided on ClockDR and during the PauseDR state, is providing the needed clock of catching on ClockDR.When during the B2BCSOP of Figure 30 operation 3006, when the CMD circuit is controlling to the drc signal of data register 3102, the output of gating circuit 3208 will be multiplexed into the ClockDR output of multiplexer 3202, thereby during the ExitlDR state, provide needed extra first to catch clock on ClockDR, and during the PauseDR state, provide needed extra second to catch clock on ClockDR.

Figure 33 illustrates following layout, and it comprises circuit block 2602, two-port router 804, TSM102 and CMD circuit 2604.Figure 33 is consistent with Figure 26, except TSM is modified to, as front described in Figure 31, via gating circuit 2904, cmd signal is outputed to CMD circuit 2604 during the ExitlDR state, and via gating circuit 3104, clock signal is outputed to two-port router during other selected TSM states.As for Figure 26,27 and 28 described, 2602 DRC input can be controlled by the CMD circuit from the two-port router to the circuit block, perhaps controls from being connected to catching with the tester of update signal of accessible outside.

Figure 34 A illustrates TAP3402, and the similar part of the TAP2902 of itself and Figure 29 A is, it comprises data register 106, two-port router 804, order register 104, multiplex electronics 110 and TSM102.The difference of itself and TAP2902 is, TAP3402 uses programmable switch (PSW) circuit 3406 to replace CMD circuit 802.TSM102 has expanded TSM state detection circuit 3404.The TSM state detection circuit is implemented as and detects ExitlDR and PauseDR state, as shown in the example of Figure 34 B.The ExitlDR(EDR that detects) and the PauseDR(PDR that detects) the TSM status signal is together with input is imported into the PSW circuit from the DRE of order register.The PSW circuit is controlled DRC and is outputed to two-port router 804, thereby is controlled at catching and being shifted, catching, being shifted and renewal or back-to-back catching and shifting function on selected one or more data registers.To the DRE of PSW circuit input, it is programmed for as required EDR and PDR signal coupling to suitable drc signal, the data register is carried out CSOP, CSUOP or B2BCSOP operation.

Figure 35 illustrates the TSM conversion and carries out the sequential chart of CSOP operation 3502, CSUOP operation 3504 and B2BCSOP operation 3506 by each state with use state detection circuit 3404 and PSW circuit 3406.During CSOP operation 3502, the ExitlDR state that detects is controlled thereby make two-port router export DRC through PSW, catches operation so that selected data register is carried out.During CSUOP operation 3504, the ExitlDR state that detects is through PSW, thereby two-port router output DRC is controlled, so that being carried out, selected data register upgrades operation, and the PauseDR state that detects is through PSW, thereby two-port router output DRC is controlled, catch operation so that selected data register is carried out.During B2BCSOP operation 3506, the ExitlDR state that detects is through PSW, thereby two-port router output DRC is controlled, so that being carried out first, selected data register catches operation, and the PauseDR state that detects is through PSW, thereby two-port router output DRC is controlled, catch operation so that selected data register is carried out second.

Similar to the sequential chart of Figure 30, the sequential chart of Figure 35 comprises dead state.As shown, during CSOP operation 3502, two dead states occuring, during CSUOP operation 3504, a dead state occurs, during B2BCSOP operation 3506, a dead state occurs.These dead states are not tedious, because after they occur in expectation during CSOP circulation 3502 full speed is caught operation, after the full speed that occurs in expectation during CSUOP circulation 3504 is upgraded and is caught operation, after occurring in during B2BCSOP circulation 3506 that the full speed of expectation is back-to-back and catching operation.

Figure 36 illustrates asynchronous register 3602, two-port router 804, TSM102 and PSW circuit 3406, all connects as shown in the figure.Asynchronous data register 3602 can be asynchronous CSU data register 402 or asynchronous CS data register 602.

If data register 3602 is asynchronous CSU data registers 402, PSW3406 will be programmed for the ExitlDR signal coupling of self-detection circuit 3404 in the future to renewal (U) the signal output of PSW by DRE input, and catch (C) that PSW is coupled in the PauseDR signal output of self-detection circuit 3404 in the future exports.By can detect the ExitlDR state time, the renewal of PSW (U) output is by effectively when TSM conversion, and is applied to the UpdateDR input of CSU data register via two-port router, upgrades operation thereby carry out.By can detect the PauseDR state time, PSW catches (C) output by effectively, and is applied to the ShiftDR input of CSU data register via two-port router, catches operation thereby carry out when TSM conversion.

If data register 3602 is asynchronous CS data registers 602, and will carry out CSOP operation to register, PSW3406 will be programmed in the future the ExitlDR signal coupling of self-detection circuit 3404 by the DRE input and export to (C) signal of catching of PSW.By can detect the ExitlDR state time, PSW catches (C) output by effectively, and is applied to the ShiftDR input of CS data register via two-port router, catches operation thereby carry out when TSM conversion.

If data register 3602 is asynchronous CS data registers 602, and to carry out the B2BCSOP operation to register, the PSW3406 ExitlDR signal coupling that will be programmed for self-detection circuit 3404 in the future by DRE input to PSW catch the output of (C) signal, and the PauseDR signal coupling of self-detection circuit 3404 is exported to (C) signal of catching of PSW in the future.By can detect the ExitlDR state time, PSW catches (C) output by effectively, and is applied to the ShiftDR input of CS data register via two-port router, catches operation thereby carry out first when TSM conversion.By can detect the PauseDR state time, PSW catches (C) output by again effective, and is applied to the ShiftDR input of CS data register via two-port router, catches operation thereby carry out second when TSM conversion.

As finding out in Figure 36, TSM has been expanded foregoing ClockDR gating circuit 3104, thereby provide clock signal on ClockDR during required TSM state, as described in Figure 32, thereby carry out CSOP, CSUOP and the B2BCSOP operation that above-mentioned PSW controls.Can design in many ways PSW circuit 3406, comprise the mode of using by gating circuit and the multiplexer of DRE input control, and use the mode by gating circuit and the cross bar switch of DRE input control.

Figure 37 illustrates following layout, and it comprises circuit block 2602, two-port router 804, TSM102 and new PSW circuit 3702, all connects as shown in the figure.As shown in Figure 38, new PSW circuit 3702 comprises previously described PSW circuit 3406 and two multiplexers 3802 and 3804.3406 inputs of PSW circuit are from ExitlDR and the PauseDR signal of the testing circuit 3404 of previously described TSM102, and input is from the DRE input of order register.PSW circuit 3406 outputs to signal multiplexer 3802 and signal is outputed to multiplexer 3804.Multiplexer 3802 inputs are from signal, lock-on signal, the DRE control inputs signal of PSW3406, and (C) signal is caught in output.Multiplexer 3804 inputs are from signal, update signal, the DRE control inputs signal of PSW3406, and (U) signal is upgraded in output.New PSW3702 may operate in two kinds of patterns determining as by the DRE input.Consistent with described in Figure 34 A and Figure 36 of the first pattern, wherein PSW3406 responds ExitlDR and the PauseDR status signal that detects, thereby controls catching (C) and upgrading (U) output of new PSW3702 via multiplexer 3802 and 3804.The second pattern allows catching (C) and upgrading (U) output by controlling to catching with update signal of multiplexer 3802 and 3804 of new PSW3702.As mentioning in previous Figure 26 and Figure 33, when TAP102 is in the ShiftDR state, during wafer and packaging manufacturing test, catch with update signal and can directly be controlled by tester, thereby more effectively control CSOP, CSUOP and B2BCSOP test operation.

Figure 39 illustrates TAP3902, and the similar part of the TAP3402 of itself and Figure 34 A is, it comprises data register 106, two-port router 804, order register 104, multiplex electronics 110 and TSM102.The difference of TAP3902 and TAP3402 is, it does not comprise PSW circuit 3406.As shown, from the ExitlDR(EDR of the TSM of state detection circuit 3404) and PauseDR(PDR) state detection signal be directly coupled to the DRC input of two-port router.Two-port router 804 is designed to respond the DRE input, thereby EDR and PDR signal coupling are arrived selected data register, thereby allows data register to carry out CSOP, CSUOP or B2BCSP operation in response to signal, and is as shown in Figure 35.

In the first example, if data register 1 is the CS data register and will carries out as shown in figure 35 CSOP operation 3502, DRE instruction input will be controlled two-port router 804 with the DRC3904 input of EDR signal coupling to data register 1, when catch operation thereby control.If the CS data register is asynchronous 602 type registers, this means that the EDR signal will be coupled to via the DRC output 3904 of two-port router 804 the ShiftDR input of register.

In the second example, if data register N is the CSU data register and will carries out as shown in figure 35 CSUOP operation 3504, DRE instruction input will be controlled two-port router 804 with the DRC3906 input to data register N of EDR and PDR signal coupling, thereby control when renewal occurs and catches operation.If the CSU data register is asynchronous 402 type registers, this means that so the EDR signal will be coupled to via the DRC output 3906 of two-port router 804 the UpdateDR input of register, and the PDR signal will be coupled to via the DRC output 3906 of two-port router 804 the ShiftDR input of register.

Figure 40 illustrates TAP4002, and the similar part of the TAP3902 of itself and Figure 39 is, it comprises data register 106, two-port router 804, order register 104, multiplex electronics 110 and TSM102.The difference of TAP4002 and TAP3902 is, inserts multiplexer (MUX) 4008 in its EDR between TSM and two-port router and PDR signal path.Multiplexer has the input with update signal of catching for accessible outside.Multiplexer is by the DRE input control, thereby the DRC input that allows two-port router is perhaps controlled by catching with update signal of accessible outside by EDR and PDR TSM signal controlling.When the DRC that selects EDR and PDR signal controlling to two-port router inputs, the operation that TAP4002 is as shown in Figure 39.When selecting to catch when controlling to the DRC input of two-port router with update signal, operation described in TAP402 such as front Figure 26,33 and 37.

Figure 41 illustrates following layout, and it comprises circuit block 2602, two-port router 804, TSM102 and multiplexer 4008, all connects as shown in the figure.Multiplexer 4008 input is from the ExitlDR(EDR of TSM) and PauseDR(PDR) signal, catch and update signal, and DRC controlled output to two-port router, as shown in Figure 40.(C) signal is caught in PSW3406 input capture signal, DRE control inputs signal and output.Multiplexer 4008 may operate in two kinds of patterns that input is determined as DRE.The first pattern allows ExitlDR and PauseDR signal controlling to arrive the DRC input of two-port router.The second pattern allows to catch the DRC input that controls to two-port router with update signal.As mentioning in previous Figure 26 and Figure 33, when TAP102 is in the ShiftDR state, during wafer and packaging manufacturing test, catch with update signal and can directly be controlled by tester, thereby more effectively control CSOP, CSUOP and B2BCSOP test operation to circuit block 2602.

The value of two-port router is that it allows objective circuit to control by TSM is conventional, is perhaps controlled by the described new method of the disclosure.For example, in Figure 21, during standard IEEE 1149.1 interconnecting test command operatings, the device in daisy-chain arrangement can optionally be controlled by TSM, and perhaps during new full speed interconnecting test command operating of the present disclosure, they can be controlled by the CMD circuit.According to the disclosure, any standard or off-gauge IEEE1149.1 instruction can have two kinds of operator schemes.The first operator scheme is controlled via two-port router is conventional by TSM, and the second operator scheme is controlled via two-port router according to instruction of the present disclosure.

Should be appreciated that, although at two-port router shown in embodiment of the present disclosure, it is not necessary feature of the present disclosure.In fact, if do not need the conventional TSM access to data register 106 or other circuit 2602, two-port router can be replaced by following another router, this router can receive DRE input, thereby will be from the DRC output of CMD circuit, PSW circuit, ExitlDR and PauseDR state detection circuit or from the DRC input of being coupled to data register 106 or circuit 2602 with update signal of catching of accessible outside.

Device circuitry

106 and 2602 includes but not limited to, device detection circuit, device debug circuit, device programming circuit, device equipment circuit, device read/write circuits, device tracking circuit and device simulation circuit.

It will be appreciated by those skilled in the art that in desired scope of the present invention, other embodiment and distortion are possible; And, even for simplicity or concisely, feature or step are to describe under the background of the whole or example embodiment more only in having these features or step, and also intention covers the embodiment of the various combination with one or more described features or step.

Claims

1. the test access port framework in an integrated circuit, it comprises:

TDI input lead, TCK input lead, TMS input lead and TDO output lead,

The Tap state machine, it has the input of being coupled to described TCK input lead, the input of being coupled to described TMS input lead, order register control output, control output and data register control exports,

Order register, it has the input of being coupled to described TDI input lead, input, the data register that is coupled to described order register control output controlled output and output,

Data register, it has input, data register control inputs and the output of being coupled to described TDI input lead,

Command circuit, it has the input of being coupled to described TCK input lead, the input of being coupled to described TMS input lead and data register and controls output,

Two-port router, the data register that it has the data register that is coupled to described Tap state machine is controlled the input of output, the data register that is coupled to described command circuit is controlled output input, be coupled to the control inputs that the data register of described order register enables to export and the data register control inputs that is coupled to described data register is controlled output, and;

Multiplexer circuit, it has the input of the output of being coupled to described order register, the input of being coupled to the output of described data register, the control inputs of control output that is coupled to described Tap state machine and the output of being coupled to described TDO output lead.

2. the test access port framework in an integrated circuit, it comprises:

TDI input lead, TCK input lead, TMS input lead and TDO output lead,

The Tap state machine, it has the input of being coupled to described TCK input lead, the input of being coupled to described TMS input lead, order register control output, controls output, the output of ExitlDR state-detection and data register control output,

Command circuit, it has the input of being coupled to described TCK input lead, the input of being coupled to described ExitlDR state-detection output and data register and controls output,

3. the test access port framework in an integrated circuit, it comprises:

TDI input lead, TCK input lead, TMS input lead and TDO output lead,

The Tap state machine, it has that the input of being coupled to described TCK input lead, the input of being coupled to described TMS input lead, order register are controlled output, controlled output, the output of ExitlDR state-detection, the output of PauseDR state-detection and data register are controlled output

The programmable switch circuit, it has the input of being coupled to described ExitlDR state-detection output, the input of being coupled to described PauseDR state-detection output and data register and controls output,

Two-port router, the data register that it has the data register that is coupled to described Tap state machine is controlled the input of output, the data register that is coupled to described programmable switch circuit is controlled output input, be coupled to the control inputs that the data register of described order register enables to export and the data register control inputs that is coupled to described data register is controlled output, and;

Multiplexer circuit, it has the input of the output of being coupled to order register, the input of being coupled to the output of data register, the control inputs of control output that is coupled to the Tap state machine and the output of being coupled to described TDO output lead.

4. the test access port framework in an integrated circuit, it comprises:

TDI input lead, TCK input lead, TMS input lead and TDO output lead,

The Tap state machine, it has that the input of being coupled to described TCK input lead, the input of being coupled to described TMS input lead, order register control that output, data register are controlled output, controlled output, the output of ExitlDR state-detection and the output of PauseDR state-detection

Order register, it has the input of being coupled to described TDI input lead, input, the data register that is coupled to described order register control output enables output and output,

Two-port router, it has, and the data register that is coupled to described Tap state machine is controlled the input of the input of output, the ExitlDR that is coupled to described Tap state machine and the output of PauseDR state-detection, the data register that is coupled to the control inputs that the data register of described order register enables to export and the data register control inputs that is coupled to described data register is controlled output, and;

5. the test access port framework in an integrated circuit, it comprises:

TDI input lead, TCK input lead, TMS input lead, catch input lead, upgrade input lead and TDO output lead,

Order register, it has the input of being coupled to described TDI input lead, input, the data register that is coupled to order register control output enables output and output,

Multiplexer, it has input, the input of being coupled to described PauseDR state-detection output of being coupled to the output of described ExitlDR state-detection, be coupled to described input of catching input lead, be coupled to described renewal input lead input, be coupled to control inputs and the data register that described data register enables to export and control output

Two-port router, the data register that it has the data register that is coupled to described Tap state machine is controlled the input of output, the described data register that is coupled to described multiplexer is controlled output input, be coupled to the control inputs that the data register of described order register enables to export and the data register control inputs that is coupled to described data register is controlled output, and;