CN103078700A - Clock synchronization processing method - Google Patents

Abstract

The invention provides a clock synchronization processing method, which solves the problem that when a plurality of clock servers are connected into exchange networks, the exchange network cannot realize the clock synchronization. The clock synchronization processing method comprises the following links that an switchboard is provided with each port receiving clock synchronization enabling register; when a plurality of clock servers are connected into exchange networks, i.e. a plurality of ports of the switchboard receive the clock synchronization signals, the corresponding interruption is generated, and the condition is reported to a CPU (central processing unit); each port receiving clock synchronization enabling register is set through the CPU, and the corresponding ports are forbidden receiving the clock synchronization signals, so that only one port receives the clock synchronization signals can be ensured; and the port receiving the clock synchronization signal sends the clock synchronization signals to all of the rest ports. When the processing method provided by the invention is adopted, when a plurality of clock servers are connected to the switchboard, the fault-tolerance processing can be carried out, the clock synchronization on the whole exchange network can still be realized, the control is simple, and the realization is easy.

Description

A kind of clock synchronous processing method

Technical field:

The invention belongs to computer communication technology, relate to a kind of clock synchronous processing method of switch in the communication network.

Background technology:

Modern switched communication network is comprised of node machine and switch, and all node machines all link to each other with switch by link, realizes distributed communication.In the hard real time switching network, in order to realize the clock synchronous of whole network, generally by a node machine as clock server, other node machine is as the clock client, regularly carry the clock sync signal of temporal information to the switch transmission by clock server, then by switch clock sync signal is sent to the clock client and bring in realization.When all clients and server sync, they have also been realized each other synchronously.

In actual applications, the user might be connected into switching network with two or more clock servers by mistake.Like this, a plurality of clock servers are the timed sending clock synchronization information all, can cause client time information saltus step to occur, causes whole switching network can't realize clock synchronous.

Summary of the invention:

The processing method that the purpose of this invention is to provide a kind of clock synchronous solves when a plurality of clock servers are connected into switching network, and switching network can't be realized the problem of clock synchronous.

Basic solution of the present invention is:

A kind of clock synchronous processing method comprises following link:

The synchronous enabled register of each port receive clock of switch configuration;

When a plurality of clock servers are connected into switching network, when namely a plurality of ports of switch receive clock sync signal, produce respective interrupt, report CPU;

By CPU the synchronous enabled register of each port receive clock is set, forbids corresponding port receive clock synchronizing signal, thereby guarantee to only have a port receive clock synchronizing signal;

Receive the port of clock sync signal to all the other port tranmitting data register synchronizing signals.

The invention has the beneficial effects as follows:

(1) each port of switch can link to each other with clock server, connects flexibly;

(2) when having a plurality of clock servers to be connected to switch, can carry out fault-tolerant processing, still can realize the clock synchronous to whole switching network;

(3) control is simple, realizes easily.

Description of drawings

Fig. 1 is exchange clock synchronous processing circuit figure of the present invention;

Fig. 2 is the synchronous process chart of exchange clock of the present invention.

Embodiment:

Below in conjunction with accompanying drawing execution mode is specifically described.

At first the exchange clock synchronous processing circuit is introduced, as shown in Figure 1: wherein, input 0～input n is the input of switch ports themselves 0～port n, is used for respectively receiving Frame and the clock sync signal that institute's connected node machine sends; Output 0～output n is the output of switch ports themselves 0～port n, is used for respectively sending Frame and clock sync signal to the node machine that connects; The input of each port has respectively three registers: register A[i], represent whether this port i has received clock sync signal, for the first time receive clock sync signal after, this register sets high, and keeps always; Register B[i], represent whether this port i receive clock synchronizing signal enables, effectively high, this register is arranged by CPU, is defaulted as height; Register C[i], represent that this port i has received that clock sync signal and this port receive clock synchronizing signal enable, high effectively, represent that namely this port received effective clock sync signal (wherein, i=0 ... n).Adder is used for calculating C[0], C[1] ..., C[n] and sum, when with greater than 1 the time, produce respective interrupt, report CPU.CPU is responsible for disposing related register, handling interrupt.

The below is introduced the synchronous handling process of exchange clock.

1) after the port i of switch receives clock sync signal, with the register A[i of correspondence] put 1, then with A[i] with B[i] with, produce C[i].Again each place value of register C is carried out addition, when sum was 1, showing had 1 port to receive clock sync signal, turns step 4); Otherwise, when sum greater than 1 the time, showing has a plurality of ports to receive clock sync signal, turns step 2);

2) switch produces respective interrupt, reports CPU;

3) CPU receives enable register to clock synchronous and arranges as required: select one in receiving a plurality of ports of clock synchronous, the corresponding register of this port is set to the state of enabling, and the corresponding register of other port is set to illegal state; Thereby guarantee to only have effectively receive clock synchronizing signal of a port;

4) because switch can only be to client tranmitting data register synchronizing signal, and can not send to clock server, therefore by everybody carries out negate to register C, need to obtain the destination interface of tranmitting data register synchronizing signal.Then, receive the port input of clock sync signal to the output tranmitting data register synchronizing signal of other all of the port;

5) each port output tranmitting data register synchronizing signal.

Claims (1)

1. clock synchronous processing method comprises following link:

The synchronous enabled register of each port receive clock of switch configuration;

When a plurality of clock servers are connected into switching network, when namely a plurality of ports of switch receive clock sync signal, produce respective interrupt, report CPU;

By CPU the synchronous enabled register of each port receive clock is set, forbids corresponding port receive clock synchronizing signal, thereby guarantee to only have a port receive clock synchronizing signal;

Receive the port of clock sync signal to all the other port tranmitting data register synchronizing signals.

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