CN103077677A - Driving system for display - Google Patents
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- CN103077677A CN103077677A CN201210510358XA CN201210510358A CN103077677A CN 103077677 A CN103077677 A CN 103077677A CN 201210510358X A CN201210510358X A CN 201210510358XA CN 201210510358 A CN201210510358 A CN 201210510358A CN 103077677 A CN103077677 A CN 103077677A
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- 239000003990 capacitor Substances 0.000 claims abstract description 28
- 239000011159 matrix material Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000001419 dependent effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 229920001621 AMOLED Polymers 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
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Abstract
The invention provides a driving system for a display. The driving system comprises a pixel circuit, wherein the pixel circuit is provided with an organic light-emitting element, a storage capacitor, a transistor and a control line for controlling the pixel circuit. When the pixel circuit is stylized and is used for driving the pixel circuit, the brightness decay of the organic light-emitting diode can be compensated by the pixel circuit, and therefore high-accuracy and high-stability current can be generated.
Description
Technical Field
The present invention relates to an organic electroluminescent display, and more particularly, to a driving system for compensating for luminance degradation of an organic electroluminescent diode display.
Background
Organic electroluminescent displays have been widely used in various display devices, and particularly, active matrix driving active light emitting diode (AMOLED) displays having amorphous silicon (a-Si), polysilicon (P-Si), Low Temperature Polysilicon (LTPS), organic or other driving backplanes have been widely attractive due to their advantages of lightness, thinness, active light emission, wide viewing angle, high resolution, high color saturation, fast response speed, low manufacturing cost, wide temperature range, etc.
The AMOLED display comprises a plurality of pixels arranged in a matrix, each pixel comprising an organic light emitting diode, a storage capacitor, and a transistor. Since the AMOLED is a current driving element, it is necessary to provide a precise and stable driving current for the AMOLED pixel unit circuit, and as the usage time increases, the voltage across the two terminals of the OLED increases, i.e. the current flowing through the OLED decreases.
Disclosure of Invention
It is an object of the present invention to provide a driving system for a display, which is capable of generating a current with high accuracy and high stability.
In order to achieve the purpose, the invention adopts the following technical scheme:
the driving system comprises a scanning driving module, a data driving module, a power supply, a data reading module and a plurality of pixel unit circuits, wherein each pixel unit circuit comprises a light-emitting device, a storage capacitor with a first end and a second end, a first transistor with a grid end and a first end and a second end, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;
the grid terminal of the first transistor is connected with the scanning driving module, the first terminal of the first transistor is connected with the data driving module, and the second terminal of the first transistor is connected with the first terminal of the storage capacitor and the first terminal of the second transistor;
the grid terminal of the second transistor is connected with the scanning driving module, the first terminal of the second transistor is connected with the first terminal of the storage capacitor, and the second terminal of the second transistor is connected with the first terminal of the fourth transistor, the second terminal of the sixth transistor and the second terminal of the seventh transistor;
the grid terminal of the third transistor is connected with the scanning driving module, the first terminal of the third transistor is connected with the second terminal of the storage capacitor and the grid terminal of the fourth transistor, and the second terminal of the third transistor is connected with the second terminal of the fourth transistor and the first terminal of the fifth transistor;
the gate terminal of the fourth transistor is connected to the second terminal of the storage capacitor, the first terminal of the fourth transistor is connected to the second terminal of the sixth transistor and the second terminal of the seventh transistor, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor;
the grid end of the fifth transistor is connected with the scanning driving module, and the second end of the fifth transistor is connected with the low-potential end of the power supply;
the grid end of the sixth transistor is connected with the scanning driving module, and the second end of the sixth transistor is connected with the second end of the seventh transistor;
the grid end of the seventh transistor is connected with the scanning driving module, and the first end of the seventh transistor is connected with the data reading module;
one end of the light emitting device is connected to a first end of the sixth transistor, and the other end is connected to a high potential end of the power supply.
The scanning driving module is led out of a first selection line, a second selection line, a third selection line and a fourth selection line, a grid end of the first transistor and a grid end of the third transistor are connected with the first selection line, a grid end of the fifth transistor is connected with the second selection line, a grid end of the second transistor and a grid end of the sixth transistor are connected with the third selection line, and a grid end of the seventh transistor is connected with the fourth selection line.
The scanning driving module drives the pixel unit circuit to sequentially form a programming period and a driving period through the first selection line, the second selection line, the third selection line and the fourth selection line, the programming period sequentially comprises a pre-charging period and a compensation period, and the driving period sequentially comprises a light-emitting period and a signal reading period.
The storage capacitor is charged during a precharge period and discharged during a compensation period, and a stored value of the storage capacitor is applied between the first terminal of the fourth transistor and the gate of the fourth transistor during a driving period.
During the compensation period, the storage value of the storage capacitor depends on the threshold voltage of the fourth transistor, the cross voltage of the light emitting device and the gray scale voltage.
The display is an organic electroluminescent display or an active matrix light emitting display.
The light emitting device is an organic light emitting diode.
At least one of the first to seventh transistors is amorphous, nanocrystalline, microcrystalline, polycrystalline, organic, N-type, P-type, or CMOS silicon.
When the driving system for the display disclosed by the invention programs the pixel unit circuit and drives the circuit, the circuit can realize the compensation of the brightness attenuation of the light-emitting device, and can generate high-precision and high-stability current.
Drawings
FIG. 1 is a schematic diagram of a pixel cell circuit according to the present invention;
FIG. 2 shows a timing diagram provided in accordance with the pixel cell circuit of FIG. 1;
FIG. 3 shows the structure of a drive system formed by the pixel cell circuit of FIG. 1;
in the figure: the scan driving module SD, the data driving module DD, the pixel unit circuit 200, the light emitting device 216, the storage capacitor 218, the first transistor 202, the second transistor 204, the third transistor 206, the fourth transistor 208, the fifth transistor 210, the sixth transistor 212, the seventh transistor 214, the first selection line S1, the second selection line S2, the third selection line S3, the fourth selection line S4, the programming period 220, the driving period 222, the pre-charging period X21, the compensation period X22, the light emitting period X23, and the signal reading period X24.
Detailed Description
The invention is further illustrated by the following figures and examples.
Embodiments of the present invention are described by a pixel circuit of a light emitting device using an organic light emitting diode and a plurality of transistors. However, the pixel circuits may include different classes of OLED devices, the transistors in the pixel circuits may be n-type, P-type, or a combination thereof, and the transistors in the pixel circuits may be fabricated using amorphous silicon (a-Si), polysilicon (P-Si), Low Temperature Polysilicon (LTPS), NMOS/PMOS technology, or CMOS technology. The display with pixel cell circuits may be a monochrome, multi-color or full-color display and may include one or more light-emitting elements. The display can be used in DVD, PDA, computer, notebook computer and TV.
In the following description, "pixel circuit" and "pixel" are used interchangeably. In the following description, "connected" and "coupled" are used interchangeably. In the following description, "control line" and "selection line" and "address line" are used interchangeably.
FIG. 1 shows a 7-transistor T1C pixel cell circuit according to the present invention. The pixel cell circuit 200 of FIG. 1 includes transistors, a storage capacitor 218, and an OLED light emitting device 216. The pixel unit circuit 200 is connected to four selection lines S1, S2, S3, S4, a data line Vdata, two voltage lines VDD, VSS, and a data read line VOUT.
The transistor is a P-type TFT, however, the transistor can also be an N-type TFT. The transistors can be fabricated using amorphous silicon (a-Si), polysilicon (P-Si), Low Temperature Polysilicon (LTPS), NMOS/PMOS technology, or CMOS technology, and the plurality of pixel circuits are arranged in a matrix to form an AMOLED display.
The fourth transistor 208 is a driving transistor. The source of the fourth transistor 108 is connected to the cathode of the OLED light emitting device 216 via the sixth transistor 212, and the drain of the fourth transistor 108 is connected to the voltage line VSS via the fifth transistor 210. The gate of the fourth transistor 108 is connected to the data line Vdata through the storage capacitor 218 and the first transistor 202.
The drain of the third transistor 206 is connected to the source of the fifth transistor 210 and the drain of the fourth transistor 208, and the source of the third transistor 206 is connected to the gate of the fourth transistor 208. The gate of the third transistor 206 is connected to the first select line S1.
The drain of the second transistor 204 is connected to the cathode of the OLED light emitting device 216 via the sixth transistor 212, the source of the second transistor 204 is connected to the data line Vdata via the first transistor 202, and the gate of the second transistor 204 is connected to the select line S3.
The first transistor 202 is a switch transistor, the source of the first transistor 202 is connected to one end of the data line Vdata, the other end of the data line Vdata is connected to the data driving module DD, the drain of the first transistor 202 is connected to the second transistor 204, and the gate of the first transistor 202 is connected to the first selection line S1.
The fifth transistor 210 and the sixth transistor 212 are both light emission control transistors, the source of the fifth transistor 210 is connected to the drain of the fourth transistor 208, the drain of the fifth transistor 210 is connected to one end of a voltage line VSS, the other end of the voltage line VSS is connected to a low potential end of the power supply, and the gate of the fifth transistor 210 is connected to the second selection line S2. The source of the sixth transistor 212 is connected to the cathode of the OLED light emitting device 216, the drain of the sixth transistor 212 is connected to the source of the fourth transistor 208, and the gate of the sixth transistor 212 is connected to the third select line S3.
The seventh transistor 214 is a voltage reading transistor, one end of the seventh transistor 214 is connected to the source of the fourth transistor 208, the other end is connected to one end of the data reading line VOUT, the other end of the data reading line VOUT is connected to the data reading module, and the gate of the seventh transistor 214 is connected to the fourth selection line S4.
The first transistor 202, the second transistor 204, and the storage capacitor 218 are connected at node A. The third transistor 206, the fourth transistor 208 and the storage capacitor 218 are connected at node B.
The anode of the OLED light emitting device 216 is connected to a high potential terminal of a power supply via a voltage line VDD.
Fig. 2 is a schematic diagram of waveforms that may be used in the embodiment of fig. 1, although other waveforms are applicable to fig. 1.
Referring to fig. 1 and 2, the operation of the pixel unit circuit 200 includes two operation cycles: a programming cycle 220 and a driving cycle 222. At the end of the programming cycle 220, node A charges to (V)OLED_int-VP)+(VDD-VOLED_i-1) In which V isPIs a gray scale voltage, VOLED_intIs the initialization voltage, V, of the OLED light-emitting device 216OLED_i-1Is the voltage across, V, of the OLED light-emitting device 216 during the previous frame illuminationDDIs the voltage at the high potential end of the power supply; node B charges to VDD+VTH，VTHIs the threshold voltage of the fourth transistor 208. The storage capacitor is then charged to:
VA-VB=（VOLED_int-VP）+（VDD-VOLED_i-1）-VDD-VTH
=-ΔVOLED-VP-VTH
wherein, is Δ VOLED=VOLED_i-1-VOLED_int，VTH<0。
The programming cycle 220 includes two sub-cycles: precharge period X21, compensation period X22. In the precharge period X21, the first selection line S1, the second selection line S2 are low, the third selection line S3, the fourth selection line S4 are high, the first transistor 202, the third transistor 206, the fifth transistor 210 are turned on, and the second transistor 204, the sixth transistor 212, the seventh transistor 210 are turned onThe crystal 214 is off. The voltage of the data line Vdata (i.e., the voltage at the A point) is (V)OLED_int-VP）+（VDD-VOLED_i-1) That is, the signal of the data line Vdata is the initialization signal and the programming signal V of the OLED light emitting device 216PThe coupling of the signals when the OLED light-emitting device 216 displays the previous frame, VOLED_i-1Is read through the seventh transistor 214, the data read line VOUT, and finally, VOLED_int-VP is added to the data line Vdata. The value of the storage capacitor 218 is:
VA-VB=（VOLED_int-VP）+（VDD-VOLED_i-1）-VSS
VSSis the voltage of the low potential terminal of the power supply, VSSCan be 0 or negative voltage;
in the compensation period X22, the first selection line S1 and the fourth selection line S4 are low, the second selection line S2 and the third selection line S3 are high, such that the first transistor 202, the third transistor 206, the fourth transistor 208 and the seventh transistor 214 are turned on, the second transistor 204, the sixth transistor 212 and the fifth transistor 210 are turned off, and the data line Vdata is continuously provided (V.sub.OLED_int-VP）+（VDD-VOLED_i-1) Voltage, i.e. VA=（VOLED_int-VP）+（VDD-VOLED_i-1) The resulting storage capacitor 216 is discharged through the third transistor 206, the fourth transistor 208, and the seventh transistor 214 until the fourth transistor 108 is driven to turn off, VB=VDD+VTH. The value of the storage capacitor 218 is:
VA-VB=（VOLED_int-VP）+（VDD-VOLED_i-1）-VDD-VTH
=-ΔVOLED-VP-VTH
wherein, is Δ VOLED=VOLED_i-1-VOLED_int，VTHIs a fourth transistor208, and VTH<0。
The driving period 222 includes two sub-periods, i.e., a light-emitting period X23 and a signal reading period X24. In the light emitting period X23, the second selection line S2 and the third selection line S3 are low, the first selection line S1 and the fourth selection line S4 are high, the sixth transistor 212, the second transistor 204 and the fifth transistor 210 are turned on, and the first transistor 202, the third transistor 206 and the seventh transistor 214 are turned off. Storage capacitor sustain- Δ VOLED-VP-VTH。
When the fourth transistor 208 enters the saturation region, the current flowing through the OLED light-emitting device 216 is:
i＝β[Vsg+VTH]2
=β[-ΔVOLED-VP-VTH+VTH]2
=β[ΔVOLED+VP]2
wherein,is the transconductance coefficient, V, of the fourth transistor 208SGIndicating the voltage between the source and the gate of the fourth transistor 208.
Based on the above analysis, the current flowing through the OLED light-emitting device 216 is eventually related to the gray-scale voltage VP、ΔVOLEDCorrelation, i.e. Δ V, with increasing time of useOLEDThe current i flowing through the OLED will increase accordingly, thereby compensating the brightness decay of the OLED caused by the long time usage.
In the phase of the signal reading period X24, the first selection line S1 is high, the second selection line S2, the third selection line S3 and the fourth selection line S4 are low, and the seventh transistor 214 is turned on based on the driving period, so that the OLED light emitting device emits light, and the current voltage value is read through the seventh transistor 214 and finally recorded for being used as one of the data line Vdata coupling signals when the OLED light emitting device is next turned on.
Fig. 3 is a driving system structure formed by the pixel unit circuit of fig. 1. The system includes a plurality of pixel unit circuits 200, a scan driving module SD and a data driving module DD shown in fig. 1, and in fig. 3, the pixels are arranged in two rows and two columns, however, the number of pixels may be different according to the system design and is not limited to the number 4. The pixel array is an active matrix light emitting display and may form an AMOLED display.
Claims (8)
1. A driving system for a display, the driving system comprising a scan driving module (SD), a data driving module (DD), a power supply, a data reading module, and a number of pixel cell circuits (200), characterized in that: the pixel cell circuit (200) includes a light emitting device (216), a storage capacitor (218) having a first terminal and a second terminal, a first transistor (202), a second transistor (204), a third transistor (206), a fourth transistor (208), a fifth transistor (210), a sixth transistor (212), and a seventh transistor (214) having a gate terminal, a first terminal, and a second terminal;
the gate terminal of the first transistor (202) is connected to the scan driving module (SD), the first terminal of the first transistor (202) is connected to the data driving module (DD), the second terminal of the first transistor (202) is connected to the first terminal of the storage capacitor (218) and the first terminal of the second transistor (204);
the gate terminal of the second transistor (204) is connected to the scan driving module (SD), the first terminal of the second transistor (204) is connected to the first terminal of the storage capacitor (218), and the second terminal of the second transistor (204) is connected to the first terminal of the fourth transistor (208), the second terminal of the sixth transistor (212), and the second terminal of the seventh transistor (214);
the gate terminal of the third transistor (206) is connected to the scan driving module (SD), the first terminal of the third transistor (206) is connected to the second terminal of the storage capacitor (218) and the gate terminal of the fourth transistor (208), the second terminal of the third transistor (206) is connected to the second terminal of the fourth transistor (208) and the first terminal of the fifth transistor (210);
a gate terminal of the fourth transistor (208) is connected to the second terminal of the storage capacitor (218), a first terminal of the fourth transistor (208) is connected to the second terminal of the sixth transistor (212) and the second terminal of the seventh transistor (214), and a second terminal of the fourth transistor (208) is connected to the first terminal of the fifth transistor (210);
the gate terminal of the fifth transistor (210) is connected to the scan driving module (SD), and the second terminal of the fifth transistor (210) is connected to the low potential terminal of the power supply;
the gate terminal of the sixth transistor (212) is connected to the scan driving module (SD), and the second terminal of the sixth transistor (212) is connected to the second terminal of the seventh transistor (214);
the gate terminal of the seventh transistor (214) is connected with the scanning driving module (SD), and the first terminal of the seventh transistor (214) is connected with the data reading module;
one terminal of the light emitting device (216) is connected to a first terminal of the sixth transistor (212), and the other terminal is connected to a high potential terminal of a power supply.
2. A driving system for a display according to claim 1, wherein: a first selection line (S1), a second selection line (S2), a third selection line (S3) and a fourth selection line (S4) are led out of the scanning driving module (SD), the grid end of the first transistor (202) and the grid end of the third transistor (206) are connected with the first selection line (S1), the grid end of the fifth transistor (210) is connected with the second selection line (S2), the grid end of the second transistor (204) and the grid end of the sixth transistor (212) are connected with the third selection line (S3), and the grid end of the seventh transistor (214) is connected with the fourth selection line (S4).
3. A driving system for a display according to claim 2, wherein: the scanning driving module (SD) drives the pixel unit circuit (200) through the first selection line (S1), the second selection line (S2), the third selection line (S3) and the fourth selection line (S4) to form a programming period (220) and a driving period (222) in sequence, the programming period (220) comprises a pre-charging period (X21) and a compensation period (X22) in sequence, and the driving period (222) comprises a light-emitting period (X23) and a signal reading period (X24) in sequence.
4. A driving system for a display according to claim 3, wherein: the reservoir capacitor (218) is charged during the precharge period (X21), discharged during the compensation period (X22), and the stored value of the reservoir capacitor (218) is applied between the first terminal of the fourth transistor (208) and the gate of the fourth transistor (208) during the drive period (222).
5. A driving system for a display according to claim 3, wherein: during the compensation period (X22), the stored value of the storage capacitor (218) is dependent on the threshold voltage of the fourth transistor (208), the voltage across the light emitting device (216), and the gray scale voltage.
6. A drive system for a display according to claim 1, 2, 3, 4 or 5, characterized in that: the display is an organic electroluminescent display or an active matrix light emitting display.
7. A drive system for a display according to claim 1, 2, 3, 4 or 5, characterized in that: the light emitting device (216) is an organic light emitting diode.
8. A drive system for a display according to claim 1, 2, 3, 4 or 5, characterized in that: at least one of the first to seventh transistors is amorphous, nanocrystalline, microcrystalline, polycrystalline, organic, N-type, P-type, or CMOS silicon.
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| TWI566221B (en) * | 2014-10-15 | 2017-01-11 | A pixel circuit and a driving method thereof and an organic light emitting display | |
| US9607545B2 (en) | 2013-12-30 | 2017-03-28 | Shanghai Tianma Micro-electronics Co., Ltd. | Organic light emitting display and pixel compensation circuit and method for organic light emitting display |
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