CN103067111A - Method and device of clock synchronization - Google Patents
Method and device of clock synchronization Download PDFInfo
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- CN103067111A CN103067111A CN 201110325787 CN201110325787A CN103067111A CN 103067111 A CN103067111 A CN 103067111A CN 201110325787 CN201110325787 CN 201110325787 CN 201110325787 A CN201110325787 A CN 201110325787A CN 103067111 A CN103067111 A CN 103067111A
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Abstract
The invention discloses a method and a device of clock synchronization. The method comprises that slave clocks are among a plurality of main clocks, and a main clock with the quality being superior to the clocks is confirmed among a plurality of main clocks; according to the priority of transmission links of the clock, a main clock with the highest priority among the confirmed main clocks is chosen to be used as a mainly-used main clock, wherein a plurality of clock transmission links respectively correspond to the plurality of main clocks, and the transmission links are used for clock transmission among the plurality of main clocks. The mainly-used main clock is used for the clock synchronization. Through the above method, the fact that all slave clocks use the same main clock for the clock synchronization is avoided, the load of the main clock is lowered, and the entire performance of the system is improved.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of clock synchronizing method and device.
Background technology
The IPization evolution of wireless network is had higher requirement to the clock synchronization of ad of data communication network equipment.In order to satisfy the needs of IP Radio Access Network (Radio Access Network is referred to as RAN), the frequency between the different base station must be synchronously within certain precision, otherwise mobile phone carries out call drop can occurring when switch the base station.And some wireless standard, also outside frequency, the special requirement Phase synchronization, namely the time is synchronous.
The base station can be satisfied by multiple means the requirement of clock synchronous and time synchronized, comprising: phy clock (such as external clock input, synchronous ethernet etc.), adaptive clock (such as 1588v2 etc.).Compare with traditional Service of Timing, IEEE1588v2 has obvious advantage.When the gps time synchro system that adopts one-way channel, although the acquisition of synchronizing signal is reliable and stable, precision is high, but price is high, and for example, equipment, installation, maintenance cost are high, difficulty of construction large (base station is placed on basement) and failure rate are also high, have simultaneously politics and security risk.IEEE1588v2 adopts two-way channel, and precision is nanosecond (ns) level, and expense is low, can adapt to different access environment etc.Under the industry background that precision is constantly required to improve, 1588 have become a kind of inexorable trend of development.
For from clockwork, in the actual networking in order to guarantee 1588 synchronous reliability and stability, often having two or more clock equipment simultaneously can be for providing the clock synchronous service from clockwork, one of them clock equipment is come to provide synchronous service to SLAVE as the active clock server, other one or more clock equipment are as the standby clock server, as shown in Figure 1.
IEEE Std 1588
TMMentioned in-2008 agreements and when having a plurality of master clock MASTER server in the actual networking, can adopt best master clock (Best Master Clock is referred to as BMC) algorithm to realize selection and the backup functionality of active clock.But have two defectives: at first, the BMC algorithm can only be selected best master clock according to the quality of master clock self, can't detect MASTER and from the transmission link situation between clock SLAVE; Secondly, in a period of time, all SLAVE all can only carry out can not realizing load sharing truly synchronously with same MASTER when the BMC algorithm was selected best master clock.
For all adopt identical master clock to select logic from clock in the correlation technique, the master clock of choosing is identical, thereby cause all can only use this master clock of choosing to carry out clock synchronous from clock, and then cause the very large problem of load of this master clock of choosing, effective solution is not yet proposed at present.
Summary of the invention
For all adopt identical master clock to select logic from clock in the correlation technique, the master clock of choosing is identical, thereby cause all can only use this master clock of choosing to carry out clock synchronous from clock, and then cause the very large problem of load of this master clock of choosing and propose the present invention, for this reason, main purpose of the present invention is to provide a kind of clock synchronizing method and device, to address the above problem.
According to an aspect of the present invention, provide a kind of clock synchronizing method, having comprised: a plurality of master clocks, determined that clock quality is better than the master clock of self from clock; Priority according to the clock transfer link, in the master clock of determining, select the highest master clock of priority as primary master clock, wherein the clock transfer link has many, corresponds respectively to a plurality of master clocks, is used for carrying out clock transfer between each master clock of clock and a plurality of master clocks; Use primary master clock to carry out clock synchronous.
Preferably, from clock a plurality of master clocks, determine that clock quality is better than also comprising before the master clock of self: receive respectively notification packet from a plurality of master clocks from clock; Monitor the clock quality of a plurality of master clocks according to this notification packet.
Preferably, in the priority according to the clock transfer link, in the master clock of determining, select the highest master clock of priority as primary master clock before, also comprise: from the packet loss situation of clock according to the notification packet that receives by the clock transfer link, determine the priority of clock transfer link.
Preferably, in the priority according to the clock transfer link, in the master clock of determining, select the highest master clock of priority as primary master clock before, also comprise: from clock setting and self exist the priority of the master clock of corresponding relation to be higher than the priority that does not have the master clock of corresponding relation with self, wherein corresponding relation is to arrange according to the network topology from clock and a plurality of master clocks.
Preferably, in the priority according to the clock transfer link, in the master clock of determining, select the highest master clock of priority as primary master clock after, also comprise: the master clock of determining, determine that master clock except primary master clock is as master clock for subsequent use from clock.
Preferably, after the primary master clock of use carries out clock synchronous, also comprise: determine that from clock the clock quality of primary master clock is inferior to the clock quality of self, determine that perhaps clock transfer link corresponding to primary master clock is unavailable; According to the priority of clock transfer link, in master clock for subsequent use, select the highest master clock of priority as new primary master clock; Use new primary master clock to carry out clock synchronous.
Preferably, after the new primary master clock of use carries out clock synchronous, also comprise: determine that from clock the clock quality of primary master clock is better than the clock quality of self, and definite clock transfer link corresponding to primary master clock can be used; Recover to use primary master clock to carry out clock synchronous.
According to a further aspect in the invention, provide a kind of clock synchronization apparatus, having comprised: the first determination module, be used at a plurality of master clocks, determine that clock quality is better than the master clock of self; Select module, be used for the priority according to the clock transfer link, in the master clock of determining, select the highest master clock of priority as primary master clock, wherein the clock transfer link has many, correspond respectively to a plurality of master clocks, be used between each master clock of clock and a plurality of master clocks, carrying out clock transfer; Executive Module is used for using primary master clock to carry out clock synchronous.
Preferably, clock synchronization apparatus also comprises: receiver module is used for receiving respectively the notification packet from a plurality of master clocks; Monitoring modular is for the clock quality of monitoring a plurality of master clocks according to notification packet.
Preferably, clock synchronization apparatus also comprises: the second determination module, be used for the packet loss situation according to the notification packet that receives by the clock transfer link, and determine the priority of clock transfer link.
In the correlation technique, all all adopt identical master clock to select logic from clock, the master clock of choosing is identical, thereby causes all can only use this master clock of choosing to carry out clock synchronous from clock, and then causes the load of this master clock of choosing very large.Expanded master clock in the embodiment of the invention and selected logic, not only considered the clock quality of master clock, also considered from the priority of the clock transfer link between clock and the master clock.Because the priority of this clock transfer link was closely related from the clock individuality with this, therefore all master clocks of selecting logic to choose according to this master clock from clock are incomplete same, therefore can avoid all to use same master clock to carry out clock synchronous from clock, alleviate the load of this master clock.Improved the overall performance of system.
Description of drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, consists of the application's a part, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not consist of improper restriction of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart according to the embodiment of the invention;
Fig. 2 is the networking schematic diagram according to the clock synchronous of the embodiment of the invention;
Fig. 3 is flow chart one according to the preferred embodiment of the invention;
Fig. 4 is flowchart 2 according to the preferred embodiment of the invention;
Fig. 5 is the structured flowchart according to the clock synchronization apparatus of the embodiment of the invention;
Fig. 6 is the structured flowchart of clock synchronization apparatus according to the preferred embodiment of the invention.
Embodiment
Need to prove, in the situation that do not conflict, embodiment and the feature among the embodiment among the application can make up mutually.Describe below with reference to the accompanying drawings and in conjunction with the embodiments the present invention in detail.
For all can only use the master clock of choosing to carry out clock synchronous from clock in the prior art, and then cause the very large problem of load of this master clock of choosing, the embodiment of the invention provides a kind of clock synchronizing method, as shown in Figure 1, may further comprise the steps:
Step S102 a plurality of master clocks, determines that clock quality is better than the master clock of self from clock;
Step S104, priority according to the clock transfer link, in the master clock of determining, select the highest master clock of priority as primary master clock, wherein the clock transfer link has many, correspond respectively to a plurality of master clocks, be used between each master clock of clock and a plurality of master clocks, carrying out clock transfer;
Step S106 uses primary master clock to carry out clock synchronous.
In the present embodiment, in correlation technique, all adopt identical master clock to select logic from clock, and the master clock of choosing is identical, thereby cause all can only use this master clock of choosing to carry out clock synchronous from clock, and then cause the load of this master clock of choosing very large.Expanded master clock in the embodiment of the invention and selected logic, not only considered the clock quality of master clock, also considered from the priority of the clock transfer link between clock and the master clock.Because the priority of this clock transfer link was closely related from the clock individuality with this, therefore all master clocks of selecting logic to choose according to this master clock from clock are incomplete same, therefore can avoid all to use same master clock to carry out clock synchronous from clock, alleviate the load of this master clock.Improved the overall performance of system.
Before step S102, namely from clock a plurality of master clocks, determine that clock quality is better than also comprising before the master clock of self: receive respectively notification packet from a plurality of master clocks from clock; Monitor the clock quality of a plurality of master clocks according to this notification packet.In this preferred embodiment, monitor the clock quality of a plurality of master clocks according to notification packet, its implementation is convenient, reliable.
Before step S104, also comprise: from the packet loss situation of clock according to the notification packet that receives by the clock transfer link, determine the priority of clock transfer link.In this preferred embodiment, determine the priority of clock transfer link according to the packet loss situation of notification packet, can guarantee that the clock transfer link that packet loss is few, link-quality is good obtains higher priority, thereby guarantee that master clock corresponding to this clock transfer link obtains the clock synchronous chance, and then can improve from the reliability of the clock synchronous of clock.
Preferably, in the priority according to the clock transfer link, in the master clock of determining, select the highest master clock of priority as primary master clock before, also comprise: from clock setting and self exist the priority of the master clock of corresponding relation to be higher than the priority that does not have the master clock of corresponding relation with self, wherein corresponding relation is to arrange according to the network topology from clock and a plurality of master clocks.
After step S104, also comprise: the master clock of determining, definite master clock except primary master clock is as master clock for subsequent use from clock.
After step S106, also comprise: determine that from clock the clock quality of primary master clock is inferior to the clock quality of self, determine that perhaps clock transfer link corresponding to primary master clock is unavailable; According to the priority of clock transfer link, in master clock for subsequent use, select the highest master clock of priority as new primary master clock; Use new primary master clock to carry out clock synchronous.In this preferred embodiment, at clock transfer insufficient-links corresponding to primary master clock or primary master clock to guarantee in the situation of the clock synchronous of clock, again elect new primary master clock to carry out clock synchronous, can improve from the reliability of the clock synchronous of clock.
Preferably, after the new primary master clock of use carries out clock synchronous, also comprise: determine that from clock the clock quality of primary master clock is better than the clock quality of self, and definite clock transfer link corresponding to primary master clock can be used; Recover to use primary master clock to carry out clock synchronous.In this preferred embodiment, in the situation that primary master clock ability is recovered, recover to use primary master clock to carry out clock synchronous, can further improve from the reliability of the clock synchronous of clock.
Be described in detail below in conjunction with the implementation procedure of example to the embodiment of the invention.
For clock equipment, a master clock server needs to provide service to a plurality of from clockwork simultaneously, when having a plurality of available master clock server in the actual networking, need a part to provide service from clockwork by one of them master clock server, another part provides service from clockwork by other certain master clock servers.Simultaneously, need other non-primary clock servers all to can be used as backup, when the active clock server of certain SLAVE use can't normally provide synchronous service, SLAVE can take over seamlessly and carry out on the master clock server for subsequent use synchronously.And the active clock server recover normal after, SLAVE can return to and this active clock server synchronously in.
Fig. 2 is the networking schematic diagram according to the clock synchronous of the embodiment of the invention, as shown in Figure 2, exist MASTER_A and two master clocks of MASTER_B can be simultaneously to provide service for being numbered 1～50 SLAVE in network topology, MASTER_A provides service for the SLAVE that is numbered 1～No. 25 in normal clock synchronous, and MASTER_B is as its backup master clock server; Same MASTER_B provides service for being numbered 26～50 SLAVE, and MASTER_A is as the master clock server of its backup.When MASTER_A can't provide service for a certain reason to the SLAVE that is numbered 1, this SLAVE can take over seamlessly that to use MASTER_B to carry out as master clock 1588 synchronous.When MASTER_A can be again when being numbered 1 SLAVE service be provided, this SLAVE can recover active clock server MASTER_A with appointment and carry out 1588 synchronous.
When existing a plurality of master clock servers to provide service for SLAVE, we have adopted the concept of logic port in the SLAVE side, and namely a PTP logic port correspondence and a MASTER communicate.Like this, when realizing active and standby master clock and load sharing, can realize by the priority of specifying master clock link corresponding to each PTP logic port on the SLAVE backstage.
Fig. 3 is flow chart one according to the preferred embodiment of the invention, as shown in Figure 3, has described from the primary and backup master clock link of clock initial selected, comprises that following step S302 is to step S314.
Step S302,, the PORT-A of configuration SLAVE1 and high priority and the low priority that PORT-B is respectively the SLAVE port.
Step S304,, the signaling signaling that sends announcement announce to PORT-A asks authorization messages to MASTER_A, sends the signaling request authorization messages of announce to MASTER_B to PORT-B.
Step S306, PORT_A and PORT_B calculate the quality condition that packet loss detects respective links by the reception condition of Announce message respectively.
Whether step S308, clock chain circuit A transmission quality meet the demands and are better than clock chain circuit B transmission quality.If meet the demands and be better than clock chain circuit B transmission quality, execution in step S310 then, otherwise execution in step S312.
Step S310, SLAVE1 use PORT_A to initiate synchronization request and carry out clock synchronous with MASTER_A; PORT_B keeps detecting synchronously with MASTER_B transceiver communication announce message the quality condition of link B.
Step S312, SLAVE1 use PORT_B and MASTER_B to carry out clock synchronous; PORT_A keeps detecting synchronously with MASTER_A transceiver communication announce message the situation of link A.
Step S314, flow process finishes.
In above-mentioned flow process, SLAVE can monitor by the Announce message that receives simultaneously each master clock transmission the clock quality of each master clock, compare by the BMC algorithm, for the master clock link better than SLAVE clock self clock quality, the PTP port that its priority is high corresponds to current primary MASTER, and the MASTER corresponding to PTP logic port of other low link priority is master clock for subsequent use.
Fig. 4 is flowchart 2 according to the preferred embodiment of the invention, as shown in Figure 4, has described the switching of active and standby master clock link and the realization of load sharing, comprises following step S402 to S414.
Step S402, PORT_A and MASTER_A clock synchronous and use Sync packet sending and receiving detect clock chain circuit A; PORT_B communicates by letter with MASTER_B and uses the Announce packet sending and receiving to detect clock chain circuit B.
Step S404, whether clock chain circuit A quality meets the demands.If meet the demands, then return step S402; If do not meet the demands, execution in step S406 then.
Step S406, whether clock chain circuit B quality meets the demands.If meet the demands, execution in step S408 then; If do not meet the demands, execution in step S410 then.
Step S408, the PORT_A cancellation is with the MASTER_A clock synchronous and use the Announce packet sending and receiving to detect the quality condition of clock chain circuit A, and link A switches to master clock link for subsequent use; PORT_B initiates synchronization request and uses the Sync packet sending and receiving to detect the quality condition of clock chain circuit B to MASTER_B, and link B switches to primary master clock link.Continue execution in step S414.
Step S410 continues to detect remaining master clock for subsequent use, until search out satisfactory clock chain circuit N.
Step S412, the PORT_A cancellation is with the MASTER_A clock synchronous and use the Announce packet sending and receiving to detect the quality condition of clock chain circuit A, and link A switches to master clock link for subsequent use; PORT_N initiates synchronization request and uses the Sync packet sending and receiving to detect the quality condition of clock chain circuit N to MASTER_N, and link N switches to primary master clock link.
Step S414, flow process finishes.
Above-mentioned Fig. 3 and flow process shown in Figure 4 are respectively from the flow process of the realization of the switching of the flow process of the primary and backup master clock link of clock initial selected and active and standby master clock link and load sharing, do not explain orally from overall flow, below, will the whole flow process from the realization load sharing to handoff links be made an explanation.
(1) can be respectively initiates the signaling message of the request mandate of Announce message to each self-corresponding master clock from clockwork its each PTP SLAVE logic port after powering on, and whether respond according to master clock in the time or detect the clock transfer link-quality according to the packet loss situation of master-salve clock link transmitting-receiving Announce message in the short-term of regulation.
(2) if the master clock link of different priorities all is in good state and is better than self clock quality, then from clock automatically select the highest PTP of link priority from logic port as current active clock link, and the signaling message that begins to initiate the request mandate of Sync (synchronously) message and Delay_Resp (delayed response) message, beginning and this master clock carry out clock synchronous, and the lower PTP of other link priority from master clock corresponding to logic port as master clock for subsequent use.
(3) the SLAVE logic port that primary master clock link is corresponding during execution in step (1) uses the transmitting-receiving of Sync message to carry out link-quality and detects, and the SLAVE logic port that other master clock links for subsequent use are corresponding then adopts the transmitting-receiving of Announce message to carry out link-quality and detects.
(4) when the clock synchronous process, detecting current primary master clock link poor quality or primary master clock sole mass from clockwork and be lower than from clock itself, just can initiate to the MASTER of current primary master clock link the signaling message of the cancellation mandate of Sync and Delay_Resp message, and this master clock link is set to master clock link for subsequent use.
(5) from clockwork other master clock links for subsequent use, seek one satisfy link transmission quality, corresponding master clock quality is better than being used as the primary master clock link that will switch to from link clock itself, that priority is the highest, and to the request mandate signaling message that MASTER corresponding to this clock link initiates Sync and Delay_Resp message, begin thus to carry out clock synchronous with new master clock.
(6) each PTP still can monitor quality and the link-quality of each master clock self simultaneously from logic port in the synchronizing process after above-mentioned switching, in finding master clock for subsequent use, have the clock sole mass be better than from clock and its corresponding link can with and priority when higher, from clockwork can repeated execution of steps (4) and step (5) to switch to the higher enterprising row clock of master clock link of this priority synchronous.
Can find out that the present embodiment is for the situation that can't take into account clock chain circuit quality and realization load sharing in the BMC algorithm, mode by user's participation, in the mode of link priority corresponding to each master clock of configuration, provide a kind of and must realize that with reasonable active and standby master clock link switches and the method for master clock load sharing function more comprehensively.
The embodiment of the invention also provides a kind of clock synchronization apparatus.Fig. 5 is the structured flowchart according to the clock synchronization apparatus of the embodiment of the invention, as shown in Figure 5, this device can be used for realizing above-mentioned clock synchronizing method, need to prove, its concrete implementation procedure had been carried out detailed description in embodiment of the method, do not repeat them here.This device comprises: the first determination module 10, select module 20 and Executive Module 30, and the below is described in detail its structure.
The first determination module 10 is used at a plurality of master clocks, determines that clock quality is better than the master clock of self; Select module 20, be connected to the first determination module 10, be used for the priority according to the clock transfer link, in the master clock that the first determination module 10 is determined, select the highest master clock of priority as primary master clock, wherein the clock transfer link has many, correspond respectively to a plurality of master clocks, be used between each master clock of clock and a plurality of master clocks, carrying out clock transfer; Executive Module 30 is connected to and selects module 20, is used for using the primary master clock of selecting module 20 to select to carry out clock synchronous.
Fig. 6 is the structured flowchart of clock synchronization apparatus according to the preferred embodiment of the invention, and as shown in Figure 6, clock synchronization apparatus also comprises: receiver module 40 is used for receiving respectively the notification packet from a plurality of master clocks; Monitoring modular 50 is connected to receiver module 40, is used for monitoring according to the notification packet that receiver module 40 receives the clock quality of a plurality of master clocks.
Preferably, clock synchronization apparatus also comprises: the second determination module 60, be connected to receiver module 40, and be used for the packet loss situation according to the notification packet that passes through the reception of clock transfer link of receiver module 40 receptions, determine the priority of clock transfer link.
Preferably, this clock synchronization apparatus can also be used for:
(1) setting is higher than the priority that does not have the master clock of corresponding relation with self with the priority of the master clock that self has corresponding relation, and wherein corresponding relation is to arrange according to the network topology from clock and a plurality of master clocks.
(2) from clock the master clock of determining, determine that master clock except primary master clock is as master clock for subsequent use.
(3) determine that the clock quality of primary master clock is inferior to the clock quality of self, determine that perhaps clock transfer link corresponding to primary master clock is unavailable; Be used for the priority according to the clock transfer link, in master clock for subsequent use, select the highest master clock of priority as new primary master clock; Be used for using new primary master clock to carry out clock synchronous.
(4) determine that from clock the clock quality of primary master clock is better than the clock quality of self, and definite clock transfer link corresponding to primary master clock can be used; Be used for recovering to use primary master clock to carry out clock synchronous.
The various embodiments described above specify the mode of master clock link priority to distinguish primary and backup clock chain circuit by configuration, and the quality of in conjunction with the foreground master clock link of all configurations being carried out MASTER self clock corresponding to link quality condition detection and each link simultaneously realizes backup and the load sharing function of master clock.The embodiment of the invention provides between a kind of a plurality of MASTER the method as active and standby master clock server and load sharing; So, can alleviate on the one hand the load of certain MASTER, so that it provides synchronous service better more accurately for SLAVE; On the other hand, for SLAVE equipment, also can improve the reliability of its synchronizing process.By said method and device, can avoid all to use same master clock to carry out clock synchronous from clock, alleviated the load of this master clock, improved the overall performance of system.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with general calculation element, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in the storage device and be carried out by calculation element, perhaps they are made into respectively each integrated circuit modules, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. clock synchronizing method is characterized in that comprising:
A plurality of master clocks, determine that clock quality is better than the master clock of self from clock;
Priority according to the clock transfer link, in described definite master clock, select the highest master clock of described priority as primary master clock, wherein said clock transfer link has many, correspond respectively to described a plurality of master clock, be used between each master clock of clock and described a plurality of master clocks, carrying out clock transfer described;
Use described primary master clock to carry out clock synchronous.
2. method according to claim 1 is characterized in that, from clock a plurality of master clocks, determine that clock quality is better than also comprising before the master clock of self:
Describedly receive respectively notification packet from described a plurality of master clocks from clock;
Monitor the clock quality of described a plurality of master clocks according to described notification packet.
3. method according to claim 1, it is characterized in that, in the priority according to the clock transfer link, in described definite master clock, select the highest master clock of described priority as primary master clock before, also comprise: described from the packet loss situation of clock according to the notification packet that receives by described clock transfer link, determine the priority of described clock transfer link.
4. method according to claim 1, it is characterized in that, in the priority according to the clock transfer link, in described definite master clock, select the highest master clock of described priority as primary master clock before, also comprise: described from clock setting and self exist the priority of the master clock of corresponding relation to be higher than the priority that does not have the master clock of corresponding relation with self, wherein said corresponding relation is to arrange according to described network topology from clock and described a plurality of master clocks.
5. each described method in 4 according to claim 1, it is characterized in that, in the priority according to the clock transfer link, in described definite master clock, select the highest master clock of described priority as primary master clock after, also comprise: described from clock described definite master clock, determine that master clock except described primary master clock is as master clock for subsequent use.
6. method according to claim 5 is characterized in that, after the described primary master clock of use carries out clock synchronous, also comprises:
Describedly determine that from clock the clock quality of described primary master clock is inferior to the clock quality of self, determine that perhaps clock transfer link corresponding to described primary master clock is unavailable;
According to the priority of clock transfer link, in master clock for subsequent use, select the highest master clock of described priority as new primary master clock;
Use described new primary master clock to carry out clock synchronous.
7. method according to claim 6 is characterized in that, after the described new primary master clock of use carries out clock synchronous, also comprises:
Describedly determine that from clock the clock quality of described primary master clock is better than the clock quality of self, and determine that clock transfer link corresponding to described primary master clock can use;
Recover to use described primary master clock to carry out clock synchronous.
8. clock synchronization apparatus is characterized in that comprising:
The first determination module is used at a plurality of master clocks, determines that clock quality is better than the master clock of self;
Select module, be used for the priority according to the clock transfer link, in described definite master clock, select the highest master clock of described priority as primary master clock, wherein said clock transfer link has many, correspond respectively to described a plurality of master clock, be used between each master clock of clock and described a plurality of master clocks, carrying out clock transfer described;
Executive Module is used for using described primary master clock to carry out clock synchronous.
9. device according to claim 8 is characterized in that, described clock synchronization apparatus also comprises:
Receiver module is used for receiving respectively the notification packet from described a plurality of master clocks;
Monitoring modular is for the clock quality of monitoring described a plurality of master clocks according to described notification packet.
10. device according to claim 8 is characterized in that, described clock synchronization apparatus also comprises:
The second determination module is used for the packet loss situation according to the notification packet that receives by described clock transfer link, determines the priority of described clock transfer link.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105515752B (en) * | 2015-12-07 | 2018-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method of data synchronization for eliminating network clocking deviation |
| CN106899370A (en) * | 2015-12-18 | 2017-06-27 | 中兴通讯股份有限公司 | A kind of clock chain circuit changing method, device and base station |
| CN111404627A (en) * | 2019-01-02 | 2020-07-10 | 中国移动通信有限公司研究院 | Time synchronization method, device, system and storage medium |
| CN112350951A (en) * | 2019-08-09 | 2021-02-09 | 诺基亚通信公司 | PTP clock and method for load bearing processing |
| CN112350951B (en) * | 2019-08-09 | 2024-01-26 | 诺基亚通信公司 | PTP clock and method for load bearing processing |
| CN113556221A (en) * | 2020-04-23 | 2021-10-26 | 西门子股份公司 | Method and device for timing in redundant network |
| WO2022067732A1 (en) * | 2020-09-30 | 2022-04-07 | Zte Corporation | Methods, systems and apparatuses for 5g time synchronization |
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