CN103066552B - Control method for avoiding false switching-on of breaker and circuit thereof - Google Patents
Control method for avoiding false switching-on of breaker and circuit thereof Download PDFInfo
- Publication number
- CN103066552B CN103066552B CN201210579911.5A CN201210579911A CN103066552B CN 103066552 B CN103066552 B CN 103066552B CN 201210579911 A CN201210579911 A CN 201210579911A CN 103066552 B CN103066552 B CN 103066552B
- Authority
- CN
- China
- Prior art keywords
- circuit
- signal
- clock signal
- breaker
- point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
Abstract
The invention discloses an operation and a device for deciding whether a breaker is allowed to switch on or not and whether a switch-on operation is allowed or not by detecting whether a short trouble exists in a load circuit line. The invention provides a control method and a circuit which can detect situations of the load circuit line without exerting of dangerous voltages, can prevent the breaker from falsely switching on under a short-circuit condition of the load circuit line and can fundamentally avoid impact accidents of oversized currents. The device comprises a power source supply circuit, a sequential control circuit, a detection and stoppage sampling circuit and a breaker drive circuit. The detection and stoppage sampling circuit detects the load circuit line: if the load circuit line is normal, the breaker is allowed to drive the circuit to switch on; if short trouble is detected, the breaker is locked and not allowed to drive the circuit to switch on. The device and the method have the advantages of being able to automatically be unlocked after the load circuit line is regular and being able to be used repeatedly. The device and the method have a safe effect of directly or partially preventing a mains supply from adding in the load circuit line to avoid hidden dangers.
Description
Technical field
the invention belongs to the Method and circuits that a kind of breaker closing controls, relate to a kind of detection loaded line that passes through and whether there is short trouble and determine whether allow breaker closing and perform the operation and device of closing a floodgate.More specifically, be that one need not apply dangerous voltage, still can find out the situation of loaded line, and then prevent circuit breaker from closing a floodgate mistakenly under loaded line short trouble state, fundamentally stop control method and the circuit of the appearance of super-large current impact accident.
circuit breaker closes a floodgate mistakenly under line short malfunction, is referred to as " false switching ".
prevent the measure of circuit breaker false switching, be referred to as " anti-error closing ".
Background technology
in prior art, the electronic installation that breaker closing controls is existing a lot, and function is also more and more complete, but circuit also becomes increasingly complex.How to adopt the structure of simple step and low cost to realize perfect control, become the target that industry technical staff pursues.
in existing apparatus, employing is had to be detected loaded line to loaded line input civil power by series resistor device.This itself just exists a kind of dangerous: these devices are under circuit breaker disjunction state, and do not make load thoroughly depart from electrical network, part line voltage is applied on loaded line, thus there is the major safety risks problem of equipment live in person electric shock and loaded line.
in addition, in existing apparatus, also have and adopt direct sensing lead circuit DC resistance.Often have a lot of inductive and capacitive load due to reality by electric line, DC resistance can not the actual impedance of reflected load circuit, and thus this method can produce very large error.
Summary of the invention
the Method and circuits that the present invention creates, before being the breaker closing being in disjunction state in supply line, first detects loaded line; If find between detection period, loaded line is normal, then allow breaker closing; And once short trouble be detected between detection period, lock, do not allow breaker closing, namely there is the effect of monitoring loaded line fault. at once
this breaker misoperation-preventing shutting-brake control method and circuit, attempting, to originally the start time that the loaded line that there is short trouble closes a floodgate again once being detected, will again to detect loaded line; If find, loaded line is replied normal, then can unlock original lock-out state.
first this method and circuit confirm that circuit breaker is in disjunction state before detection, and allow test section exit before guaranteeing combined floodgate, thus can ensure that extraneous power supply can not have an impact to test section and damage.
therefore, the object of invention be to provide a kind of prevent that circuit breaker from closing a floodgate under loaded line exists short trouble or serious extra-heavy situation, after loaded line is normal can automatic unlocking so that the breaker misoperation-preventing shutting-brake control Method and circuits of Reusability.
inventing further object is, above-mentioned basis provides a kind of detection method to loaded line that extraneous power supply can not have an impact to test section that can ensure, thus fundamentally stop due to when detecting by civil power directly or part add loaded line and the potential safety hazard that produces.
inventing further object is, above-mentioned basis provides a kind of detection method adopting the test signal identical with mains frequency, thus makes testing result close to the virtual condition of loaded line.
method of the present invention is achieved in that
a kind of breaker misoperation-preventing shutting-brake control method, the steps include:
(1) produce that frequency is identical with utility grid frequency by a power-frequency voltage peak value constant circuit, voltage peak is by the constant test signal that mains ripple affects;
(2) differentiate that circuit breaker is in disjunction state or on-state by a reset licensed circuit, and only under circuit breaker is in disjunction state, just allow reset circuit action;
(3) when the licensed action of reset circuit, when manually by logical reset button, send the first clock signal T1 and the second clock signal T2 by a sequence circuit simultaneously, wherein, the second clock signal length t2 > first clock signal length t1;
(4) while producing according to the second clock signal T2, by a taboo lock circuit disables circuit breaker drive circuit feed motion;
(5), while producing according to the first clock signal T1, a sample circuit is made to access loaded line by a detection executive circuit;
(6) after sample circuit access loaded line, within the time of the first clock signal T1, the output signal of sample circuit is processed by a testing circuit, and export its result to lock solution circuit: when circuit is normal, export unlocking signal; And once find that circuit exists short trouble, then export locking signal immediately;
(7), while producing according to the second clock signal T2, a pulse signal is produced by an impulse circuit;
(8) lock separates circuit according to the unlocking signal from testing circuit input, forms the control signal allowing to close a floodgate under the effect of above-mentioned pulse signal, or forms the control signal not allowing to close a floodgate according to the locking signal from testing circuit input;
(9), while terminating according to the first clock signal T1, detect executive circuit and make sample circuit depart from loaded line;
(10), while terminating according to the second clock signal T2, prohibit lock circuit and no longer forbid the action of circuit breaker drive circuit;
(11) after the second clock signal T2 terminates, combined floodgate drive circuit separates the permission energization control signal of circuit according to lock, the motor-operating mechanism of circuit breaker is carried out to the control of feed motion.
like this, between detection period, when loaded line is normal, output is represented the normal signal of circuit by testing circuit, and provide unlocking signal to lock solution circuit accordingly, so lock is separated circuit and is just exported a signal allowing to close a floodgate, and combined floodgate drive circuit can make breaker closing with rear drive motor-operating mechanism.
simultaneously, between detection period, any instant is once find that loaded line exists short trouble, testing circuit represents the signal of line fault by exporting, and provide a locking signal to lock solution circuit accordingly, lock is separated circuit and is just exported a signal not allowing to close a floodgate no longer changed, and circuit breaker drive circuit just can not make breaker closing.Therefore, lock is separated circuit and is had the effect of monitoring the signal of fault sample circuit output, and has the function of locking fault.
moreover pulse signal produced in the moment that the second sequential T2 produces, and work according to the signal of testing circuit output.When circuit is normal, unlocking signal makes pulse signal act on lock solution circuit and makes its state that unlocks.Therefore, when detecting beginning, namely there is the function that the loaded line after to failture evacuation identifies again.
further, during whole second clock signal T2, all forbid circuit breaker drive circuit feed motion due to prohibiting lock circuit, and the second clock signal length t2 > first clock signal length t1; And sample circuit accesses loaded line when the first clock signal T1 produces, at the end of T1, sample circuit departs from loaded line, namely sample circuit just can access when loaded line departs from civil power completely, and circuit breaker can not carry out feed motion during sample circuit access loaded line, therefore, it is possible to ensure that sample circuit can not be subject to the impact of mains supply.
it is desirable to, in said method step (6), be provide that one that with electrical network isolate, voltage very low and peak value constant by a sample resistance to a tetrapolar input by a power-frequency voltage peak value constant circuit, waveform is close to the power frequency test voltage of square wave; Tetrapolar output is connected with loaded line; the characteristic impedance of four-terminal network input and the reflected umpedance of four-terminal network output define a parallel impedance Z0 thus; this impedance and sample resistance are contacted; and another input tetrapolar is connected on power-frequency voltage peak value constant circuit and forms loop; sampled signal is drawn by the tie point of parallel impedance Z0 and sample resistance; as the output signal of sample circuit, thus obtain the signal representing the normal or short trouble of loaded line.
thus obtained method, directly or partly need not add loaded line by civil power during detection, thus the potential safety hazard can fundamentally stopped to apply dangerous voltage in loaded line and may cause.
circuit of the present invention is achieved in that
a kind of breaker misoperation-preventing contacting controling circuit, is characterized in, comprises:
a power-frequency voltage peak value constant circuit, produces that frequency is identical with utility grid frequency, voltage peak is by the constant test signal that mains ripple affects;
a reset licensed circuit is be in disjunction or on-state according to circuit breaker, differentiates license or forbids reset circuit action;
a reset circuit, comprises a reset button for operating;
a sequence circuit, produces the first clock signal T1 and the second clock signal T2 while reset operation, wherein, and the second clock signal length t2 > first clock signal length t1;
a detection executive circuit, produces according to the first clock signal T1 or terminates, and sample circuit is accessed or departs from loaded line;
described sample circuit, during making it access loaded line, produces a sampled signal Ut be closely related with loaded line impedance according to detection executive circuit;
a testing circuit, carries out differentiation process and separates circuit to a lock exporting its result P to the sampled signal Ut that sample circuit exports: when loaded line is normal, export unlocking signal, when once find that loaded line exists short trouble, namely export locking signal;
a taboo lock circuit, according to during the second clock signal T2, No switching on drive circuit feed motion;
an impulse circuit, while producing, produces a pulse signal according to the second clock signal T2;
circuit separated by described lock, according to the unlocking signal that testing circuit exports, under the effect of the pulse signal of impulse circuit, remove the lock-out state that originally perhaps existed and form the control signal allowing to close a floodgate, or form according to the locking signal that testing circuit exports the control signal that do not allow to close a floodgate and locked;
described combined floodgate drive circuit, the control signal of closing a floodgate according to the permission of separating circuit input from lock and the end according to the second clock signal T2, carry out the control of feed motion to the motor-operating mechanism of circuit breaker.
by the cooperation of foregoing circuit, method of the present invention can be realized.
in above-mentioned sample circuit, comprise four-terminal network and sample resistance.Tetrapolar output and input are structurally highly withstand voltage insulation.Tetrapolar output connects loaded line between detection period, and now the impedance of its comprehensive impedance and loaded line is closely related.According to four-terminal network principle, four-terminal network output defines parallel impedance Z0 to the reflected umpedance of input and the characteristic impedance of four-terminal network input, and power-frequency voltage peak value constant circuit injects constant test signal to sample resistance and tetrapolar input, so just create the voltage sampling signal with loaded line impedance tight association on parallel impedance Z0.
because the sample circuit and electrical network that access loaded line between detection period are completely isolated, therefore, it is possible to accomplish to be perfectly safe to user, though solve detect in the past in the security hidden trouble that still exists with dangerous voltage of circuit breaker disjunction but loaded line.
meanwhile, test signal during detection is from power frequency constant pressure source, and its frequency is consistent with the actual operating frequency of line load, thus improves the degree of approximation and the credibility of testing result.
method and circuits of the present invention, its step is simply effective, and controls perfect, and the structure of related circuit is also comparatively simple.
drawing explanation
fig. 1 is the present invention's " breaker misoperation-preventing shutting-brake control method realizing circuit " block diagram;
fig. 2 is the level waveforms figure of power-supply circuit schematic diagram (comprising regulator rectifier circuit, power-frequency voltage peak value constant circuit) and each contact;
fig. 3 is the level waveforms figure of sequential control circuit schematic diagram (comprising reset licensed circuit, reset circuit, sequence circuit) and each contact;
fig. 4 be detect and under fault sample circuit schematic diagram (comprise detect executive circuit, sample circuit, testing circuit) and load normal condition with the level waveforms figure of each contact under load short circuits state;
fig. 5 is that the combined floodgate under circuit breaker driving circuit principle figure (comprise and prohibit lock circuit, impulse circuit, lock solution circuit, combined floodgate drive circuit) and normal condition drives, the level waveforms figure of each contact when resetting after locking under load short circuits fault and failture evacuation;
fig. 6 is the complete circuit schematic diagram of breaker misoperation-preventing shutting-brake control method implement device.
Embodiment
below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail:
1, power-supply circuit
power-supply circuit comprises regulator rectifier circuit, power-frequency voltage peak value constant circuit.With reference to Fig. 2.
(1.1) regulator rectifier circuit
be with centre tapped low-voltage secondary winding BR1, diode D1, D2, D3, D4, three proper Voltagre regulator W1, three end negative voltage pressurizer W2, electric capacity C1, C2, C3, C4 to form, provide symmetrical positive Vc, negative Vs working power to whole device for one by power transformer B1.This circuit is conventional serial regulating circuit, and the course of work illustrates to be omitted.
(1.2) course of work of power-frequency voltage peak value constant circuit:
power-frequency voltage peak value constant circuit is made up of another low-voltage secondary winding BR2, the resistance R1 of power transformer B1, voltage stabilizing didoe WD1, WD2.
(1.2.a) a low-voltage secondary winding BR2 of power transformer B1 exports the power-frequency voltage Y of an a few volt, through resistance R1 current limliting, after the two-way slicing of voltage stabilizing didoe WD1, WD2 docked in opposite directions, form that one that be limited, close to the power frequency low-voltage of square wave, this voltage is using the test signal L as this method.Voltage stabilizing value due to voltage stabilizing didoe WD1, WD2 of selecting is only the part of the peak value of power-frequency voltage Y, even if therefore supply power voltage is fluctuating in a big way, the waveform of test signal L and peak value still can substantially constants, so just ensure that the stability and consistency that detect loaded line.
(1.2.b) power transformer B1 has high dielectric strength, and therefore test signal L has good isolation to electrical network.
, sequential control circuit
sequential control circuit comprises reset licensed circuit, reset circuit, sequence circuit.With reference to Fig. 3, adopt CD40106 by this example of cmos schmitt inverter U1A, U1B, U1C, U1D, U1E, U1F() and Fig. 3 shown in peripheral element form.
(2.1) course of work of reset licensed circuit:
reset licensed circuit is made up of optical coupler G1, diode D5, resistance R2, R3, R4, electric capacity C5, C6, button K.
(2.1.a) when circuit breaker is in "on" position, output and loaded line two ends Lo, No of circuit breaker have line voltage, after C5 step-down, the conducting of D5 half-wave, R2 current limliting, C6 filtering, optical coupler G1 input obtains positive incentive and makes output conducting, so the input of B point and inverter U1A is by the positive voltage Vc of pincers due to working power, even if reset switch K is by logical, the high level of B point also can not change.Now, be in and do not allow reset mode, reset switch can not cut any ice.
(2.1.b) when circuit breaker is in disjunction state, Lo, No do not have voltage, and optical coupler G1 input does not encourage, output cut-off, and B point is driven high to Vc by R4.Now, permission reset mode is in.B level point will depend on reset switch K whether by by logical:
when allowing reset, K logical: Rk=∞, Vc=+5V, Vs=-5V, then VB=+5V;
allow reset, K by time logical: Rk=0, Vc=+5V, Vs=-5V, then VB=-4V.
(2.2) course of work of reset circuit:
reset circuit is made up of inverter U1A, U1B, resistance R5, R6.
(2.2.a) not allowing to reset or allow to reset reset switch K not by by under logical state, the input of inverter U1A and B level point are the high level (hereinafter referred to as " height ") close to Vc, now the output of inverter U1A and C level point are the low level (hereinafter referred to as " low ") close to Vs, so the input of inverter U1B is also low, the output of U1B and D level point are high thus, are maintained the high level of B point by R5 further.
(2.2.b) when allowing to reset and reset switch K is pressed connection, B level point is down to negative level as previously mentioned, so inverter U1A output and the saltus step of C level point are high, the input making inverter U1B by resistance R6 is also for high, and the output of U1B and D level point become and be low to moderate close to Vs thus.Now, make it to disconnect even if decontrol reset switch K, B level point still can maintain negative level:
(2.3) course of work of sequence circuit:
sequence circuit is made up of inverter U1C, U1D, U1E, U1F, diode D6, D7, D8, resistance R7, R9, electric capacity C7, C8.At C point acquisition first clock signal T1, T1 is that high level is effective within its length t1 time.At J point acquisition second clock signal T2, T2 is Low level effective within its length t2 time.
, R10 is the input resistance of CMOS comparator U1C, U1E, only shield.
(2.3.a) as previously mentioned, not allowing to reset or allow to reset, reset switch K is not by by under logical state, and B point is height, C point is low.Now diode D6 forward conduction, E level point is dragged down, the output F point of U1C is high, and thus diode D7 is oppositely cut-off.Meanwhile, the output G point of U1D is high, and the input H point of U1E is also high, and the output I point of U1E is low, and the output J point of U1F is high.Now, the first clock signal and the second clock signal all do not produce.
(2.3.b) as previously mentioned, after permission resets and reset switch K is pressed connection, because B point becomes and maintains low level, therefore inverter U1A output and the saltus step of C level point are high and maintain, now diode D6 oppositely ends, the high voltage of U1A output is charged to electric capacity C7, so E point voltage raises gradually thereupon by resistance R7; After certain hour, E point voltage is raised above 0 level and continues to rise.Namely the first clock signal T1 is obtained thus at C point.
(2.3.c) as previously mentioned, while the saltus step of C level point is high also maintenance, the output G point step-down of comparator U1D, diode D8 forward conduction, makes that electric capacity C8 thoroughly discharges, H point step-down, and the output I point of U1E uprises, the input of U1F also uprises, so the output J point step-down of U1F.Namely the second clock signal T2 is obtained thus at J point.
(2.3.d) when E point voltage continuation rising reaches the forward breakover threshold values of schmitt inverter U1C, the output F point saltus step of U1C is low; Now diode D7 forward conduction, makes the input level of U1B be dragged down rapidly, so the output of U1B and the saltus step of D level point are high, B level point is no longer maintained at low and uprises thus.Like this, the output of U1A and C point fall after rise to low.So far, the first clock signal T1 terminates.Resistance R7 and electric capacity C7 constitutes an integrating circuit, and its time constant determines the time of this process, namely determines the length t1 of the first clock signal T1.
(2.3.e) while the falling of C point is extremely low, diode D6 conducting, makes C7 discharge rapidly, and E level point is dragged down, so F level point uprises, and the state that reset circuit is returned to (2.2.a).
(2.3.f) while the falling of C point terminates to low, the first clock signal T1, comparator U1D output G point uprises, and now diode D8 ends, and the high voltage of G point is charged to electric capacity C8, so H point voltage raises gradually thereupon by resistance R9; Similar to R7, C7, resistance R9 and electric capacity C8 also constitutes an integrating circuit.After certain hour, H point voltage is raised above 0 level and continues to rise.Now I point is still that height, J point are also still for low.That is, the second clock signal T2 is still in continuity.
(2.3.g) when H point voltage continuation rising reaches the forward breakover threshold values of schmitt inverter U1E, the output I point saltus step of U1E is output J point saltus step that is low, U1F is height.So far, the second clock signal T2 terminates.Obviously, such circuit structure, ensure that the length t2 of the second clock signal T2 is longer than the length t1 of the first clock signal T1, and the time extended depends on the time constant of the integrating circuit that resistance R9 and electric capacity C8 form.
so far, whole sequential control circuit is returned to original state.
, detect and fault sample circuit
detection and fault sample circuit comprise detection executive circuit, sample circuit, testing circuit.With reference to Fig. 4, the low maladjustment voltage integrated comparator adopting open collector to export by this example of comparator U2, U3, U4(, as LM139/239/339 series, lower with) and Fig. 4 shown in peripheral element form.
(3.1) course of work of executive circuit is detected:
detect executive circuit to be made up of comparator U4 and relay J 1, and two of relay J 1 moving contacts are connected on the output of four-terminal network B2, two corresponding fixed contacts are connected to loaded line two ends.The in-phase input end of comparator U4 connects 0 level.
(3.1.a) the first clock signal T1 accesses the inverting input of comparator U4, i.e. C point.This o'clock is negative level before the first clock signal T1 arrives or after terminating, therefore the output of U4 is cut-offs in these times, and now K level point is high, thus relay J 1 not excitation, contact disconnects, and the voltage transformer B2 of sample circuit and loaded line depart from.
(3.1.b) during the first clock signal T1 arrives, namely in the t1 time, the level of the inverting input of comparator U4 and C point is high, so the output of comparator U4 is to Vs conducting, now K level point is low to moderate close to Vs, relay J 1 obtains the excitation of Vc and Vs, two groups of contactings, and the voltage transformer B2 of sample circuit is connected with loaded line.
(3.2) course of work of sample circuit:
sample circuit by as tetrapolar low magnetic leakage high permeability iron core double winding voltage transformer B2(hereinafter referred to as " four-terminal network B2 ") form with sample resistance R11.Four-terminal network B2 output defines parallel impedance Z0(hereinafter referred to as " impedance Z 0 " to the reflected umpedance of input and the characteristic impedance of four-terminal network B2 input).
(3.2.a) power-frequency voltage peak value constant circuit is injected close to the constant test signal L of the peak value of square wave to the input of four-terminal network B2 by sample resistance R11.Due to the existence of impedance Z 0, just sampled signal Ut can be obtained from the tie point of four-terminal network B2 and sample resistance R11; Again because impedance Z 0 is inductive, thus Ut form respectively spike at rising edge and trailing edge, and its cycle is 20ms.The waveform of Ut is shown in Fig. 4.
(3.2.b), before the first clock signal T1 arrives or after terminating, the contact due to relay J 1 is the output open circuit of disconnection, four-terminal network B2, and impedance Z 0 is maximum, and therefore the peak value of sampled signal Ut is maximum.
(3.2.c) during the first clock signal T1 arrives, the contact of relay J 1 connects, and the output of four-terminal network B2 is connected with loaded line, and impedance Z 0 will diminish; Line load is heavier, and impedance Z 0 is less.The peak value of sampled signal Ut presents synchronous change along with the change of impedance Z 0; If loaded line short circuit, then impedance Z 0 is by minimum, and now, the peak value of sampled signal Ut is also minimum.Fig. 4 is shown in the change of sampled signal Ut waveform.
(3.3) course of work of testing circuit:
testing circuit is made up of comparator U2, U3 and resistance R12, R13, R14, R15 and electric capacity C9.This circuit to sampled signal Ut process, and forms unlocking signal or locking signal at the output P point of comparator U3.
(3.3.a) in-phase input end that resistance R12, R13 is comparator U2 provides an offset voltage Vt.Input due to four-terminal network B2 is a coil, and its D.C. resistance is negligible, therefore:
Vt＝Vc·R12/(R13＋R12)
by becoming this testing circuit, this offset voltage Vt, differentiates whether loaded line exists the threshold value of short trouble or serious excess load.By the size of adjusting resistance R12, R13, the height of this threshold value can be selected, thus determine the sensitivity of this testing circuit; The value of Vt is less, then allow the load of circuit heavier.
(3.3.b) sampled signal Ut enters the in-phase input end of comparator U2 by resistance R12, i.e. M point.Due to the existence of offset voltage Vt, Ut is the level of Vt value by integral raising.The waveform of M point is shown in Fig. 4.
(3.3.c) the anti-phase input termination public zero of comparator U2; The output of comparator U2 and N point are connected to resistance R14 to Vc, electric capacity C9 to public zero, constitute an integrating circuit.The numerical value suitably choosing resistance R14 and electric capacity C9 makes the time constant of its this integrating circuit be enough multiples in power frequency 20ms cycle.When M point is positive level, the output cut-off of U2, Vc is charged to electric capacity C9 by resistance R14, and N point voltage raises gradually; When M point is negative level, the output conducting of U2, electric capacity C9 discharges rapidly and makes N level point close to Vs.
if (3.3.d) line load is normal, or the output of four-terminal network B2 is not access in loaded line and opens a way, by integral raising, the negative peak of the Ut of Vt level can be offset Vt and cross 0 level at M point and define a string negative pulse, it makes the output of comparator U2 by the cycle conducting of 20ms, the electric capacity C9 periodically charged by R14 due to the periodicity cut-off of U2 between each pulse is periodically discharged rapidly, although so the waveform of N point has zigzag fluctuation, its level is in negative level all the time.
if (3.3.e) loaded line short circuit, then, during the first clock signal T1 arrives, the peak value of sampled signal Ut becomes minimum.Suitably choose the size of resistance R12, R13 and set Vt, just make by integral raising the negative peak of the sampled signal Ut of Vt level under loaded line short-circuit conditions can not surmount this threshold value of Vt and be in positive level all the time, therefore the output of comparator U2 ends all the time, electric capacity C9 is continuously charged, so the level of N point just rises to positive level very soon.
(3.3.f) in-phase input end of comparator U3 connects public zero, anti-phase input termination N point.When the level of N point is in negative level, when namely line load output that is normal or four-terminal network B2 is not access in loaded line, the output cut-off of comparator U3, P point is pulled to the high level close to Vc by R15.When the level of N point is in positive level, namely line load be short circuit or serious excess load time, the output conducting of comparator U3, P point is pulled down to the low level close to Vs.
as mentioned above, during the first clock signal T1, when loaded line is normal, become the unlocking signal of high level toward the signal of circuit breaker drive circuit from the extraction of P point; When loaded line exists short trouble or serious excess load, this signal becomes low level locking signal.
, circuit breaker drive circuit
circuit breaker drive circuit comprises prohibits lock circuit, impulse circuit, lock solution circuit, combined floodgate drive circuit.With reference to Fig. 5, be made up of peripheral element shown in comparator U5, U6, U7 and Fig. 5.
(4.1) course of work of lock circuit is prohibited
prohibit lock circuit to be made up of diode D13, resistance R21.
(4.1.a) negative pole of diode D13 is connected to the output point J of the second clock signal T2 of sequential control circuit.Before T2 produces and after terminating, J point is in high level, and diode D13 ends, and resistance R21 pull-up makes the input V point of combined floodgate drive circuit be in high level.
(4.1.b) because the second clock signal T2 is that negative level is effective, so in the T2 duration, diode D13 forward conduction, makes V point voltage by clamp extremely close to Vs; So the coupling capacitance C11 two ends of combined floodgate drive circuit are all stable low levels, combined floodgate drive circuit all can not be encouraged within the t2 time of whole second clock signal, and thus feed motion is prohibited.
(4.2) course of work of impulse circuit
impulse circuit is made up of comparator U6, diode D14, resistance R19, R20, electric capacity C10.The in-phase input end of comparator U6 connects 0 current potential.
(4.2.a) at ordinary times, the inverting input of comparator U6 and S point are pulled to high level by resistance R19, therefore U6 output conducting and be in low level.
(4.2.b) electric capacity C10 and resistance R19 forms a differential circuit, and electric capacity C10 is connected to the output point J of the second clock signal T2 of sequential control circuit.In the moment that T2 arrives, one end of electric capacity C10 obtains a negative sense leaping voltage, so the S point formation negative sense differentiated pulse be connected with resistance R19 at electric capacity C10 also puts on the inverting input of comparator U6, thus the output cut-off of comparator U6, due to the pull-up effect of resistance R20, just create a direct impulse U.The width of pulse U depends on the time constant of the differential circuit that resistance R19 and electric capacity C10 forms.
(4.2.c) at the end of the second clock signal T2, S point can produce a positive transition voltage; Due to the electric discharge of electric capacity C10, the peak value of this voltage can be nearly more than Vc one times, and comparator U6 may be made to cause damage.For this reason, be provided with the diode D14 being parallel to resistance R19, this positive transition voltage clamp at Vc, play the protective effect to comparator U6.
(4.3) course of work of circuit separated by lock
lock is separated circuit and is made up of comparator U5, diode D9, D10, D11, D12, light-emitting diode L1, resistance R16, R17, R18.The negative-phase input of comparator U5 connects 0 current potential.
(4.3.a) negative pole of diode D9 is connected to the P point of testing circuit.As previously mentioned, when loaded line is normal, the signal of P point is the unlocking signal of high level, thus diode D9 ends, the in-phase input end of comparator U5 and Q point are pulled to high level by resistance R16, R17, so the output cut-off of U5, T point is pulled to high level by resistance R18, light-emitting diode L1.Now, diode D10 is also cut-off.
(4.3.b) when loaded line exists short trouble or serious excess load, during the first clock signal T1, the signal of P point becomes low level locking signal, now diode D9 conducting and make R point for low level, Q point is made also to be low level after the direct impulse U from impulse circuit by resistance R17, so the output conducting of U5, T level point is low to moderate close to Vs; Now, diode D10 conducting, makes R point be clamped at low level.Meanwhile, the low level of T point makes diode D11 forward conduction, so the input V point of combined floodgate drive circuit is also clamped at low level.
(4.3.c) under above-mentioned state, light-emitting diode L1 is luminous by resistance R18 current limliting, thus sends the alarm that loaded line exists short trouble or serious excess load.
(4.3.d) the first clock signal T1 terminates rear, low level locking signal elimination, and P point returns back to high level, but ends because diode D9 replys, and the low level of R point will be still constant.So the input V point of the in-phase input end Q point of U5, output T point, combined floodgate drive circuit is all still in low level.
even if (4.3.e) the second clock signal T2 also terminates, J point becomes high level, and the diode D13 prohibiting lock circuit now oppositely ends, but makes diode D11 forward conduction due to the low level of T point, and therefore V point is still in low level.That is, once low level locking signal appears in P point, lock solution circuit just enters a stable lock-out state.Change the in-phase input end of comparator U5 and the low level of Q point as long as no other factor, this state will maintain down always, and its result is exactly that the input V point of combined floodgate drive circuit is locked in low level.
(4.3.f) to the fault of the short circuit of loaded line or serious excess load after maintenance, reset button can be operated and carry out new one and take turns to close a floodgate and attempt.As described in the course of work of front (4.2) impulse circuit, when reset button is pressed, namely in the moment that the second clock signal T2 produces, impulse circuit forms a direct impulse U, be applied to in-phase input end and the Q point of comparator U5 by diode D12, now, the output of comparator U5 ends during pulse U, T point becomes high level during this period, so diode D10 also ends during pulse U.
if (4.3.g) fault of loaded line short circuit or serious excess load after maintenance is got rid of not yet, then during the first clock signal T1, P point still can obtain a low level locking signal, so circuit separated by lock will repeat above-mentioned (4.3.b) to the process of (4.3.e), again locks.
if (4.3.h) loaded line recovers normal after maintenance, so the signal of P point is the unlocking signal of high level; Like this, after the process of above-mentioned (4.3.f), R point is pulled to high level by resistance R16, and Q point is also in high level by resistance R17, even if direct impulse U is still like this after terminating simultaneously.So lock is separated circuit and is just unlocked, and gets back to the state of above-mentioned (4.3.a).
(4.4) course of work of combined floodgate drive circuit
combined floodgate drive circuit is made up of comparator U7, diode D15, resistance R22, electric capacity C11, relay J 2.Due to conventional electric operating mechanism of circuit-breaker generally only need the output pulses of a short time to drive can to complete to detain again, the action such as combined floodgate, therefore this example only describes the combined floodgate that the contact of relay J 2 is engaged in short-term and drives process.During embody rule, the connection of its contact and the source of driving power, can refer to the operation instruction of various electric operating mechanism of circuit-breaker.
(4.4.a) in-phase input end of comparator U7 connects public zero, and inverting input and W point are access to the output and V point of prohibiting lock circuit and lock solution circuit by electric capacity C11, be pulled down to the low level close to Vs by resistance R22 simultaneously.At ordinary times, the output of comparator U7 is cut-off, and X point is high level, and relay J 2 is failure to actuate.
(4.4.b) during the second clock signal T2, owing to prohibiting the effect of lock circuit, V point is low level, and now electric capacity C11 both end voltage does not all change, and the output of U7 remains cut-off, and relay J 2 is also failure to actuate.
(4.4.c) separate circuit when lock to be locked, even if the second clock signal T2 terminates, V point is continuously low level, and therefore the output of U7 continues to be cut-off, and relay J 2 is still failure to actuate.
(4.4.d) when loaded line is normal, namely lock solution circuit is locked or has been unlocked, and at this moment T level point is high, and diode D11 ends.In the moment that the second clock signal T2 terminates, J level point jumps as height, and the diode D13 prohibiting lock circuit ends immediately, and resistance R21 charges to electric capacity C11 and draws high the level of V point.Because electric capacity C11 and resistance R22, R21 constitute a differential circuit, and the less and resistance that R22 chooses of the resistance chosen of resistance R21 is much larger than R21, so define a forward differentiated pulse at W point and put on the inverting input of comparator U7, thus the output conducting of comparator U7 is to Vs, and the time of conducting depends on the time constant of the differential circuit that resistance R21, R22 and electric capacity C11 form.Due to the conducting of comparator U7 output, relay J 2 obtains Vc, Vs excitation, and corresponding contacts action and drive electric operating mechanism of circuit-breaker, makes breaker closing.
(4.4.e) when the second clock signal T2 starts, owing to prohibiting the conducting of the diode D13 of lock circuit, V level point becomes negative, and due to the electric discharge of electric capacity C11, W point can produce a negative sense leaping voltage, and the peak value of this voltage can lower than Vs; Diode D15 is clamped at Vs this negative sense leaping voltage, plays a part protection to comparator U7.
Claims (4)
1. a breaker misoperation-preventing shutting-brake control method, the steps include:
(1) produce that frequency is identical with utility grid frequency by a power-frequency voltage peak value constant circuit, voltage peak is by the constant test signal that mains ripple affects;
(2) differentiate that circuit breaker is in disjunction state or on-state by a reset licensed circuit, and only under circuit breaker is in disjunction state, just allow reset circuit action;
(3) when the licensed action of reset circuit, when manually by logical reset button, send the first clock signal T1 and the second clock signal T2 by a sequence circuit simultaneously, wherein, the second clock signal length t2 > first clock signal length t1;
(4) while producing according to the second clock signal T2, by a taboo lock circuit disables circuit breaker drive circuit feed motion;
(5), while producing according to the first clock signal T1, a sample circuit is made to access loaded line by a detection executive circuit;
(6) after sample circuit access loaded line, within the time of the first clock signal T1, the output signal of sample circuit is processed by a testing circuit, and export its result to lock solution circuit: when circuit is normal, export unlocking signal; And once find that circuit exists short trouble, then export locking signal immediately;
(7), while producing according to the second clock signal T2, a pulse signal is produced by an impulse circuit;
(8) lock separates circuit according to the unlocking signal from testing circuit input, forms the control signal allowing to close a floodgate under the effect of above-mentioned pulse signal, or forms the control signal not allowing to close a floodgate according to the locking signal from testing circuit input;
(9), while terminating according to the first clock signal T1, detect executive circuit and make sample circuit depart from loaded line;
(10), while terminating according to the second clock signal T2, prohibit lock circuit and no longer forbid the action of circuit breaker drive circuit;
(11) after the second clock signal T2 terminates, combined floodgate drive circuit separates the permission energization control signal of circuit according to lock, the motor-operating mechanism of circuit breaker is carried out to the control of feed motion.
2. breaker misoperation-preventing shutting-brake control method according to claim 1, in step (6), described sample circuit access loaded line, mean and be connected with loaded line by tetrapolar output, and the characteristic impedance of four-terminal network input and the reflected umpedance of four-terminal network output define a parallel impedance Z0 thus, this parallel impedance Z0 and sample resistance are contacted, and another input tetrapolar is connected to power-frequency voltage peak value constant circuit, is drawn by the tie point of parallel impedance Z0 and sample resistance and output signal.
3. a breaker misoperation-preventing contacting controling circuit, is characterized in that, comprising:
A power-frequency voltage peak value constant circuit, produces that frequency is identical with utility grid frequency, voltage peak is by the constant test signal that mains ripple affects;
A reset licensed circuit is be in disjunction or on-state according to circuit breaker, differentiates license or forbids reset circuit action;
Described reset circuit, comprises a button for reset operation;
A sequence circuit, produces the first clock signal T1 and the second clock signal T2 while reset operation, wherein, and the second clock signal length t2 > first clock signal length t1;
A detection executive circuit, produces according to the first clock signal T1 or terminates, and sample circuit is accessed or departs from loaded line;
Described sample circuit, during making it access loaded line, produces a sampled signal Ut be closely related with loaded line impedance according to detection executive circuit;
A testing circuit, carries out differentiation process and separates circuit to a lock exporting its result P to the sampled signal Ut that sample circuit exports: when loaded line is normal, export unlocking signal, when once find that loaded line exists short trouble, namely export locking signal;
A taboo lock circuit, according to during the second clock signal T2, No switching on drive circuit feed motion;
An impulse circuit, while producing, produces a pulse signal according to the second clock signal T2;
Circuit separated by described lock, according to the unlocking signal that testing circuit exports, under the effect of the pulse signal of impulse circuit, remove the lock-out state that originally perhaps existed and form the control signal allowing to close a floodgate, or form according to the locking signal that testing circuit exports the control signal that do not allow to close a floodgate and locked;
Described combined floodgate drive circuit, the control signal of closing a floodgate according to the permission of separating circuit input from lock and the end according to the second clock signal T2, carry out the control of feed motion to the motor-operating mechanism of circuit breaker.
4. breaker misoperation-preventing contacting controling circuit according to claim 3, sample circuit comprises a four-terminal network and a sample resistance, be connected with loaded line by tetrapolar output, and the characteristic impedance of four-terminal network input and the reflected umpedance of four-terminal network output define a parallel impedance Z0 thus, this parallel impedance Z0 and sample resistance are contacted, and another input tetrapolar is connected to power-frequency voltage peak value constant circuit, is drawn by the tie point of parallel impedance Z0 and sample resistance and output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210579911.5A CN103066552B (en) | 2012-12-28 | 2012-12-28 | Control method for avoiding false switching-on of breaker and circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210579911.5A CN103066552B (en) | 2012-12-28 | 2012-12-28 | Control method for avoiding false switching-on of breaker and circuit thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103066552A CN103066552A (en) | 2013-04-24 |
| CN103066552B true CN103066552B (en) | 2015-01-07 |
Family
ID=48109065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210579911.5A Expired - Fee Related CN103066552B (en) | 2012-12-28 | 2012-12-28 | Control method for avoiding false switching-on of breaker and circuit thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103066552B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107967001A (en) * | 2017-12-08 | 2018-04-27 | 广东电网有限责任公司清远供电局 | A kind of intelligent type low-voltage flood control level control system |
| CN108923375A (en) * | 2018-09-27 | 2018-11-30 | 襄阳先义电力科技有限公司 | Wireline inspection, coincidence and off device and method after a kind of tripping of line switching |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6657837B1 (en) * | 1999-12-29 | 2003-12-02 | General Electric Company | Circuit breaker incorporating fault lockout protection |
| CN101242096A (en) * | 2008-02-04 | 2008-08-13 | 南京因泰莱配电自动化设备有限公司 | Current protection control method and device |
| CN201450318U (en) * | 2009-05-20 | 2010-05-05 | 陕西扬子电力有限公司 | Automatic false ground preventive low-voltage power distribution device |
| CN102394492A (en) * | 2011-09-29 | 2012-03-28 | 安徽鑫龙电器股份有限公司 | Circuit breaker closing protection device and closing protection method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4096668B2 (en) * | 2002-09-06 | 2008-06-04 | 三菱電機株式会社 | Circuit breaker |
| JP4468316B2 (en) * | 2006-02-15 | 2010-05-26 | 株式会社日立製作所 | Overcurrent detection circuit and overcurrent detection method for power supply device |
-
2012
- 2012-12-28 CN CN201210579911.5A patent/CN103066552B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6657837B1 (en) * | 1999-12-29 | 2003-12-02 | General Electric Company | Circuit breaker incorporating fault lockout protection |
| CN101242096A (en) * | 2008-02-04 | 2008-08-13 | 南京因泰莱配电自动化设备有限公司 | Current protection control method and device |
| CN201450318U (en) * | 2009-05-20 | 2010-05-05 | 陕西扬子电力有限公司 | Automatic false ground preventive low-voltage power distribution device |
| CN102394492A (en) * | 2011-09-29 | 2012-03-28 | 安徽鑫龙电器股份有限公司 | Circuit breaker closing protection device and closing protection method |
Non-Patent Citations (3)
| Title |
|---|
| JP特开2004-103308A 2004.04.02 * |
| 一起由于电磁干扰造成断路器误合闸的事故分析;赵兵等;《广东电力》;20060831;第19卷(第8期);第52-55页 * |
| 断路器遥控回路的改进和校验;潘鹏飞等;《电力自动化设备》;20110131;第31卷(第1期);第150-152页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103066552A (en) | 2013-04-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102280862B (en) | Frequency converter input/output reverse connection detection protection method and device | |
| CN103560479A (en) | Load circuit fault detection circuit and method applied to breaker reclosing | |
| CN205665378U (en) | Relay adhesion detection circuitry | |
| CN204967236U (en) | Leakage protector | |
| CN203522122U (en) | Load line fault detection circuit applied to circuit breaker reclosing | |
| CN106655075A (en) | Electric equipment arc fault protection device and electric equipment control system | |
| CN103066552B (en) | Control method for avoiding false switching-on of breaker and circuit thereof | |
| CN104993455A (en) | Traction transformer over current protection method | |
| CN106501716B (en) | Single-phase electric meter open signal detection circuit and method based on resistance end sampling | |
| CN106099857A (en) | Detection zero-sequence current pulse width conforming ferromagnetic resonance harmonic elimination method | |
| CN203491680U (en) | Automatic reset electric leakage overvoltage/undervoltage protection circuit | |
| CN205992726U (en) | A kind of earth leakage protective device | |
| CN104377647B (en) | leakage protection circuit | |
| CN102364762B (en) | Leakage protection plug | |
| CN200953461Y (en) | Earth leakage protector | |
| CN207381953U (en) | Arc, earth leakage | |
| CN102222880B (en) | Method for identifying inrush exciting current of transformer and avoiding differential protection maloperation of transformer | |
| CN104749486A (en) | Residual current protector based IT system single-phase fault positioning method | |
| CN103001174B (en) | Detect the electric Wiring protection device of power supply false wiring condition | |
| CN205429688U (en) | Track traffic safety door electromagnetic lock short -circuit protection circuit and system | |
| CN205945024U (en) | Ferroresonance harmonic elimination device | |
| CN211127104U (en) | Circuit breaker | |
| CN108306257A (en) | Three pole break-make leakage protecting plug of intelligent control type | |
| CN207926257U (en) | A kind of power supply circuit for equipment In Oil Service Station | |
| CN207926256U (en) | A kind of power supply circuit for equipment In Oil Service Station |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150107 Termination date: 20161228 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |