CN103064801B - Termination circuit, memory system, and DC balancing method - Google Patents
Termination circuit, memory system, and DC balancing method Download PDFInfo
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Abstract
Description
技术领域 technical field
本发明有关于一种终端电路,且特别有关于终端电路与多个存储器之前进行数据传输的一种存储器系统。The present invention relates to a terminal circuit, and in particular to a memory system for data transmission between the terminal circuit and multiple memories.
背景技术 Background technique
随着系统带宽不断的增加,储存技术针对更高的速度和性能进行了优化。下一代双倍数据速率(double data rate,简称为DDR)之同步易失存储器(synchronous dynamic random access memory,简称为SDRAM)为DDR3SDRAM。DDR3 SDRAM具有比DDR2SDRAM更多的优势,例如更低的操作功率、更高的速度、更高的性能(2倍的带宽)等。具体而言,相较于DDR2 SDRAM,DDR3SDRAM降低了耗电量,其主要是由于较小的晶粒尺寸以及较低的供应电压(例如DDR3 SDRAM为1.5V而DDR2 SDRAM为1.8V)。As system bandwidth continues to increase, storage technologies are optimized for higher speed and performance. The next generation of double data rate (double data rate, referred to as DDR) synchronous volatile memory (synchronous dynamic random access memory, referred to as SDRAM) is DDR3SDRAM. DDR3 SDRAM has more advantages than DDR2 SDRAM, such as lower operating power, higher speed, higher performance (2 times bandwidth), etc. Specifically, DDR3 SDRAM reduces power consumption compared to DDR2 SDRAM, which is mainly due to smaller die size and lower supply voltage (eg 1.5V for DDR3 SDRAM versus 1.8V for DDR2 SDRAM).
同于DDR2 SDRAM的T型分支拓扑结构,DDR3 SDRAM采用了传控(fly-by)拓扑结构,其以更高的速度来提供更好的信号完整性。传控拓扑结构是应用在DDR3 SDRAM的命令、地址、控制和频率信号。来自于存储器控制器的这些信号以串联的方式连接到每个DRAM装置,因此可藉由减少分支的数量和分支的长度而改善信号完整性。Unlike the T-branch topology of DDR2 SDRAM, DDR3 SDRAM uses a fly-by topology, which provides better signal integrity at higher speeds. The control topology is the command, address, control and frequency signals applied to DDR3 SDRAM. These signals from the memory controller are connected in series to each DRAM device, thus improving signal integrity by reducing the number and length of branches.
终端电路通常会提供终端阻抗值至多个DDR3 SDRAM的共同节点,以避免造成DDR3 SDRAM的传输在线信号完整性的降低。共同节点可以在接地电位或是在接地端以及供应电压之间的一半电位,其中所需要的终端电压可调整。例如,可要求DDR SDRAM的存储器终端电路在共同节点处来提供大约相同于供应电压(例如VDD)之一半位准的终端电压。然而,传统终端电路,例如传统DDR DRAM终端电路,会导致许多缺点。The terminal circuit usually provides a terminal impedance value to the common node of multiple DDR3 SDRAMs to avoid reducing the signal integrity of the DDR3 SDRAM transmission line. The common node can be at ground potential or at half potential between ground and the supply voltage, wherein the desired terminal voltage can be adjusted. For example, the memory termination circuitry of a DDR SDRAM may be required to provide a termination voltage at a common node that is about the same as one-half level of the supply voltage (eg, VDD). However, conventional termination circuits, such as conventional DDR DRAM termination circuits, lead to many disadvantages.
在传统终端电路中,每一传输线由一驱动器所驱动,并耦接于电压调整节点。电压调整节点透过以串联方式连接的终端电阻以及终端电压调整器而耦接于接地端,其中终端电压调整器能提供与汲取电流的特别调整器。虽然终端电压调整器能在电压调整节点上提供准确的终端电压,然而终端电压调整器却是个会增加制造成本的独立组件。In conventional termination circuits, each transmission line is driven by a driver and coupled to a voltage adjustment node. The voltage adjustment node is coupled to the ground terminal through a terminal resistor connected in series and a terminal voltage regulator, wherein the terminal voltage regulator can provide and sink a special regulator of current. Although the termination voltage regulator can provide accurate termination voltage on the voltage regulation node, the termination voltage regulator is a separate component that adds to the manufacturing cost.
因此,需要一种不使用任何终端电压调整器的终端电路。Therefore, there is a need for a termination circuit that does not use any termination voltage regulator.
发明内容 Contents of the invention
有鉴于此,有必要提供不使用任何终端电压调整器的终端电路、存储器系统以及直流平衡方法。In view of this, it is necessary to provide a termination circuit, a memory system, and a DC balancing method that do not use any termination voltage regulator.
在一实施方式中,本发明提供一种终端电路,适用于传输数据。该终端电路包括多个驱动器,多个电阻以及多个电容。每一上述驱动器经由一传输线而提供数据;每一上述电阻经由对应的上述传输线而耦接于对应的上述驱动器;每一上述电容耦接于对应的上述电阻以及一参考电压之间,其中当经由对应于上述驱动器之一者的上述传输线而传送的逻辑“0”的数量与逻辑“1”的数量为不平衡时,上述驱动器之该者接收一特定码并将该特定码提供至上述传输线,以便调整对应于上述驱动器之该者的上述电容的一终端电压。In one embodiment, the present invention provides a terminal circuit suitable for transmitting data. The terminal circuit includes multiple drivers, multiple resistors and multiple capacitors. Each of the drivers provides data via a transmission line; each of the resistors is coupled to the corresponding driver via the corresponding transmission line; each of the capacitors is coupled between the corresponding resistor and a reference voltage, wherein when via When the number of logic "0"s and the number of logic "1" transmitted corresponding to the transmission line of one of the above-mentioned drivers are unbalanced, the one of the above-mentioned drivers receives a specific code and provides the specific code to the above-mentioned transmission line, In order to adjust a terminal voltage corresponding to the capacitor of the driver.
在另一实施方式中,本发明还提供一种存储器系统。该存储器系统包括终端电路、控制器、以及多个存储器。该终端电路包括:多个驱动器,其中每一上述驱动器经由一传输线而耦接于上述存储器;多个电阻,其中每一上述电阻经由对应的上述传输线而耦接于对应的上述驱动器;以及多个电容,其中每一上述电容耦接于对应的上述电阻以及一参考电压之间。当经由对应于上述驱动器之一者之上述传输线而传送至上述存储器之逻辑“0”的数量与逻辑“1”的数量为不平衡时,上述控制器提供一特定码至上述驱动器之该者,以便调整对应于上述驱动器之该者之上述电容的一终端电压。In another embodiment, the present invention also provides a memory system. The memory system includes terminal circuits, a controller, and a plurality of memories. The terminal circuit includes: a plurality of drivers, each of which is coupled to the memory via a transmission line; a plurality of resistors, wherein each of the above resistors is coupled to the corresponding driver via a corresponding transmission line; and a plurality of Capacitors, wherein each of the capacitors is coupled between the corresponding resistor and a reference voltage. When the number of logic "0"s and the number of logic "1" transmitted to the memory through the transmission line corresponding to one of the drivers are unbalanced, the controller provides a specific code to the one of the drivers, In order to adjust a terminal voltage corresponding to the capacitor of the driver.
在又一实施方式中,本发明还提供一种在另一个实施方式中,本发明还提供一种存储器系统,适用于藉由一终端电路传输数据至多个存储器,其中上述终端电路包括多个驱动器、多个电阻以及多个电容,以及上述驱动器可经由多条传输线而耦接于上述存储器,每一上述电阻经由对应的上述传输线而耦接于对应的上述驱动器以及每一上述电容耦接于对应的上述电阻以及一参考电压之间。该直流平衡方法包括:解码一输入信号,以得到具有地址以及命令信息的数据;经由上述驱动器,提供上述数据;以及当经由对应于上述驱动器之一者而提供的数据的逻辑“0”的数量与逻辑“1”的数量为不平衡时,经由上述驱动器之该者而提供一特定码,以便调整对应于上述驱动器之该者的上述电容的一终端电压。In yet another embodiment, the present invention also provides a memory system adapted to transfer data to a plurality of memories via a termination circuit, wherein the termination circuit includes a plurality of drivers , a plurality of resistors and a plurality of capacitors, and the driver can be coupled to the memory via a plurality of transmission lines, each of the resistors is coupled to the corresponding driver via the corresponding transmission line, and each of the capacitors is coupled to the corresponding between the above resistance and a reference voltage. The DC balancing method includes: decoding an input signal to obtain data having address and command information; providing the data via the drivers; and when the number of logic "0"s of the data provided via one of the drivers When the number of AND logic "1"s is unbalanced, a specific code is provided via the one of the drivers to adjust a terminal voltage of the capacitor corresponding to the one of the drivers.
上述终端电路、存储器系统以及直流平衡方法可以在不使用任何终端电压调整器的情况下达到平衡直流的效果。The above terminal circuit, memory system and DC balancing method can achieve the effect of balancing DC without using any terminal voltage regulator.
附图说明 Description of drawings
图1显示根据本发明一实施例所述之存储器系统;FIG. 1 shows a memory system according to an embodiment of the present invention;
图2显示根据本发明一实施例所述之图1中控制器的示意图;FIG. 2 shows a schematic diagram of the controller in FIG. 1 according to an embodiment of the present invention;
图3显示根据本发明一实施例所述之适用于存储器系统之直流平衡方法,其中存储器系统包括控制器、终端电路以及多个存储器;FIG. 3 shows a DC balancing method suitable for a memory system according to an embodiment of the present invention, wherein the memory system includes a controller, a terminal circuit, and a plurality of memories;
图4显示根据本发明一实施例所述之由图2中控制器所执行之平衡程序的流程图;以及FIG. 4 shows a flowchart of a balancing program executed by the controller in FIG. 2 according to an embodiment of the present invention; and
图5显示由图2中一判断单元所得到之统计值的示意图。FIG. 5 shows a schematic diagram of statistical values obtained by a judging unit in FIG. 2 .
具体实施方式 Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.
图1显示根据本发明一实施例所述的存储器系统。存储器系统包括控制器10、多个存储器301-30M以及终端电路60。存储器301-30M由控制器10所控制。此外,终端电路60包括多个驱动器201-20N、多个终端电阻RT1-RTN以及多个终端电容CT1-CTN。根据输入信号IN,控制器10会经由驱动器201-20N以及总线50来提供地址信号以及命令信号至存储器301-30M,例如写入致能(write enable,简称为WE)信号、行地址(column address signal,简称为CAS)信号、列地址(row address signal,简称为RAS)信号以及芯片选择(chipselect,简称为CS)信号,其中总线50由多条传输线401-40N所形成。在此实施例中,存储器301-30M为双倍数据速率之动态随机存取器。对每一驱动器201-20N而言,个别的终端电阻以及个别的终端电容用来对由控制器10所提供的对应的信号来提供终端电压。例如,终端电阻RT1耦接于驱动器201,而终端电容CT1耦接于终端电阻RT1以及接地端GND之间。在一实施例中,终端电容CT1可以耦接在终端电阻RT1以及供应电压VDD之间。FIG. 1 shows a memory system according to an embodiment of the invention. The memory system includes a controller 10 , a plurality of memories 30 1 - 30 M , and a termination circuit 60 . The memories 30 1 - 30 M are controlled by the controller 10 . In addition, the termination circuit 60 includes a plurality of drivers 20 1 -20 N , a plurality of termination resistors R T1 -R TN and a plurality of termination capacitors C T1 -C TN . According to the input signal IN, the controller 10 will provide address signals and command signals to the memory 30 1 -30 M through the drivers 20 1 -20 N and the bus 50, such as write enable (write enable, WE for short) signal, row Address (column address signal, referred to as CAS) signal, column address signal (row address signal, referred to as RAS) signal and chip select (chipselect, referred to as CS) signal, wherein the bus 50 is formed by a plurality of transmission lines 40 1 -40 N . In this embodiment, the memories 30 1 - 30 M are double data rate dynamic random access devices. For each driver 20 1 - 20 N , an individual termination resistor and an individual termination capacitance are used to provide termination voltages for corresponding signals provided by the controller 10 . For example, the terminal resistor R T1 is coupled to the driver 20 1 , and the terminal capacitor C T1 is coupled between the terminal resistor R T1 and the ground terminal GND. In an embodiment, the termination capacitor C T1 may be coupled between the termination resistor R T1 and the supply voltage VDD.
通常,双倍数据速率之动态随机存取器的规格会要求电阻性之传输线终端会终止在接近供应电压VDD以及接地电压GND之中间点位准的电压(即终端电压)。在图1,当经由总线50之一传输线而传送至存储器301-30M之逻辑“0”的数量与逻辑“1”的数量为不平衡时,藉由在一或多个闲置周期的期间来经由该传输线而提供直流平衡码(DC balance code)至所对应之终端电容,控制器10可调整在所对应的终端电容上的终端电压。闲置周期表示总线50为无动作或是被驱动为“无操作”命令(即no operation,简称为NOP)之时间周期。再者,直流平衡码表示所传送之逻辑“0”与逻辑“1”之长期间的比例(long-term ratio)约为50%。在其他实施例中,控制器10可在闲置周期的期间来传送扰乱码或是调变码,以控制在所对应之终端电容上的终端电压。Typically, the specification of a DDR DRAM requires that the resistive transmission line termination be terminated at a voltage close to the midpoint between the supply voltage VDD and the ground voltage GND (ie, the termination voltage). In FIG. 1, when the number of logic "0"s and the number of logic "1s" transmitted to the memories 301-30M via one of the transmission lines of the bus 50 are unbalanced, by To provide a DC balance code (DC balance code) to the corresponding terminal capacitor via the transmission line, the controller 10 can adjust the terminal voltage on the corresponding terminal capacitor. The idle period represents the time period during which the bus 50 is inactive or driven to a "no operation" command (ie, NOP for short). Furthermore, the DC balanced code means that the long-term ratio of the transmitted logic "0" to logic "1" is about 50%. In other embodiments, the controller 10 may transmit the scrambling code or the modulation code during the idle period to control the terminal voltage on the corresponding terminal capacitor.
图2显示根据本发明一实施例所述之图1中控制器10的示意图。控制器10包括解码器110、调度器(scheduler)120、多个选择器1301-130K以及复数个判断单元1401-140K。在此实施例中,每一选择器1301-130K为一多任务器(multiplexer,简称为MUX)。解码器110用以对来自其他电路(例如处理器)之具有多个位的输入信号IN进行解码,以得到地址数据ADDR1-ADDRK或者命令数据CMD1-CMDK或是其组合。地址数据ADDR1-ADDRK以及命令数据CMD1-CMDK经由总线150而传送至图1的驱动器201-20M,其中总线150由多条传输线1601-160K所形成。每一判断单元1401-140K耦接于总线150中所对应之传输线,其中各判断单元1401-140K用以记录被输出至所对应之驱动器的数据。举例来说,判断单元1401耦接于传输线1601,而判断单元140K耦接于传输线160K。此外,每一判断单元1401-140K可根据其所记录的数据而得到一统计值。各判断单元1401-140K可提供直流平衡码至所对应之选择器。根据控制信号SEL,每一选择器1301-130K会选择性地提供地址数据ADDR1-ADDRK或者命令数据CMD1-CMDK或是其组合,或是直流平衡码CODE1-CODEK至所对应的传输线。举例来说,一旦,统计值之一者指示所输出之数据的逻辑“0”的数量与逻辑“1”的数量为不平衡时,则得到该统计值的判断单元会提供插入信号INS1、…或INSK至调度器120。相应于插入信号,调度器120会提供请求信号REQ至解码器110,以便通知解码器110需插入直流平衡码。于是,解码器110会提供控制信号SEL来控制选择器1301-130K,而分别输出由判断单元1401-140K所提供之直流平衡码CODE1-CODEK至总线150的传输线1601-160K,以便控制图1中终端电容CT1-CTN的终端电压能回复到大概在供应电压VDD以及接地端GND之间的中间点位准。同时地,解码器110会停止提供地址数据ADDR1-ADDRK与命令数据CMD1-CMDK至选择器1301-130K。如先前所描述,控制信号SEL会控制选择器1301-130K只在闲置周期来提供直流平衡码。判断单元1401-140K会继续记录总线150上的数据并得到对应于所记录之数据的统计值。藉由插入信号INS1-INSK,一旦全部的统计值皆指示逻辑“0”的数量与逻辑“1”的数量为平衡,则调度器120会提供请求信号REQ至解码器110,用以通知解码器110不需要再插入直流平衡码。FIG. 2 shows a schematic diagram of the controller 10 in FIG. 1 according to an embodiment of the present invention. The controller 10 includes a decoder 110 , a scheduler 120 , a plurality of selectors 1301 - 130K and a plurality of judging units 140 1 - 140 K . In this embodiment, each selector 130 1 - 130 K is a multiplexer (MUX for short). The decoder 110 is used for decoding an input signal IN with multiple bits from other circuits (such as a processor) to obtain address data ADDR 1 -ADDR K or command data CMD 1 -CMD K or a combination thereof. The address data ADDR 1 -ADDR K and the command data CMD 1 -CMD K are transmitted to the drivers 20 1 -20 M of FIG. 1 via the bus 150 formed by a plurality of transmission lines 160 1 -160 K. Each judging unit 140 1 -140 K is coupled to a corresponding transmission line in the bus 150, wherein each judging unit 140 1 -140 K is used for recording data output to a corresponding driver. For example, the judging unit 140 1 is coupled to the transmission line 160 1 , and the judging unit 140 K is coupled to the transmission line 160 K . In addition, each judging unit 140 1 -140 K can obtain a statistical value according to its recorded data. Each judging unit 140 1 -140 K can provide a DC balanced code to the corresponding selector. According to the control signal SEL, each selector 130 1-130 K will selectively provide address data ADDR 1 -ADDR K or command data CMD 1 -CMD K or a combination thereof, or a DC balance code CODE 1 -CODE K to the corresponding transmission line. For example, once one of the statistical values indicates that the quantity of logic “0” and the quantity of logic “1” in the output data are unbalanced, the judging unit that obtains the statistical value will provide the insertion signal INS 1 , ... or INS K to scheduler 120 . Corresponding to the insertion signal, the scheduler 120 provides a request signal REQ to the decoder 110 to notify the decoder 110 that the DC balanced code needs to be inserted. Therefore, the decoder 110 will provide the control signal SEL to control the selectors 130 1 -130 K , and respectively output the DC balanced codes CODE 1 -CODE K provided by the judging units 140 1 -140 K to the transmission line 160 1 - of the bus 150 160 K so as to control the terminal voltage of the terminal capacitors C T1 -C TN in FIG. 1 to return to a level approximately at the middle point between the supply voltage VDD and the ground terminal GND. Simultaneously, the decoder 110 stops providing address data ADDR 1 -ADDR K and command data CMD 1 -CMD K to the selectors 130 1 -130 K . As previously described, the control signal SEL controls the selectors 130 1 - 130 K to provide DC balanced codes only during idle periods. The judging units 140 1 - 140 K continue to record data on the bus 150 and obtain statistical values corresponding to the recorded data. By inserting the signals INS 1 -INS K , once all statistics indicate that the number of logic “0”s and the number of logic “1”s are balanced, the scheduler 120 will provide a request signal REQ to the decoder 110 to notify The decoder 110 does not need to insert a DC balanced code.
再者,由判断单元1401-140K所提供的直流平衡码CODE1-CODEK可以相同或不同。在图2中,地址数据ADDR1-ADDRK与命令数据CMD1-CMDK共享相同的传输线。例如,地址数据ADDR1与命令数据CMD1共享总线150的传输线1601,而地址数据ADDRK与命令数据CMDK共享总线150的传输线160K。在一实施例中,地址数据ADDR1-ADDRK与命令数据CMD1-CMDK可以不共享相同的传输线。例如,每一地址数据ADDR1-ADDRK以及每一命令数据CMD1-CMDK经由不同的选择器、总线150的不同传输线以及不同的驱动器而传送至存储器。Furthermore, the DC balance codes CODE 1 -CODE K provided by the judging units 140 1 -140 K may be the same or different. In FIG. 2, address data ADDR1- ADDRK and command data CMD1 - CMDK share the same transmission line. For example, the address data ADDR 1 and the command data CMD 1 share the transmission line 160 1 of the bus 150 , and the address data ADDR K and the command data CMD K share the transmission line 160 K of the bus 150 . In one embodiment, the address data ADDR 1 -ADDR K and the command data CMD 1 -CMD K may not share the same transmission line. For example, each address data ADDR 1 -ADDR K and each command data CMD 1 -CMD K are transmitted to the memory through different selectors, different transmission lines of the bus 150 and different drivers.
图3显示根据本发明一实施例所述的适用于存储器系统的直流平衡方法,其中存储器系统包括控制器(例如图1的控制器10)、终端电路(例如图1的终端电路60)以及多个存储器(例如第1图的存储器301-30M)。首先,在步骤S310,控制器的解码器(例如第1图的解码器110)会对输入信号IN进行解码,以得到地址数据或者命令数据或者其组合(例如图2的地址数据ADDR1-ADDRK或者命令数据CMD1-CMDK或者其组合)。接着,在步骤S320,控制器会经由终端电路的驱动器(例如第1图的驱动器201-20N)来传送数据至存储器。接着,在步骤S330,控制器会对经由各驱动器而传送至存储器的数据进行记录。接着,在步骤S340,对每个所记录的数据而言,控制器会得到一统计值,其中统计值关于所记录之数据之逻辑“0”的数量与逻辑“1”的数量。接着,在步骤S350,控制器会根据统计值来执行一平衡程序,而决定是否需插入直流平衡码。接着,在步骤S360,当统计值指示经由驱动器之一者而传送至存储器的所记录的数据的逻辑“0”的数量与逻辑“1”的数量为不平衡时,控制器会经由驱动器传送直流平衡码至存储器,以便调整终端电路的终端电压,或是特别调整对应于该驱动器的终端电压。FIG. 3 shows a DC balancing method suitable for a memory system according to an embodiment of the present invention, wherein the memory system includes a controller (such as the controller 10 in FIG. 1 ), a terminal circuit (such as the terminal circuit 60 in FIG. 1 ) and multiple memory (eg memory 30 1 -30 M in Figure 1). First, in step S310, the decoder of the controller (such as the decoder 110 in Figure 1) decodes the input signal IN to obtain address data or command data or a combination thereof (such as address data ADDR 1 -ADDR in Figure 2 K or command data CMD 1 -CMD K or a combination thereof). Next, in step S320 , the controller transmits data to the memory via the drivers of the terminal circuit (such as the drivers 20 1 -20 N in FIG. 1 ). Next, in step S330, the controller records the data transmitted to the memory via each driver. Next, in step S340, for each recorded data, the controller obtains a statistical value, wherein the statistical value is related to the number of logic "0"s and the number of logic "1"s in the recorded data. Next, in step S350, the controller executes a balancing procedure according to the statistical value to determine whether to insert a DC balancing code. Next, in step S360, when the statistical value indicates that the number of logic “0”s and the number of logic “1” of the recorded data transmitted to the memory via one of the drivers are unbalanced, the controller transmits a direct current through the driver. The balance code is stored in the memory so as to adjust the terminal voltage of the terminal circuit, or specifically adjust the terminal voltage corresponding to the driver.
图4显示根据本发明一实施例所述的由图2中控制器10所执行之平衡程序的流程图。图5显示由图2中判断单元1401所得到之统计值的示意图。在控制器10中,判断单元1401可使用低通滤波器来对所记录的数据之标号A所显示),判断单元1401会提供插入信号INS1至调度器120,以通知调度器120该统计值已经超出第一平衡范围BR1。于是,调度器120提供请求信号REQ至解码器110。接着,在步骤S420,解码器110会执行第一阶段直流平衡程序,以停止提供地址数据ADDR1以及命令数据CMD1-CMDK至选择器1301-130K。同时地,解码器110会在适合的时间点来提供控制信号SEL,以便将来自判断单元1401-140K的直流平衡码插入至总线150中。具体而言,控制器10不会立即地插入直流平衡码至总线150。接着,在步骤S430,判断单元1401会继续对传输线1601上的数据进行记录,并根据所记录之数据来得到统计值,以便侦测统计值是否仍超出第一平衡范围BR1。若统计值回到第一平衡范围BR1内,判断单元1401会提供插入信号INS1至调度器120,来通知调度器120该统计值未超出第一平衡范围BR1。接着,调度器120会提供请求信号REQ至解码器110,以便停止执行第一阶段直流平衡程序(即停止插入直流平衡码至总线150)。若统计值仍超出第一平衡范围BR1,判断单元1401更侦测统计值是否超出第二平衡范围BR2(步骤S440)。位准L2H与位准L2L分别为第二阶段直流平衡程序中第二平衡范围BR2的上限与下限。同样地,位准Lmid为位准L2H与位准L2L之间的中间位准。此外,位准L2H高于位准L1H,而位准L2L低于位准L1L。若统计值没有超出第二平衡范围BR2,则执行步骤S420,然后解码器110会继续执行第一阶段直流平衡程序。反之,若统计值超出第二平衡范围BR2,例如统计值达到位准L2H(如第5图之标号B所显示),判断单元1401会提供插入信号INS1至调度器120,来通知调度器120该统计值已经超出第二平衡范围BR2。于是,调度器120会提供请求信号REQ至解码器110,而解码器110会执行第二阶段直流平衡程序(步骤S450),以便立即地提供控制信号SEL至选择器1301-130K,而能立即插入直流平衡码,直到判断单元1401侦测到统计值到达位准Loff,如第5图之标号C所显示。在此实施例中,位准Loff为第一平衡范围BR1内的一位准。此外,位准Loff可以大于位准Lmid或是小于位准Lmid。再者,对每一判断单元1401-140K而言,位准L1H与L1L、位准L2H与L2L以及位准Loff可根据实际应用而设定。FIG. 4 shows a flowchart of a balancing procedure executed by the controller 10 in FIG. 2 according to an embodiment of the present invention. FIG. 5 shows a schematic diagram of statistical values obtained by the judging unit 1401 in FIG. 2 . In the controller 10, the judging unit 1401 can use a low-pass filter to display the label A of the recorded data), and the judging unit 1401 will provide an insertion signal INS1 to the scheduler 120 to notify the scheduler 120 of the The statistical value has exceeded the first balance range BR1. Then, the scheduler 120 provides a request signal REQ to the decoder 110 . Next, in step S420 , the decoder 110 executes a first-stage DC balance procedure to stop providing the address data ADDR 1 and the command data CMD 1 -CMD K to the selectors 130 1 -130 K . Simultaneously, the decoder 110 provides the control signal SEL at an appropriate time point, so as to insert the DC balanced codes from the judging units 140 1 -140 K into the bus 150 . Specifically, the controller 10 does not immediately insert the DC balanced code into the bus 150 . Next, in step S430, the judging unit 1401 will continue to record the data on the transmission line 1601, and obtain statistical values according to the recorded data, so as to detect whether the statistical values still exceed the first balance range BR1. If the statistical value returns to the first balance range BR1, the judging unit 1401 provides an insertion signal INS1 to the scheduler 120 to notify the scheduler 120 that the statistical value does not exceed the first balance range BR1. Next, the scheduler 120 provides a request signal REQ to the decoder 110 to stop the first-stage DC balancing procedure (ie stop inserting the DC balancing code into the bus 150 ). If the statistical value still exceeds the first balance range BR1, the judging unit 1401 further detects whether the statistical value exceeds the second balance range BR2 (step S440). The level L 2H and the level L 2L are respectively the upper limit and the lower limit of the second balance range BR2 in the second-stage DC balance procedure. Likewise, the level L mid is an intermediate level between the levels L 2H and L 2L . In addition, the level L 2H is higher than the level L 1H , and the level L 2L is lower than the level L 1L . If the statistical value does not exceed the second balance range BR2, step S420 is executed, and then the decoder 110 continues to execute the first-stage DC balance procedure. Conversely, if the statistical value exceeds the second balance range BR2, for example, the statistical value reaches the level L2H (as shown by the label B in FIG. 5), the judgment unit 1401 will provide an insertion signal INS1 to the scheduler 120 to notify the scheduler The statistical value of the controller 120 has exceeded the second balance range BR2. Then, the scheduler 120 will provide the request signal REQ to the decoder 110, and the decoder 110 will execute the second-stage DC balancing procedure (step S450), so as to immediately provide the control signal SEL to the selectors 130 1 -130 K , thereby enabling Immediately insert the DC balance code until the judging unit 140 1 detects that the statistical value reaches the level L off , as shown by the symbol C in FIG. 5 . In this embodiment, the level L off is a level within the first balance range BR1. In addition, the level L off can be greater than the level L mid or smaller than the level L mid . Furthermore, for each judging unit 140 1 -140 K , the levels L 1H and L 1L , the levels L 2H and L 2L , and the level L off can be set according to actual applications.
最后应说明的是:以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域技术人员应当理解:其依然可以对前述各实施方式所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施方式技术方案的范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still be used for the foregoing The technical solutions recorded in the various embodiments are modified, or some of the technical features are replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the various embodiments of the present invention.
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US13/572,143 US8952718B2 (en) | 2011-08-25 | 2012-08-10 | Termination circuit and DC balance method thereof |
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