CN103064801B - Terminating circuit, accumulator system and DC balance method - Google Patents
Terminating circuit, accumulator system and DC balance method Download PDFInfo
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Abstract
The invention provides a kind of terminating circuit, accumulator system and DC balance method.This accumulator system comprises terminating circuit, controller and multiple storer.This terminating circuit comprises: multiple driver, and wherein each above-mentioned driver is coupled to above-mentioned storer via a transmission line; Multiple resistance, wherein each above-mentioned resistance is coupled to corresponding above-mentioned driver via the above-mentioned transmission line of correspondence; And multiple electric capacity, wherein each above-mentioned electric capacity is coupled between corresponding above-mentioned resistance and a reference voltage.When the quantity via the quantity and logical one that are sent to the logical zero of above-mentioned storer corresponding to stating transmission line on the one of above-mentioned driver is uneven, above-mentioned controller provides a special code to this person of above-mentioned driver, so that adjustment corresponds to a terminal voltage of the above-mentioned electric capacity of this person of above-mentioned driver.
Description
Technical field
The present invention has about a kind of terminating circuit, and carries out a kind of accumulator system of data transmission before being particularly to terminating circuit and multiple storer.
Background technology
Along with system bandwidth constantly increases, storing technology is optimized for higher speed and performance.The synchronous volatile storage (synchronous dynamic random access memory, referred to as SDRAM) of Double Data Rate (double data rate, referred to as DDR) of future generation is DDR3SDRAM.DDR3 SDRAM has advantage more more than DDR2SDRAM, such as lower operating power, higher speed, higher performance (bandwidth of 2 times) etc.Specifically, compared to DDR2 SDRAM, DDR3SDRAM reduces power consumption, and it is mainly due to less crystallite dimension and lower supply voltage (such as DDR3 SDRAM is 1.5V and DDR2 SDRAM is 1.8V).
Be same as the T-shaped branch topological structure of DDR2 SDRAM, DDR3 SDRAM have employed transmission control (fly-by) topological structure, and it provides better signal integrity with higher speed.Transmission control topological structure is applied in the order of DDR3 SDRAM, address, control and frequency signal.These signals coming from Memory Controller are connected to each DRAM device in the mode of series connection, therefore can improve signal integrity by the minimizing quantity of branch and the length of branch.
Terminating circuit can provide termination impedance value to the common node of multiple DDR3 SDRAM usually, to avoid the reduction causing the online signal integrity of the transmission of DDR3 SDRAM.Common node can at earthing potential or the half current potential between earth terminal and supply voltage, wherein required terminal voltage adjustable.Such as, can require that the memory terminal circuit of DDR SDRAM provides the terminal voltage being approximately same as one of supply voltage (such as VDD) subluxation standard at common node place.Such as, but conventional terminal circuit, legacy ddr DRAM terminating circuit, can cause many shortcomings.
In conventional terminal circuit, each transmission line driven by a driver, and is coupled to Voltage Cortrol node.Voltage Cortrol node is coupled to earth terminal through the terminal resistance connected in a series arrangement and terminal voltage adjuster, and wherein terminal voltage adjuster can provide and the special adjuster drawing electric current.Although terminal voltage adjuster can provide terminal voltage accurately on Voltage Cortrol node, but terminal voltage adjuster is the stand-alone assembly that a meeting increases manufacturing cost.
Therefore, a kind of terminating circuit not using any terminal voltage adjuster is needed.
Summary of the invention
In view of this, be necessary to provide the terminating circuit, accumulator system and the DC balance method that do not use any terminal voltage adjuster.
In one embodiment, the invention provides a kind of terminating circuit, be applicable to transmit data.This terminating circuit comprises multiple driver, multiple resistance and multiple electric capacity.Each above-mentioned driver provides data via a transmission line; Each above-mentioned resistance is coupled to corresponding above-mentioned driver via the above-mentioned transmission line of correspondence; Each above-mentioned electric capacity is coupled between corresponding above-mentioned resistance and a reference voltage, the quantity of the logical zero wherein transmitted when the above-mentioned transmission line via the one corresponding to above-mentioned driver and the quantity of logical one are for time uneven, this person of above-mentioned driver receives a special code and this special code is provided to above-mentioned transmission line, so that adjustment corresponds to a terminal voltage of the above-mentioned electric capacity of this person of above-mentioned driver.
In another embodiment, the present invention also provides a kind of accumulator system.This accumulator system comprises terminating circuit, controller and multiple storer.This terminating circuit comprises: multiple driver, and wherein each above-mentioned driver is coupled to above-mentioned storer via a transmission line; Multiple resistance, wherein each above-mentioned resistance is coupled to corresponding above-mentioned driver via the above-mentioned transmission line of correspondence; And multiple electric capacity, wherein each above-mentioned electric capacity is coupled between corresponding above-mentioned resistance and a reference voltage.When the quantity via the quantity and logical one that are sent to the logical zero of above-mentioned storer corresponding to stating transmission line on the one of above-mentioned driver is uneven, above-mentioned controller provides a special code to this person of above-mentioned driver, so that adjustment corresponds to a terminal voltage of the above-mentioned electric capacity of this person of above-mentioned driver.
In yet, the present invention also provides one in another embodiment, the present invention also provides a kind of accumulator system, be applicable to transfer data to multiple storer by a terminating circuit, wherein above-mentioned terminating circuit comprises multiple driver, multiple resistance and multiple electric capacity, and above-mentioned driver can be coupled to above-mentioned storer via plurality of transmission lines, each above-mentioned resistance is coupled to corresponding above-mentioned driver via the above-mentioned transmission line of correspondence and each above-mentioned electric capacity is coupled between corresponding above-mentioned resistance and a reference voltage.This DC balance method comprises: an input signal of decoding, to obtain the data with address and command information; Via above-mentioned driver, provide above-mentioned data; And when the quantity of the logical zero of the data provided via the one corresponding to above-mentioned driver and the quantity of logical one are for time uneven, a special code is provided, so that adjustment corresponds to a terminal voltage of the above-mentioned electric capacity of this person of above-mentioned driver via this person of above-mentioned driver.
The effect that above-mentioned terminating circuit, accumulator system and DC balance method can not use the situation of any terminal voltage adjuster to be issued to balanced d. c.
Accompanying drawing explanation
The accumulator system of Fig. 1 display according to one embodiment of the invention;
The schematic diagram of Fig. 1 middle controller of Fig. 2 display according to one embodiment of the invention;
The DC balance method that be applicable to accumulator system of Fig. 3 display according to one embodiment of the invention, wherein accumulator system comprises controller, terminating circuit and multiple storer;
The process flow diagram of the equilibrium code by Fig. 2 middle controller performed by of Fig. 4 display according to one embodiment of the invention; And
Fig. 5 display by a judging unit in Fig. 2 the schematic diagram of statistical value that obtains.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those skilled in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The accumulator system of Fig. 1 display according to one embodiment of the invention.Accumulator system comprises controller 10, multiple storer 30
1-30
mand terminating circuit 60.Storer 30
1-30
mcontrolled by controller 10.In addition, terminating circuit 60 comprises multiple driver 20
1-20
n, multiple terminal resistance R
t1-R
tNand multiple Terminal Capacitance C
t1-C
tN.According to input signal IN, controller 10 can via driver 20
1-20
nand bus 50 provides address signal and command signal to storer 30
1-30
msuch as write activation (write enable, referred to as WE) signal, row address (column address signal, referred to as CAS) signal, column address (row address signal, referred to as RAS) signal and chip selection (chipselect, referred to as CS) signal, wherein bus 50 is by plurality of transmission lines 40
1-40
nformed.In this embodiment, storer 30
1-30
mfor the dynamic random access memory of Double Data Rate.To each driver 20
1-20
n, other terminal resistance individual and other Terminal Capacitance individual are used for the signal of the correspondence provided by controller 10 to provide terminal voltage.Such as, terminal resistance R
t1be coupled to driver 20
1, and Terminal Capacitance C
t1be coupled to terminal resistance R
t1and between earth terminal GND.In one embodiment, Terminal Capacitance C
t1terminal resistance R can be coupled in
t1and between supply voltage VDD.
Usually, the specification of the dynamic random access memory of Double Data Rate can require that the transmission-wire terminal of resistive can terminate in the voltage (i.e. terminal voltage) of the intermediate point position standard close to supply voltage VDD and ground voltage GND.At Fig. 1, when being sent to storer 30 via one of bus 50 transmission line
1-30
mthe quantity of logical zero and the quantity of logical one when being uneven, by providing DC balance code (DC balance code) to corresponding Terminal Capacitance during one or more idle period via this transmission line, the terminal voltage of controller 10 adjustable on corresponding Terminal Capacitance.Idle period represents that bus 50 is attonity or is driven to the time cycle of " without operation " order (i.e. no operation, referred to as NOP).Moreover the long-standing ratio (long-term ratio) of the logical zero that DC balance representation is transmitted and logical one is about 50%.In other embodiments, controller 10 can transmit disturbing code or modulation codes during idle period, to control the terminal voltage on corresponding Terminal Capacitance.
The schematic diagram of Fig. 1 middle controller 10 of Fig. 2 display according to one embodiment of the invention.Controller 10 comprises demoder 110, scheduler (scheduler) 120, multiple selector switch 1301-130K and a plurality of judging unit 140
1-140
k.In this embodiment, each selector switch 130
1-130
kbe a multiplexer (multiplexer, referred to as MUX).Demoder 110 is in order to decode to the input signal IN with multiple from other circuit (such as processor), to obtain address date ADDR
1-ADDR
kor order data CMD
1-CMD
kor its combination.Address date ADDR
1-ADDR
kand order data CMD
1-CMD
kthe driver 20 of Fig. 1 is sent to via bus 150
1-20
m, wherein bus 150 is by plurality of transmission lines 160
1-160
kformed.Each judging unit 140
1-140
kbe coupled to transmission line corresponding in bus 150, wherein each judging unit 140
1-140
kthe data of corresponding driver are output in order to record.For example, judging unit 140
1be coupled to transmission line 160
1, and judging unit 140
kbe coupled to transmission line 160
k.In addition, each judging unit 140
1-140
ka statistical value can be obtained according to its recorded data.Each judging unit 140
1-140
kdC balance code can be provided to corresponding selector switch.According to control signal SEL, each selector switch 130
1-130
kcan optionally provide address date ADDR
1-ADDR
kor order data CMD
1-CMD
kor its combination, or DC balance code CODE
1-CODE
kto corresponding transmission line.For example, once, the quantity of logical zero of the data that the one of statistical value instruction institute exports with the quantity of logical one for imbalance time, then the judging unit obtaining this statistical value can provide insertion signal INS
1... or INS
kto scheduler 120.Corresponding to insertion signal, scheduler 120 can provide request signal REQ to demoder 110, to notify that demoder 110 need insert DC balance code.So demoder 110 can provide control signal SEL to carry out controlled selector 130
1-130
k, and export respectively by judging unit 140
1-140
kthe DC balance code CODE provided
1-CODE
kto the transmission line 160 of bus 150
1-160
k, so that Terminal Capacitance C in control chart 1
t1-C
tNterminal voltage to be returned to general intermediate point position between supply voltage VDD and earth terminal GND accurate.Side by side, demoder 110 can stop providing address date ADDR
1-ADDR
kwith order data CMD
1-CMD
kto selector switch 130
1-130
k.As described previously, control signal SEL can controlled selector 130
1-130
konly provide DC balance code at idle period.Judging unit 140
1-140
kthe data on record trunk 150 can be continued and obtain corresponding to the statistical value of data that records.By insertion signal INS
1-INS
k, once whole statistical values all indicates the quantity of the quantity of logical zero and logical one for balance, then scheduler 120 can provide request signal REQ to demoder 110, in order to notify that demoder 110 does not need to insert DC balance code again.
Moreover, by judging unit 140
1-140
kthe DC balance code CODE provided
1-CODE
kcan be identical or different.In fig. 2, address date ADDR
1-ADDR
kwith order data CMD
1-CMD
kshare identical transmission line.Such as, address date ADDR
1with order data CMD
1the transmission line 160 of shared bus 150
1, and address date ADDR
kwith order data CMD
kthe transmission line 160 of shared bus 150
k.In one embodiment, address date ADDR
1-ADDR
kwith order data CMD
1-CMD
kidentical transmission line can not be shared.Such as, each address date ADDR
1-ADDR
kand each order data CMD
1-CMD
kstorer is sent to via the different transmission line of different selector switchs, bus 150 and different drivers.
The DC balance method that be applicable to accumulator system of Fig. 3 display according to one embodiment of the invention, wherein accumulator system comprises controller (controller 10 of such as Fig. 1), terminating circuit (terminating circuit 60 of such as Fig. 1) and multiple storer (such as storer 30 of the 1st figure
1-30
m).First, in step S310, the demoder (such as the demoder 110 of the 1st figure) of controller can be decoded to input signal IN, combines (the address date ADDR of such as Fig. 2 to obtain address date or order data or its
1-ADDR
kor order data CMD
1-CMD
kor its combination).Then, in step S320, controller can via the driver of terminating circuit (the such as driver 20 of the 1st figure
1-20
n) transmit data to storer.Then, in step S330, controller can carry out record to the data being sent to storer via each driver.Then, in step S340, for each recorded data, controller can obtain a statistical value, wherein statistical value about the quantity of logical zero of data that records and the quantity of logical one.Then, in step S350, controller can perform an equilibrium code according to statistical value, and determines whether need to insert DC balance code.Then, in step S360, when statistical value indicates the quantity of the logical zero of the recorded data being sent to storer via the one of driver and the quantity of logical one for time uneven, controller can transmit DC balance code to storer via driver, to adjust the terminal voltage of terminating circuit, or special adjustment corresponds to the terminal voltage of this driver.
The process flow diagram of by Fig. 2 middle controller 10 performed equilibrium code of Fig. 4 display according to one embodiment of the invention.Fig. 5 display is by judging unit in Fig. 2 140
1the schematic diagram of statistical value that obtains.In controller 10, judging unit 140
1shown by the label A that low-pass filter can be used to come recorded data), judging unit 140
1can provide and insert signal INS
1to scheduler 120, to notify that this statistical value of scheduler 120 has exceeded the first range of balance BR1.So scheduler 120 provides request signal REQ to demoder 110.Then, in step S420, demoder 110 can perform first stage DC balance program, to stop providing address date ADDR
1and order data CMD
1-CMD
kto selector switch 130
1-130
k.Side by side, demoder 110 can provide control signal SEL, so that will from judging unit 140 at the time point be applicable to
1-140
kdC balance code be inserted in bus 150.Specifically, controller 10 can not insert DC balance code immediately to bus 150.Then, in step S430, judging unit 140
1can continue transmission line 160
1on data carry out record, and according to the data that record obtain statistical value, to detect statistical value whether still exceed the first range of balance BR1.If statistical value is got back in the first range of balance BR1, judging unit 140
1can provide and insert signal INS
1to scheduler 120, notify that this statistical value of scheduler 120 does not exceed the first range of balance BR1.Then, scheduler 120 can provide request signal REQ to demoder 110, to stop performing first stage DC balance program (namely stopping inserting DC balance code to bus 150).If statistical value still exceeds the first range of balance BR1, judging unit 140
1more detect statistical value and whether exceed the second range of balance BR2(step S440).The accurate L in position
2Hl accurate with position
2Lbe respectively the upper limit and the lower limit of the second range of balance BR2 in subordinate phase DC balance program.Similarly, the accurate L in position
midfor the accurate L in position
2Hl accurate with position
2Lbetween interposition accurate.In addition, the accurate L in position
2Hhigher than the accurate L in position
1H, and the accurate L in position
2Llower than the accurate L in position
1L.If statistical value does not exceed the second range of balance BR2, then perform step S420, then demoder 110 can continue to perform first stage DC balance program.Such as, otherwise if statistical value exceeds the second range of balance BR2, statistical value reaches the accurate L in position
2H(as shown in the label B of the 5th figure), judging unit 140
1can provide and insert signal INS
1to scheduler 120, notify that this statistical value of scheduler 120 has exceeded the second range of balance BR2.So scheduler 120 can provide request signal REQ to demoder 110, and demoder 110 can perform subordinate phase DC balance program (step S450), to provide control signal SEL to selector switch 130 immediately
1-130
k, and DC balance code can be inserted immediately, until judging unit 140
1detect statistical value and arrive the accurate L in position
off, as shown in the label C of the 5th figure.In this embodiment, the accurate L in position
offit is a standard in the first range of balance BR1.In addition, the accurate L in position
offthe accurate L in position can be greater than
midor be less than the accurate L in position
mid.Moreover, to each judging unit 140
1-140
k, the accurate L in position
1Hwith L
1L, the accurate L in position
2Hwith L
2Land the accurate L in position
offcan set according to practical application.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those skilled in the art are to be understood that: it still can be modified to the technical scheme described in aforementioned each embodiment, or carry out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of each embodiment technical scheme of the present invention.
Claims (25)
1. a terminating circuit, is applicable to transmit data, comprises:
Multiple driver, wherein each above-mentioned driver provides data via a transmission line;
Multiple resistance, wherein each above-mentioned resistance is coupled to corresponding driver via the transmission line of correspondence; And
Multiple electric capacity, wherein each above-mentioned electric capacity has the first end being coupled to corresponding resistance and the second end being coupled to a reference voltage, wherein the first end of each above-mentioned electric capacity and the first end of other electric capacity electrically isolated, the quantity of the logical zero wherein transmitted when the transmission line via the one corresponding to above-mentioned multiple driver and the quantity of logical one are for time uneven, this person of above-mentioned multiple driver receives a special code and this special code is provided to corresponding transmission line, so that adjustment corresponds to a terminal voltage of the electric capacity of this person of above-mentioned multiple driver.
2. terminating circuit according to claim 1, is characterized in that, above-mentioned terminating circuit is also for obtaining multiple statistical value according to the quantity of logical zero of the above-mentioned data transmitted via each above-mentioned driver and the quantity of logical one.
3. terminating circuit according to claim 2, is characterized in that, when the statistical value of this person corresponding to above-mentioned multiple driver exceeds a particular range, this person of above-mentioned multiple driver receives this special code.
4. terminating circuit according to claim 2, is characterized in that, when the statistical value of this person corresponding to above-mentioned multiple driver exceeds a particular range, All Drives receives corresponding special code, to adjust the above-mentioned terminal voltage of above-mentioned electric capacity.
5. terminating circuit according to claim 1, is characterized in that, above-mentioned special code is that a DC balance code, confuses code or a modulation codes.
6. terminating circuit according to claim 1, it is characterized in that, above-mentioned reference voltage is a supply voltage or a ground voltage, and this person of above-mentioned multiple driver receives this special code, so that adjustment corresponds to the above-mentioned terminal voltage of the electric capacity of this person of above-mentioned multiple driver, make an accurate general intermediate point position between above-mentioned supply voltage and above-mentioned ground voltage, the position of above-mentioned terminal voltage accurate.
7. an accumulator system, it comprises just like the terminating circuit in claim 1-6 described in any one, one controller, and multiple storer, wherein, each above-mentioned driver is coupled to above-mentioned storer via the transmission line of correspondence, above-mentioned controller is coupled to above-mentioned storer via above-mentioned driver, and when via the quantity corresponding to the transmission line of one of above-mentioned multiple driver and the quantity that is sent to the logical zero of above-mentioned storer and logical one for imbalance time, above-mentioned controller provides a special code to this person of above-mentioned multiple driver, so that adjustment corresponds to a terminal voltage of the electric capacity of this person of above-mentioned multiple driver.
8. accumulator system according to claim 7, is characterized in that, above-mentioned controller comprises:
One demoder, in order to decode to an input signal, to provide the data with address and command information to above-mentioned storer; And
Multiple selector switch, is coupled between above-mentioned demoder and above-mentioned driver,
Wherein each above-mentioned selector switch optionally provides above-mentioned data or above-mentioned special code to corresponding driver according to a control signal.
9. accumulator system according to claim 8, is characterized in that, above-mentioned controller more comprises:
One scheduler, in order to insert signal corresponding to one, and provides a request signal to above-mentioned demoder; And
Multiple judging unit, wherein each judging unit is coupled to corresponding selector switch and the driver of correspondence,
The wherein data that exported by corresponding selector switch of each an above-mentioned judging unit record and statistical value is provided, and provide above-mentioned special code to corresponding selector switch, and when above-mentioned statistical value indicates the quantity of the logical zero of the above-mentioned data recorded and the quantity of logical one for time uneven, above-mentioned judging unit provides above-mentioned insertion signal to above-mentioned scheduler.
10. accumulator system according to claim 9, it is characterized in that, after receiving above-mentioned request signal, above-mentioned demoder stops providing above-mentioned data and providing the above-mentioned above-mentioned selector switch controlled signal to corresponding to the above-mentioned judging unit providing above-mentioned insertion signal, to control above-mentioned selector switch to provide above-mentioned special code to corresponding driver.
11. accumulator systems according to claim 9, it is characterized in that, after receiving above-mentioned request signal, above-mentioned demoder stops providing above-mentioned data and providing above-mentioned controlling signal to above-mentioned selector switch, to control above-mentioned selector switch to provide the above-mentioned special code extremely above-mentioned multiple driver from above-mentioned judging unit, to adjust the above-mentioned terminal voltage of above-mentioned electric capacity.
12. accumulator systems according to claim 7, is characterized in that, above-mentioned storer is the dynamic random access memory of Double Data Rate.
13. 1 kinds of DC balance methods, be applicable to transfer data to multiple storer by a terminating circuit, wherein above-mentioned terminating circuit comprises multiple driver, multiple resistance and multiple electric capacity, and above-mentioned driver can be coupled to above-mentioned storer via plurality of transmission lines, each above-mentioned resistance is coupled to corresponding driver via the transmission line of correspondence and each above-mentioned electric capacity is coupled between corresponding resistance and a reference voltage, and this DC balance method comprises:
To decode an input signal, to obtain the data with address and command information;
Via above-mentioned driver, provide above-mentioned data; And
When the quantity of the logical zero of the data provided via the one corresponding to above-mentioned multiple driver and the quantity of logical one are for time uneven, a special code is provided, so that adjustment corresponds to a terminal voltage of the electric capacity of this person of above-mentioned multiple driver via this person of above-mentioned multiple driver;
Wherein, each above-mentioned electric capacity has the first end being coupled to corresponding resistance and the second end being coupled to this reference voltage, and the first end of each above-mentioned electric capacity and the first end of other electric capacity electrically isolated.
14. DC balance methods according to claim 13, also comprise:
Record is provided to the above-mentioned data of above-mentioned storer via each above-mentioned driver; And
A statistical value is obtained according to the quantity of logical zero of each recorded above-mentioned data and the quantity of logical one.
15. DC balance methods according to claim 14, is characterized in that, when the statistical value of this person corresponding to above-mentioned multiple driver is more than a particular range, above-mentioned special code is provided to above-mentioned storer via this person of above-mentioned multiple driver.
16. DC balance methods according to claim 14, it is characterized in that, when the statistical value of this person corresponding to above-mentioned multiple driver is more than a particular range, above-mentioned special code is provided to above-mentioned storer via whole above-mentioned drivers, to adjust the above-mentioned terminal voltage of above-mentioned electric capacity.
17. DC balance methods according to claim 14, is characterized in that, provide above-mentioned special code also to comprise to the step of above-mentioned storer via this person of above-mentioned multiple driver:
When the one of above-mentioned statistical value exceeds first scope, between an idle period of above-mentioned storer, there is provided above-mentioned special code, wherein above-mentioned first scope is between one first standard and a second standard, and above-mentioned second is accurate lower than above-mentioned first standard; And
When this person of above-mentioned statistical value exceeds second scope, provide above-mentioned special code immediately, wherein above-mentioned second scope is between one the 3rd standard and one the 4th standard, and above-mentioned 4th standard is lower than above-mentioned 3rd standard,
Wherein above-mentioned 3rd standard is higher than above-mentioned first standard, and above-mentioned 4th standard is accurate lower than above-mentioned second.
18. DC balance methods according to claim 13, is characterized in that above-mentioned special code is that a DC balance code, confuses code or a modulation codes.
19. DC balance methods according to claim 14, also comprise:
According to a control signal, optionally provide above-mentioned data or above-mentioned special code to above-mentioned storer via this person of above-mentioned multiple driver.
20. DC balance methods according to claim 19, also comprise:
When above-mentioned statistical value indicates the quantity of the logical zero of the above-mentioned data recorded being provided to above-mentioned storer via this person of above-mentioned multiple driver and the quantity of logical one for time uneven, obtain a request signal.
21. DC balance methods according to claim 20, is characterized in that, provide above-mentioned special code more to comprise to the step of above-mentioned storer via this person of above-mentioned multiple driver:
Corresponding to above-mentioned request signal, stop providing above-mentioned data to above-mentioned storer; And
Corresponding to above-mentioned request signal, obtain above-mentioned control signal, to provide above-mentioned special code to above-mentioned storer via this person of above-mentioned multiple driver.
22. DC balance methods according to claim 14, also comprise:
According to a control signal, optionally provide above-mentioned data or above-mentioned special code to above-mentioned storer via All Drives.
23. DC balance methods according to claim 22, also comprise:
When the one of above-mentioned statistical value indicates the quantity of the logical zero of the above-mentioned data recorded being provided to above-mentioned storer via the driver of correspondence and the quantity of logical one for time uneven, obtain a request signal.
24. DC balance methods according to claim 23, is characterized in that, above-mentioned above-mentioned special code to the step of above-mentioned storer that provides more comprises:
Corresponding to above-mentioned request signal, stop providing above-mentioned data to above-mentioned storer; And
Corresponding to above-mentioned request signal, obtain above-mentioned control signal, to provide above-mentioned special code to above-mentioned storer via All Drives.
25. DC balance methods according to claim 13, it is characterized in that above-mentioned reference voltage is a supply voltage or a ground voltage, and this person of above-mentioned multiple driver receives this special code, so that adjustment corresponds to the above-mentioned terminal voltage of the electric capacity of this person of above-mentioned multiple driver, make an accurate general intermediate point position between above-mentioned supply voltage and above-mentioned ground voltage, the position of above-mentioned terminal voltage accurate.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161527345P | 2011-08-25 | 2011-08-25 | |
| US61/527,345 | 2011-08-25 | ||
| US201261595361P | 2012-02-06 | 2012-02-06 | |
| US61/595,361 | 2012-02-06 | ||
| US13/572,143 US8952718B2 (en) | 2011-08-25 | 2012-08-10 | Termination circuit and DC balance method thereof |
| US13/572,143 | 2012-08-16 |
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| Publication Number | Publication Date |
|---|---|
| CN103064801A CN103064801A (en) | 2013-04-24 |
| CN103064801B true CN103064801B (en) | 2015-08-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210303093.6A Active CN103064801B (en) | 2011-08-25 | 2012-08-23 | Terminating circuit, accumulator system and DC balance method |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1639982A (en) * | 2002-02-28 | 2005-07-13 | 泰克诺弗斯公司 | Multiplexing an additional bit stream with a primary bit stream |
| US7800399B1 (en) * | 2009-08-04 | 2010-09-21 | Broadcom Corporation | Virtual regulator for controlling a termination voltage in a termination circuit |
-
2012
- 2012-08-23 CN CN201210303093.6A patent/CN103064801B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1639982A (en) * | 2002-02-28 | 2005-07-13 | 泰克诺弗斯公司 | Multiplexing an additional bit stream with a primary bit stream |
| US7800399B1 (en) * | 2009-08-04 | 2010-09-21 | Broadcom Corporation | Virtual regulator for controlling a termination voltage in a termination circuit |
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| CN103064801A (en) | 2013-04-24 |
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