CN103064801B - Termination circuit, memory system, and DC balancing method - Google Patents

Abstract

The invention provides a terminal circuit, a memory system and a direct current balancing method. The memory system includes a termination circuit, a controller, and a plurality of memories. The termination circuit includes: a plurality of drivers, wherein each driver is coupled to the memory through a transmission line; a plurality of resistors, wherein each of the resistors is coupled to the corresponding driver through the corresponding transmission line; and a plurality of capacitors, wherein each capacitor is coupled between the corresponding resistor and a reference voltage. When the number of logic '0's and the number of logic '1's transmitted to the memory through the transmission line corresponding to one of the drivers are unbalanced, the controller provides a specific code to the one of the drivers so as to adjust a terminal voltage of the capacitor corresponding to the one of the drivers.

Description

Termination circuit, memory system, and DC balancing method

technical field

The present invention relates to a terminal circuit, and in particular to a memory system for data transmission between the terminal circuit and multiple memories.

Background technique

As system bandwidth continues to increase, storage technologies are optimized for higher speed and performance. The next generation of double data rate (double data rate, referred to as DDR) synchronous volatile memory (synchronous dynamic random access memory, referred to as SDRAM) is DDR3SDRAM. DDR3 SDRAM has more advantages than DDR2 SDRAM, such as lower operating power, higher speed, higher performance (2 times bandwidth), etc. Specifically, DDR3 SDRAM reduces power consumption compared to DDR2 SDRAM, which is mainly due to smaller die size and lower supply voltage (eg 1.5V for DDR3 SDRAM versus 1.8V for DDR2 SDRAM).

Unlike the T-branch topology of DDR2 SDRAM, DDR3 SDRAM uses a fly-by topology, which provides better signal integrity at higher speeds. The control topology is the command, address, control and frequency signals applied to DDR3 SDRAM. These signals from the memory controller are connected in series to each DRAM device, thus improving signal integrity by reducing the number and length of branches.

The terminal circuit usually provides a terminal impedance value to the common node of multiple DDR3 SDRAMs to avoid reducing the signal integrity of the DDR3 SDRAM transmission line. The common node can be at ground potential or at half potential between ground and the supply voltage, wherein the desired terminal voltage can be adjusted. For example, the memory termination circuitry of a DDR SDRAM may be required to provide a termination voltage at a common node that is about the same as one-half level of the supply voltage (eg, VDD). However, conventional termination circuits, such as conventional DDR DRAM termination circuits, lead to many disadvantages.

In conventional termination circuits, each transmission line is driven by a driver and coupled to a voltage adjustment node. The voltage adjustment node is coupled to the ground terminal through a terminal resistor connected in series and a terminal voltage regulator, wherein the terminal voltage regulator can provide and sink a special regulator of current. Although the termination voltage regulator can provide accurate termination voltage on the voltage regulation node, the termination voltage regulator is a separate component that adds to the manufacturing cost.

Therefore, there is a need for a termination circuit that does not use any termination voltage regulator.

Contents of the invention

In view of this, it is necessary to provide a termination circuit, a memory system, and a DC balancing method that do not use any termination voltage regulator.

In one embodiment, the present invention provides a terminal circuit suitable for transmitting data. The terminal circuit includes multiple drivers, multiple resistors and multiple capacitors. Each of the drivers provides data via a transmission line; each of the resistors is coupled to the corresponding driver via the corresponding transmission line; each of the capacitors is coupled between the corresponding resistor and a reference voltage, wherein when via When the number of logic "0"s and the number of logic "1" transmitted corresponding to the transmission line of one of the above-mentioned drivers are unbalanced, the one of the above-mentioned drivers receives a specific code and provides the specific code to the above-mentioned transmission line, In order to adjust a terminal voltage corresponding to the capacitor of the driver.

In another embodiment, the present invention also provides a memory system. The memory system includes terminal circuits, a controller, and a plurality of memories. The terminal circuit includes: a plurality of drivers, each of which is coupled to the memory via a transmission line; a plurality of resistors, wherein each of the above resistors is coupled to the corresponding driver via a corresponding transmission line; and a plurality of Capacitors, wherein each of the capacitors is coupled between the corresponding resistor and a reference voltage. When the number of logic "0"s and the number of logic "1" transmitted to the memory through the transmission line corresponding to one of the drivers are unbalanced, the controller provides a specific code to the one of the drivers, In order to adjust a terminal voltage corresponding to the capacitor of the driver.

In yet another embodiment, the present invention also provides a memory system adapted to transfer data to a plurality of memories via a termination circuit, wherein the termination circuit includes a plurality of drivers , a plurality of resistors and a plurality of capacitors, and the driver can be coupled to the memory via a plurality of transmission lines, each of the resistors is coupled to the corresponding driver via the corresponding transmission line, and each of the capacitors is coupled to the corresponding between the above resistance and a reference voltage. The DC balancing method includes: decoding an input signal to obtain data having address and command information; providing the data via the drivers; and when the number of logic "0"s of the data provided via one of the drivers When the number of AND logic "1"s is unbalanced, a specific code is provided via the one of the drivers to adjust a terminal voltage of the capacitor corresponding to the one of the drivers.

The above terminal circuit, memory system and DC balancing method can achieve the effect of balancing DC without using any terminal voltage regulator.

Description of drawings

FIG. 1 shows a memory system according to an embodiment of the present invention;

FIG. 2 shows a schematic diagram of the controller in FIG. 1 according to an embodiment of the present invention;

FIG. 3 shows a DC balancing method suitable for a memory system according to an embodiment of the present invention, wherein the memory system includes a controller, a terminal circuit, and a plurality of memories;

FIG. 4 shows a flowchart of a balancing program executed by the controller in FIG. 2 according to an embodiment of the present invention; and

FIG. 5 shows a schematic diagram of statistical values obtained by a judging unit in FIG. 2 .

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

FIG. 1 shows a memory system according to an embodiment of the invention. The memory system includes a controller 10 , a plurality of memories 30 ₁ - 30 _M , and a termination circuit 60 . The memories 30 ₁ - 30 _M are controlled by the controller 10 . In addition, the termination circuit 60 includes a plurality of drivers 20 ₁ -20 _N , a plurality of termination resistors R _T1 -R _TN and a plurality of termination capacitors C _T1 -C _TN . According to the input signal IN, the controller 10 will provide address signals and command signals to the memory 30 ₁ -30 _M through the drivers 20 ₁ -20 _N and the bus 50, such as write enable (write enable, WE for short) signal, row Address (column address signal, referred to as CAS) signal, column address signal (row address signal, referred to as RAS) signal and chip select (chipselect, referred to as CS) signal, wherein the bus 50 is formed by a plurality of transmission lines 40 ₁ -40 _N . In this embodiment, the memories 30 ₁ - 30 _M are double data rate dynamic random access devices. For each driver 20 ₁ - 20 _N , an individual termination resistor and an individual termination capacitance are used to provide termination voltages for corresponding signals provided by the controller 10 . For example, the terminal resistor R _T1 is coupled to the driver 20 ₁ , and the terminal capacitor C _T1 is coupled between the terminal resistor R _T1 and the ground terminal GND. In an embodiment, the termination capacitor C _T1 may be coupled between the termination resistor R _T1 and the supply voltage VDD.

Typically, the specification of a DDR DRAM requires that the resistive transmission line termination be terminated at a voltage close to the midpoint between the supply voltage VDD and the ground voltage GND (ie, the termination voltage). In FIG. 1, when the number of logic "0"s and the number of logic "1s" transmitted to the memories _301-30M via _one of the transmission lines of the bus 50 are unbalanced, by To provide a DC balance code (DC balance code) to the corresponding terminal capacitor via the transmission line, the controller 10 can adjust the terminal voltage on the corresponding terminal capacitor. The idle period represents the time period during which the bus 50 is inactive or driven to a "no operation" command (ie, NOP for short). Furthermore, the DC balanced code means that the long-term ratio of the transmitted logic "0" to logic "1" is about 50%. In other embodiments, the controller 10 may transmit the scrambling code or the modulation code during the idle period to control the terminal voltage on the corresponding terminal capacitor.

FIG. 2 shows a schematic diagram of the controller 10 in FIG. 1 according to an embodiment of the present invention. The controller 10 includes a decoder 110 , a scheduler 120 , a plurality of selectors 1301 - 130K and a plurality of judging units 140 ₁ - 140 _K . In this embodiment, each selector 130 ₁ - 130 _K is a multiplexer (MUX for short). The decoder 110 is used for decoding an input signal IN with multiple bits from other circuits (such as a processor) to obtain address data ADDR ₁ -ADDR _K or command data CMD ₁ -CMD _K or a combination thereof. The address data ADDR ₁ -ADDR _K and the command data CMD ₁ -CMD _K are transmitted to the drivers 20 ₁ -20 _M of FIG. 1 via the bus 150 formed by a plurality of transmission lines 160 ₁ -160 _K. Each judging unit 140 ₁ -140 _K is coupled to a corresponding transmission line in the bus 150, wherein each judging unit 140 ₁ -140 _K is used for recording data output to a corresponding driver. For example, the judging unit 140 ₁ is coupled to the transmission line 160 ₁ , and the judging unit 140 _K is coupled to the transmission line 160 _K . In addition, each judging unit 140 ₁ -140 _K can obtain a statistical value according to its recorded data. Each judging unit 140 ₁ -140 _K can provide a DC balanced code to the corresponding selector. According to the control signal SEL, each selector ₁₃₀ 1-130 _K will selectively provide address data ADDR ₁ -ADDR _K or command data CMD ₁ -CMD _K or a combination thereof, or a DC balance code CODE ₁ -CODE _K to the corresponding transmission line. For example, once one of the statistical values indicates that the quantity of logic “0” and the quantity of logic “1” in the output data are unbalanced, the judging unit that obtains the statistical value will provide the insertion signal INS ₁ , ... or INS _K to scheduler 120 . Corresponding to the insertion signal, the scheduler 120 provides a request signal REQ to the decoder 110 to notify the decoder 110 that the DC balanced code needs to be inserted. Therefore, the decoder 110 will provide the control signal SEL to control the selectors 130 ₁ -130 _K , and respectively output the DC balanced codes CODE ₁ -CODE _K provided by the judging units 140 ₁ -140 _K to the transmission line 160 ₁ - of the bus 150 160 _K so as to control the terminal voltage of the terminal capacitors C _T1 -C _TN in FIG. 1 to return to a level approximately at the middle point between the supply voltage VDD and the ground terminal GND. Simultaneously, the decoder 110 stops providing address data ADDR ₁ -ADDR _K and command data CMD ₁ -CMD _K to the selectors 130 ₁ -130 _K . As previously described, the control signal SEL controls the selectors 130 ₁ - 130 _K to provide DC balanced codes only during idle periods. The judging units 140 ₁ - 140 _K continue to record data on the bus 150 and obtain statistical values corresponding to the recorded data. By inserting the signals INS ₁ -INS _K , once all statistics indicate that the number of logic “0”s and the number of logic “1”s are balanced, the scheduler 120 will provide a request signal REQ to the decoder 110 to notify The decoder 110 does not need to insert a DC balanced code.

Furthermore, the DC balance codes CODE ₁ -CODE _K provided by the judging units 140 ₁ -140 _K may be the same or different. In FIG. 2, address data ADDR1- _ADDRK and command data _{CMD1 - CMDK} share the same transmission line. For example, the address data ADDR ₁ and the command data CMD ₁ share the transmission line 160 ₁ of the bus 150 , and the address data ADDR _K and the command data CMD _K share the transmission line 160 _K of the bus 150 . In one embodiment, the address data ADDR ₁ -ADDR _K and the command data CMD ₁ -CMD _K may not share the same transmission line. For example, each address data ADDR ₁ -ADDR _K and each command data CMD ₁ -CMD _K are transmitted to the memory through different selectors, different transmission lines of the bus 150 and different drivers.

FIG. 3 shows a DC balancing method suitable for a memory system according to an embodiment of the present invention, wherein the memory system includes a controller (such as the controller 10 in FIG. 1 ), a terminal circuit (such as the terminal circuit 60 in FIG. 1 ) and multiple memory (eg memory 30 ₁ -30 _M in Figure 1). First, in step S310, the decoder of the controller (such as the decoder 110 in Figure 1) decodes the input signal IN to obtain address data or command data or a combination thereof (such as address data ADDR ₁ -ADDR in Figure 2 _K or command data CMD ₁ -CMD _K or a combination thereof). Next, in step S320 , the controller transmits data to the memory via the drivers of the terminal circuit (such as the drivers 20 ₁ -20 _N in FIG. 1 ). Next, in step S330, the controller records the data transmitted to the memory via each driver. Next, in step S340, for each recorded data, the controller obtains a statistical value, wherein the statistical value is related to the number of logic "0"s and the number of logic "1"s in the recorded data. Next, in step S350, the controller executes a balancing procedure according to the statistical value to determine whether to insert a DC balancing code. Next, in step S360, when the statistical value indicates that the number of logic “0”s and the number of logic “1” of the recorded data transmitted to the memory via one of the drivers are unbalanced, the controller transmits a direct current through the driver. The balance code is stored in the memory so as to adjust the terminal voltage of the terminal circuit, or specifically adjust the terminal voltage corresponding to the driver.

FIG. 4 shows a flowchart of a balancing procedure executed by the controller 10 in FIG. 2 according to an embodiment of the present invention. FIG. 5 shows a schematic diagram of statistical values obtained by the judging unit 1401 in FIG. ₂ . In the controller 10, the judging unit 1401 can use _a low-pass filter to display the label A of the recorded data), and the judging unit 1401 will provide _an insertion signal _INS1 to the scheduler 120 to notify the scheduler 120 of the The statistical value has exceeded the first balance range BR1. Then, the scheduler 120 provides a request signal REQ to the decoder 110 . Next, in step S420 , the decoder 110 executes a first-stage DC balance procedure to stop providing the address data ADDR ₁ and the command data CMD ₁ -CMD _K to the selectors 130 ₁ -130 _K . Simultaneously, the decoder 110 provides the control signal SEL at an appropriate time point, so as to insert the DC balanced codes from the judging units 140 ₁ -140 _K into the bus 150 . Specifically, the controller 10 does not immediately insert the DC balanced code into the bus 150 . Next, in step S430, the judging unit ₁₄₀₁ will continue to record the data _on the transmission line 1601, and obtain statistical values according to the recorded data, so as to detect whether the statistical values still exceed the first balance range BR1. If the statistical value returns to the first balance range BR1, the judging unit 1401 provides _an insertion signal _INS1 to the scheduler 120 to notify the scheduler 120 that the statistical value does not exceed the first balance range BR1. Next, the scheduler 120 provides a request signal REQ to the decoder 110 to stop the first-stage DC balancing procedure (ie stop inserting the DC balancing code into the bus 150 ). If the statistical value still exceeds the _first balance range BR1, the judging unit 1401 further detects whether the statistical value exceeds the second balance range BR2 (step S440). The level L _2H and the level L _2L are respectively the upper limit and the lower limit of the second balance range BR2 in the second-stage DC balance procedure. Likewise, the level L _mid is an intermediate level between the levels L _2H and L _2L . In addition, the level L _2H is higher than the level L _1H , and the level L _2L is lower than the level L _1L . If the statistical value does not exceed the second balance range BR2, step S420 is executed, and then the decoder 110 continues to execute the first-stage DC balance procedure. Conversely, if the statistical value exceeds the second balance range BR2, for example, the statistical value reaches the level _L2H (as shown by the label B in FIG. 5), the judgment unit 1401 will provide _an insertion signal _INS1 to the scheduler 120 to notify the scheduler The statistical value of the controller 120 has exceeded the second balance range BR2. Then, the scheduler 120 will provide the request signal REQ to the decoder 110, and the decoder 110 will execute the second-stage DC balancing procedure (step S450), so as to immediately provide the control signal SEL to the selectors 130 ₁ -130 _K , thereby enabling Immediately insert the DC balance code until the judging unit 140 ₁ detects that the statistical value reaches the level L _off , as shown by the symbol C in FIG. 5 . In this embodiment, the level L _off is a level within the first balance range BR1. In addition, the level L _off can be greater than the level L _mid or smaller than the level L _mid . Furthermore, for each judging unit 140 ₁ -140 _K , the levels L _1H and L _1L , the levels L _2H and L _2L , and the level L _off can be set according to actual applications.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still be used for the foregoing The technical solutions recorded in the various embodiments are modified, or some of the technical features are replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the various embodiments of the present invention.

Claims (25)

1. a terminating circuit, is applicable to transmit data, comprises:

Multiple driver, wherein each above-mentioned driver provides data via a transmission line;

Multiple resistance, wherein each above-mentioned resistance is coupled to corresponding driver via the transmission line of correspondence; And

Multiple electric capacity, wherein each above-mentioned electric capacity has the first end being coupled to corresponding resistance and the second end being coupled to a reference voltage, wherein the first end of each above-mentioned electric capacity and the first end of other electric capacity electrically isolated, the quantity of the logical zero wherein transmitted when the transmission line via the one corresponding to above-mentioned multiple driver and the quantity of logical one are for time uneven, this person of above-mentioned multiple driver receives a special code and this special code is provided to corresponding transmission line, so that adjustment corresponds to a terminal voltage of the electric capacity of this person of above-mentioned multiple driver.

2. terminating circuit according to claim 1, is characterized in that, above-mentioned terminating circuit is also for obtaining multiple statistical value according to the quantity of logical zero of the above-mentioned data transmitted via each above-mentioned driver and the quantity of logical one.

3. terminating circuit according to claim 2, is characterized in that, when the statistical value of this person corresponding to above-mentioned multiple driver exceeds a particular range, this person of above-mentioned multiple driver receives this special code.

4. terminating circuit according to claim 2, is characterized in that, when the statistical value of this person corresponding to above-mentioned multiple driver exceeds a particular range, All Drives receives corresponding special code, to adjust the above-mentioned terminal voltage of above-mentioned electric capacity.

5. terminating circuit according to claim 1, is characterized in that, above-mentioned special code is that a DC balance code, confuses code or a modulation codes.

6. terminating circuit according to claim 1, it is characterized in that, above-mentioned reference voltage is a supply voltage or a ground voltage, and this person of above-mentioned multiple driver receives this special code, so that adjustment corresponds to the above-mentioned terminal voltage of the electric capacity of this person of above-mentioned multiple driver, make an accurate general intermediate point position between above-mentioned supply voltage and above-mentioned ground voltage, the position of above-mentioned terminal voltage accurate.

7. an accumulator system, it comprises just like the terminating circuit in claim 1-6 described in any one, one controller, and multiple storer, wherein, each above-mentioned driver is coupled to above-mentioned storer via the transmission line of correspondence, above-mentioned controller is coupled to above-mentioned storer via above-mentioned driver, and when via the quantity corresponding to the transmission line of one of above-mentioned multiple driver and the quantity that is sent to the logical zero of above-mentioned storer and logical one for imbalance time, above-mentioned controller provides a special code to this person of above-mentioned multiple driver, so that adjustment corresponds to a terminal voltage of the electric capacity of this person of above-mentioned multiple driver.

8. accumulator system according to claim 7, is characterized in that, above-mentioned controller comprises:

One demoder, in order to decode to an input signal, to provide the data with address and command information to above-mentioned storer; And

Multiple selector switch, is coupled between above-mentioned demoder and above-mentioned driver,

Wherein each above-mentioned selector switch optionally provides above-mentioned data or above-mentioned special code to corresponding driver according to a control signal.

9. accumulator system according to claim 8, is characterized in that, above-mentioned controller more comprises:

One scheduler, in order to insert signal corresponding to one, and provides a request signal to above-mentioned demoder; And

Multiple judging unit, wherein each judging unit is coupled to corresponding selector switch and the driver of correspondence,

The wherein data that exported by corresponding selector switch of each an above-mentioned judging unit record and statistical value is provided, and provide above-mentioned special code to corresponding selector switch, and when above-mentioned statistical value indicates the quantity of the logical zero of the above-mentioned data recorded and the quantity of logical one for time uneven, above-mentioned judging unit provides above-mentioned insertion signal to above-mentioned scheduler.

10. accumulator system according to claim 9, it is characterized in that, after receiving above-mentioned request signal, above-mentioned demoder stops providing above-mentioned data and providing the above-mentioned above-mentioned selector switch controlled signal to corresponding to the above-mentioned judging unit providing above-mentioned insertion signal, to control above-mentioned selector switch to provide above-mentioned special code to corresponding driver.

11. accumulator systems according to claim 9, it is characterized in that, after receiving above-mentioned request signal, above-mentioned demoder stops providing above-mentioned data and providing above-mentioned controlling signal to above-mentioned selector switch, to control above-mentioned selector switch to provide the above-mentioned special code extremely above-mentioned multiple driver from above-mentioned judging unit, to adjust the above-mentioned terminal voltage of above-mentioned electric capacity.

12. accumulator systems according to claim 7, is characterized in that, above-mentioned storer is the dynamic random access memory of Double Data Rate.

13. 1 kinds of DC balance methods, be applicable to transfer data to multiple storer by a terminating circuit, wherein above-mentioned terminating circuit comprises multiple driver, multiple resistance and multiple electric capacity, and above-mentioned driver can be coupled to above-mentioned storer via plurality of transmission lines, each above-mentioned resistance is coupled to corresponding driver via the transmission line of correspondence and each above-mentioned electric capacity is coupled between corresponding resistance and a reference voltage, and this DC balance method comprises:

To decode an input signal, to obtain the data with address and command information;

Via above-mentioned driver, provide above-mentioned data; And

When the quantity of the logical zero of the data provided via the one corresponding to above-mentioned multiple driver and the quantity of logical one are for time uneven, a special code is provided, so that adjustment corresponds to a terminal voltage of the electric capacity of this person of above-mentioned multiple driver via this person of above-mentioned multiple driver;

Wherein, each above-mentioned electric capacity has the first end being coupled to corresponding resistance and the second end being coupled to this reference voltage, and the first end of each above-mentioned electric capacity and the first end of other electric capacity electrically isolated.

14. DC balance methods according to claim 13, also comprise:

Record is provided to the above-mentioned data of above-mentioned storer via each above-mentioned driver; And

A statistical value is obtained according to the quantity of logical zero of each recorded above-mentioned data and the quantity of logical one.

15. DC balance methods according to claim 14, is characterized in that, when the statistical value of this person corresponding to above-mentioned multiple driver is more than a particular range, above-mentioned special code is provided to above-mentioned storer via this person of above-mentioned multiple driver.

16. DC balance methods according to claim 14, it is characterized in that, when the statistical value of this person corresponding to above-mentioned multiple driver is more than a particular range, above-mentioned special code is provided to above-mentioned storer via whole above-mentioned drivers, to adjust the above-mentioned terminal voltage of above-mentioned electric capacity.

17. DC balance methods according to claim 14, is characterized in that, provide above-mentioned special code also to comprise to the step of above-mentioned storer via this person of above-mentioned multiple driver:

When the one of above-mentioned statistical value exceeds first scope, between an idle period of above-mentioned storer, there is provided above-mentioned special code, wherein above-mentioned first scope is between one first standard and a second standard, and above-mentioned second is accurate lower than above-mentioned first standard; And

When this person of above-mentioned statistical value exceeds second scope, provide above-mentioned special code immediately, wherein above-mentioned second scope is between one the 3rd standard and one the 4th standard, and above-mentioned 4th standard is lower than above-mentioned 3rd standard,

Wherein above-mentioned 3rd standard is higher than above-mentioned first standard, and above-mentioned 4th standard is accurate lower than above-mentioned second.

18. DC balance methods according to claim 13, is characterized in that above-mentioned special code is that a DC balance code, confuses code or a modulation codes.

19. DC balance methods according to claim 14, also comprise:

According to a control signal, optionally provide above-mentioned data or above-mentioned special code to above-mentioned storer via this person of above-mentioned multiple driver.

20. DC balance methods according to claim 19, also comprise:

When above-mentioned statistical value indicates the quantity of the logical zero of the above-mentioned data recorded being provided to above-mentioned storer via this person of above-mentioned multiple driver and the quantity of logical one for time uneven, obtain a request signal.

21. DC balance methods according to claim 20, is characterized in that, provide above-mentioned special code more to comprise to the step of above-mentioned storer via this person of above-mentioned multiple driver:

Corresponding to above-mentioned request signal, stop providing above-mentioned data to above-mentioned storer; And

Corresponding to above-mentioned request signal, obtain above-mentioned control signal, to provide above-mentioned special code to above-mentioned storer via this person of above-mentioned multiple driver.

22. DC balance methods according to claim 14, also comprise:

According to a control signal, optionally provide above-mentioned data or above-mentioned special code to above-mentioned storer via All Drives.

23. DC balance methods according to claim 22, also comprise:

When the one of above-mentioned statistical value indicates the quantity of the logical zero of the above-mentioned data recorded being provided to above-mentioned storer via the driver of correspondence and the quantity of logical one for time uneven, obtain a request signal.

24. DC balance methods according to claim 23, is characterized in that, above-mentioned above-mentioned special code to the step of above-mentioned storer that provides more comprises:

Corresponding to above-mentioned request signal, stop providing above-mentioned data to above-mentioned storer; And

Corresponding to above-mentioned request signal, obtain above-mentioned control signal, to provide above-mentioned special code to above-mentioned storer via All Drives.

25. DC balance methods according to claim 13, it is characterized in that above-mentioned reference voltage is a supply voltage or a ground voltage, and this person of above-mentioned multiple driver receives this special code, so that adjustment corresponds to the above-mentioned terminal voltage of the electric capacity of this person of above-mentioned multiple driver, make an accurate general intermediate point position between above-mentioned supply voltage and above-mentioned ground voltage, the position of above-mentioned terminal voltage accurate.