CN103035637A - Electro-static discharge (ESD) component in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) process and manufacture method - Google Patents

Electro-static discharge (ESD) component in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) process and manufacture method Download PDF

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CN103035637A
CN103035637A CN2012101528561A CN201210152856A CN103035637A CN 103035637 A CN103035637 A CN 103035637A CN 2012101528561 A CN2012101528561 A CN 2012101528561A CN 201210152856 A CN201210152856 A CN 201210152856A CN 103035637 A CN103035637 A CN 103035637A
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injection region
type
lightly doped
doped drain
rfldmos
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CN103035637B (en
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段文婷
刘冬华
石晶
钱文生
胡君
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses an electro-static discharge (ESD) component in a radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) process. The ESD component is an N-channel metal oxide semiconductor (NMOS) component. An N type light dope drain injection region and an N type source drain injection region are formed in P traps on two side of a polycrystalline silicon gate, a second P type light dope drain injection region for reducing breakdown voltage of the ESD component is formed in the P trap on one side of a drain terminal of the polycrystalline silicon gate, and the junction depth of the second P type light dope drain injection region is larger than that of the N type source drain injection region. The invention further discloses a manufacture method for the ESD component in the RF LDMOS process. The manufacture method can reduce an extra source drain of the ESD component to be injected into a light cover so as to reduce process complexity, reduce process cost and improve competitiveness of the RF LDMOS process.

Description

ESD device and manufacture method in the RFLDMOS technique
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to the ESD device in a kind of RFLDMOS technique, the invention still further relates to the manufacture method of the ESD device in a kind of RFLDMOS technique.
Background technology
The electrostatic discharge (ESD) protection has very important effect in integrated circuit.Integrated circuit is very accurate product, and large scale integrated circuit is in order to reduce power consumption and to improve integrated level, and the variation tendency of operating voltage is to reduce always.But the residing external environment condition of integrated circuit contacts such as the weather of drying, with human body etc., can cause assembling on the integrated circuit modules some static, these static can be on the short time produces the high voltage of kilovolt.In this case, if this voltage does not obtain suitable release, circuit itself will be burnt, and causes circuit even thrashing.Esd protection plays this protective effect just.
The ESD circuit has the ESD device of particular design to consist of usually.The puncture voltage that to the key request of ESD device is exactly this ESD device is higher than the operating voltage of claimed device, but lower than the puncture voltage of claimed device.Requirement for the puncture voltage that realizes the ESD device; it is different that the condition of injecting is leaked in the condition that the source leakage of ESD device is injected and the source of claimed device; so usually can adopt extra light shield one; source and drain areas at the ESD device carries out extra Implantation one, is reduced to puncture voltage less than claimed device even reduce the puncture voltage of the puncture voltage ESD device of ESD device.Carry out so the source of ESD device leaks to inject to leak to inject to integrate with the source of claimed device, this needs extra cost and has increased the complexity that integrated circuit is made.
Summary of the invention
Technical problem to be solved by this invention provides the ESD device in a kind of RFLDMOS technique, and the injection light shield is leaked in the source that can reduce by one extra ESD device, can reduce the complexity of technique, reduces process costs, improves the competitiveness of RFLDMOS technique.For this reason, the present invention also provides the manufacture method of the ESD device in a kind of RFLDMOS technique.
For solving the problems of the technologies described above, the ESD device in the RFLDMOS technique provided by the invention is nmos device, comprising: be formed at the polysilicon gate on the P trap, isolation has gate dielectric layer between described polysilicon gate and the described P trap.Side, both sides at described polysilicon gate forms side wall.In the described P trap of described polysilicon gate both sides, be formed with N-type lightly doped drain injection region and N-type source and leak the injection region, the edge of the edge of described N-type lightly doped drain injection region and its contiguous described polysilicon gate is aimed at, and the edge of injection region is leaked in described N-type source and the outer ledge of its contiguous described side wall is aimed at; The junction depth of injection region is leaked greater than the junction depth of described N-type lightly doped drain injection region in described N-type source.Be formed with the 2nd P type lightly doped drain injection region for reducing the puncture voltage of described ESD device in the described P trap of drain terminal one side of described polysilicon gate, junction depth, described the 2nd P type lightly doped drain injection region that the junction depth of described the 2nd P type lightly doped drain injection region leaks the injection region greater than described N-type source are passed described N-type source and are leaked the injection region and enter into the described P trap that the bottom, injection region is leaked in described N-type source.The edge of the described polysilicon gate that the edge of described the 2nd P type lightly doped drain injection region and its are contiguous lateral separation of being separated by.
Further improve and be, the process conditions of the 2nd P type lightly doped drain injection region of the drain terminal of the P type LDMOS in the process conditions of described the 2nd P type lightly doped drain injection region and the described RFLDMOS technique are identical.
Further improve and be, the process conditions of the N-type lightly doped drain injection region of the source of the N-type LDMOS in the process conditions of described N-type lightly doped drain injection region and the described RFLDMOS technique are identical; The process conditions that the injection region is leaked in the N-type source of N-type LDMOS in the process conditions that the injection region is leaked in described N-type source and the described RFLDMOS technique are identical.
Further improve is that the lateral separation that the edge of the edge of described the 2nd P type lightly doped drain injection region and its contiguous described polysilicon gate is separated by is 0.5 micron～1.5 microns.
For solving the problems of the technologies described above, the invention provides the manufacture method of the ESD device in a kind of RFLDMOS technique, on the P trap, form after gate dielectric layer and the polysilicon gate, comprise the steps:
Step 1, carry out the N-type lightly doped drain and inject, form N-type lightly doped drain injection region in the described P trap of described polysilicon gate both sides, the edge of the edge of described N-type lightly doped drain injection region and its contiguous described polysilicon gate is aimed at.
Step 2, carry out the 2nd P type lightly doped drain and inject, in the described P trap of drain terminal one side of described polysilicon gate, form the 2nd P type lightly doped drain injection region.The edge of the described polysilicon gate that the edge of described the 2nd P type lightly doped drain injection region and its are contiguous lateral separation of being separated by.
Step 3, form side wall in the side, both sides of described polysilicon gate.
Step 4, carry out the N-type source and leak to inject, form the N-type source and leak the injection region in the described P trap of described polysilicon gate both sides, the edge of injection region is leaked in described N-type source and the outer ledge of its contiguous described side wall is aimed at; The junction depth of injection region is leaked greater than the junction depth of described N-type lightly doped drain injection region in described N-type source, and the junction depth of described the 2nd P type lightly doped drain injection region passes the described P trap that described N-type source is leaked the injection region and entered into bottom, leakage injection region, described N-type source greater than junction depth, described the 2nd P type lightly doped drain injection region that the injection region is leaked in described N-type source.
Further improve is that the process conditions that the process conditions that the lightly doped drain of N-type described in the step 1 injects and the N-type lightly doped drain of the source of the N-type LDMOS of described RFLDMOS technique inject are identical.
Further improve is that the process conditions that the 2nd P type lightly doped drain of the drain terminal of the process conditions that the 2nd P type lightly doped drain described in the step 2 injects and the P type LDMOS of described RFLDMOS technique injects are identical.The lateral separation that the edge of the edge of described the 2nd P type lightly doped drain injection region and its contiguous described polysilicon gate is separated by is 0.5 micron～1.5 microns.
Further improve is that the process conditions that described the 2nd P type lightly doped drain injects are: implanted dopant is boron, and implantation dosage is 1e 12Cm -2～5e 13Cm -2, Implantation Energy is 20KeV～60KeV.
Further improve is that the process conditions that the N-type source leakage of the process conditions that the leakage of the source of N-type described in the step 4 is injected and the N-type LDMOS of described RFLDMOS technique is injected are identical.
Further improve is that described N-type source is leaked the process conditions of injecting and is: implanted dopant is arsenic, and implantation dosage is 1e 15Cm -2～5e 16Cm -2, Implantation Energy is 20KeV～50KeV.
The source-drain area of ESD device of the present invention need not adopt the reduction that one extra light shield injects and realize the puncture voltage of ESD device, but increase the reduction that the puncture voltage of device is realized in the 2nd a P type lightly doped drain injection region at the drain terminal of ESD device, the beneficial effect that brings like this is: the N-type lightly doped drain injection region that forms the source-drain area of ESD device, the injection region is leaked in the N-type source and the process compatible with RFLDMOS can both be realized in the 2nd P type lightly doped drain injection region, the N-type lightly doped drain injection region that is the ESD device can be identical with the N-type lightly doped drain injection of the drain terminal of N-type LDMOS, the injection region is leaked in the N-type source of ESD device can be identical with the leakage injection region, N-type source of N-type LDMOS, the 2nd P type lightly doped drain injection region of ESD device can be identical with the 2nd P type lightly doped drain injection region of P type LDMOS, each doped region of the source-drain area of ESD device of the present invention like this forms when can form at the doped region of the N-type LDMOS of correspondence or P type LDMOS synchronously, and the formation of each doped region of the source-drain area of ESD device does not need extra light shield one.So with respect to prior art, the present invention can reduce the light shield of the source leakage injection of one ESD device, can reduce like this complexity of technique, reduces process costs, improves the competitiveness of RFLDMOS technique.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the device architecture schematic diagram of the N-type LDMOS in the existing RFLDMOS technique;
Fig. 2 is the device architecture schematic diagram of the P type LDMOS in the existing RFLDMOS technique;
Fig. 3 is the device architecture schematic diagram of the ESD device in the embodiment of the invention RFLDMOS technique;
Fig. 4 A-Fig. 4 C is the device architecture schematic diagram in each step of manufacture method of the ESD device in the embodiment of the invention RFLDMOS technique.
Embodiment
Including N-type LDMOS and P type LDMOS in the existing RFLDMOS technique, as illustrated in fig. 1 and 2, is respectively N-type in the existing RFLDMOS technique and the device architecture schematic diagram of P type LDMOS.
As shown in Figure 1, N-type LDMOS is formed on the P trap 12, and P trap 12 is formed on the P type substrate 11, and described N-type LDMOS comprises the polysilicon gate 14 that is formed on the described P trap 12, isolation has gate dielectric layer 13 between described polysilicon gate 14 and the described P trap 12, and gate dielectric layer 13 can be gate oxide; Be formed with side wall 17 in the side of polysilicon gate 14.
In the described P trap 12 of source one side of described polysilicon gate 14, be formed with N-type lightly doped drain injection region 15 and N-type source and leak injection region 18, the edge of the edge of described N-type lightly doped drain injection region 15 and its contiguous described polysilicon gate 14 is aimed at, and the edge of injection region 18 is leaked in described N-type source and the outer ledge of its contiguous described side wall 17 is aimed at; The junction depth of injection region 18 is leaked greater than the junction depth of described N-type lightly doped drain injection region 15 in described N-type source.It is the source region of device that injection region 18 is leaked in the described N-type source of this source one side.
In the described P trap 12 of drain terminal one side of described polysilicon gate 14, be formed with the second N-type lightly doped drain injection region 16 and N-type source and leak injection region 18, the edge of the described polysilicon gate 14 that the edge of described the second N-type lightly doped drain injection region 16 and its are contiguous is aimed at, the outer ledge that the edge of injection region 18 and its contiguous described side wall 17 are leaked in the described N-type source of the drain terminal one side segment distance of being separated by.The junction depth of injection region 18 is leaked less than the junction depth of described the second N-type lightly doped drain injection region 16 in described N-type source.Wherein, the described N-type source that is positioned at drain terminal one side is leaked injection region 18 and is the drain region of device.Described the second N-type lightly doped drain injection region 16 is used to form the drift region at drain terminal of device.Channel region by between described N-type lightly doped drain injection region 15 and described the second N-type lightly doped drain injection region 16 and the described P trap 12 that is covered by described polysilicon gate 14 form.
As shown in Figure 2, P type LDMOS is formed on the N trap 102, N trap 102 is formed on the P type substrate 101, described P type LDMOS comprises the polysilicon gate 104 that is formed on the described N trap 102, isolation has gate dielectric layer 103 between described polysilicon gate 104 and the described N trap 102, and gate dielectric layer 103 can be gate oxide; Be formed with side wall 107 in the side of polysilicon gate 104.
In the described N trap 102 of source one side of described polysilicon gate 104, be formed with P type lightly doped drain injection region 105 and P type source and leak injection region 108, the edge of the edge of described P type lightly doped drain injection region 105 and its contiguous described polysilicon gate 104 is aimed at, and the edge of injection region 108 is leaked in described P type source and the outer ledge of its contiguous described side wall 107 is aimed at; The junction depth of injection region 108 is leaked greater than the junction depth of described P type lightly doped drain injection region 105 in described P type source.It is the source region of device that injection region 108 is leaked in the described P type source of this source one side.
In the described N trap 102 of drain terminal one side of described polysilicon gate 104, be formed with the 2nd P type lightly doped drain injection region 106 and P type source and leak injection region 108, the edge of the described polysilicon gate 104 that the edge of described the 2nd P type lightly doped drain injection region 106 and its are contiguous is aimed at, the outer ledge that the edge of injection region 108 and its contiguous described side wall 107 are leaked in the described P type source of the drain terminal one side segment distance of being separated by.The junction depth of injection region 108 is leaked less than the junction depth of described the 2nd P type lightly doped drain injection region 106 in described P type source.Wherein, the described N-type source that is positioned at drain terminal one side is leaked injection region 18 and is the drain region of device.Described the second N-type lightly doped drain injection region 16 is used to form the drift region at drain terminal of device.Channel region by between described N-type lightly doped drain injection region 15 and described the second N-type lightly doped drain injection region 16 and the described P trap 12 that is covered by described polysilicon gate 14 form.
As shown in Figure 3, be the device architecture schematic diagram of the ESD device in the embodiment of the invention RFLDMOS technique.ESD device in the embodiment of the invention RFLDMOS technique is nmos device, comprising:
Be formed at the polysilicon gate 4 on the P trap 2, isolation has gate dielectric layer 3 between described polysilicon gate 4 and the described P trap 2.Described P trap 2 is formed on the P type substrate 1.Side, both sides at described polysilicon gate 4 forms side wall 7.
In the described P trap 2 of described polysilicon gate 4 both sides, be formed with N-type lightly doped drain injection region 5 and N-type source and leak injection region 8, the edge of the edge of described N-type lightly doped drain injection region 5 and its contiguous described polysilicon gate 4 is aimed at, and the edge of injection region 8 is leaked in described N-type source and the outer ledge of its contiguous described side wall 7 is aimed at; The junction depth of injection region 8 is leaked greater than the junction depth of described N-type lightly doped drain injection region 5 in described N-type source.In the embodiment of the invention, the process conditions of the N-type lightly doped drain injection region 15 of the source of the N-type LDMOS in the process conditions of described N-type lightly doped drain injection region 5 and the described RFLDMOS technique as shown in Figure 1 are identical; The process conditions of leakage injection region 18, N-type source that the N-type LDMOS in the process conditions of injection region 8 and the described RFLDMOS technique is as shown in Figure 1 leaked in described N-type source are identical.
Be formed with the 2nd P type lightly doped drain injection region 6 for reducing the puncture voltage of described ESD device in the described P trap 2 of drain terminal one side of described polysilicon gate 4, junction depth, described the 2nd P type lightly doped drain injection region 6 that the junction depth of described the 2nd P type lightly doped drain injection region 6 leaks injection region 8 greater than described N-type source are passed described N-type source and are leaked injection region 8 and enter into the described P trap 2 that 8 bottoms, injection region are leaked in described N-type source.The edge of the described polysilicon gate that the edge of described the 2nd P type lightly doped drain injection region and its are contiguous size of being separated by is 0.5 micron～1.5 microns lateral separation.The process conditions of the 2nd P type lightly doped drain injection region 106 of the drain terminal of the P type LDMOS in the process conditions of described the 2nd P type lightly doped drain injection region 6 and the described RFLDMOS technique as shown in Figure 2 are identical.In the embodiment of the invention, the source region of ESD device is leaked injection region 8 by the described N-type source that is positioned at source and is formed, the drain region is leaked injection region 8 by the described N-type source that is positioned at drain terminal and is formed, and described the 2nd P type lightly doped drain injection region 6 is then for reducing the puncture voltage of described ESD device.
As from the foregoing, the described N-type source of the embodiment of the invention leak injection region 8, N-type lightly doped drain injection region 5 and the 2nd P type lightly doped drain injection region 6 can both with existing RFLDMOS process compatible, so the formation of each doped region of the source-drain area of ESD device does not need extra light shield one.So with respect to prior art, the present invention can reduce the light shield of the source leakage injection of one ESD device, can reduce like this complexity of technique, reduces process costs, improves the competitiveness of RFLDMOS technique.
Shown in Fig. 4 A to Fig. 4 C, it is the device architecture schematic diagram in each step of manufacture method of the ESD device in the embodiment of the invention RFLDMOS technique.The manufacture method of the ESD device in the embodiment of the invention RFLDMOS technique comprises step:
Shown in Fig. 4 A, at first be to form P trap 2 at a P type substrate 1, on P trap 2, form gate dielectric layer 3 and polysilicon gate 4, wherein gate dielectric layer 3 can be a gate oxide.Afterwards, comprise the steps:
Step 1, shown in Fig. 4 B, carry out the N-type lightly doped drain and inject, in the described P trap 2 of described polysilicon gate 4 both sides, form N-type lightly doped drain injection region 5, the edge of the edge of described N-type lightly doped drain injection region 5 and its contiguous described polysilicon gate 4 is aimed at.The process conditions that the process conditions that described N-type lightly doped drain injects and the N-type lightly doped drain of the source of the N-type LDMOS of described RFLDMOS technique inject are identical, and namely the N-type lightly doped drain of the source of the N-type LDMOS of this injection energy and described RFLDMOS technique injects and carries out simultaneously.
Step 2, shown in Fig. 4 B, carry out the 2nd P type lightly doped drain and inject, in the described P trap 2 of drain terminal one side of described polysilicon gate 4, form the 2nd P type lightly doped drain injection region 6.The process conditions that the 2nd P type lightly doped drain of the drain terminal of the process conditions that described the 2nd P type lightly doped drain injects and the P type LDMOS of described RFLDMOS technique injects are identical, and namely the 2nd P type lightly doped drain of the drain terminal of the P type LDMOS of this injection energy and described RFLDMOS technique injects and carries out simultaneously.The process conditions that described the 2nd P type lightly doped drain injects are: implanted dopant is boron, and implantation dosage is 1e 12Cm -2～5e 13Cm -2, Implantation Energy is 20KeV～60KeV.
Step 3, shown in Fig. 4 C, form side wall 7 in the side, both sides of described polysilicon gate 4.
Step 4, is as shown in Figure 3 carried out the N-type source and is leaked and inject, and forms the N-type source and leak injection region 8 in the described P trap 2 of described polysilicon gate 4 both sides, and the edge of injection region 8 is leaked in described N-type source and the outer ledge of its contiguous described side wall 7 is aimed at; The junction depth of injection region 8 is leaked greater than the junction depth of described N-type lightly doped drain injection region 5 in described N-type source, and the junction depth of described the 2nd P type lightly doped drain injection region 6 passes the described P trap 2 that described N-type source is leaked injection region 8 and entered into leakage 8 bottoms, injection region, described N-type source greater than junction depth, described the 2nd P type lightly doped drain injection region 6 that injection region 8 is leaked in described N-type source.The process conditions that injection is leaked in the process conditions that the leakage of described N-type source is injected and the N-type source of the N-type LDMOS of described RFLDMOS technique are identical, and namely this N-type source of injecting the N-type LDMOS of energy and described RFLDMOS technique is leaked to inject and carried out simultaneously.The process conditions of injecting are leaked in described N-type source: implanted dopant is arsenic, and implantation dosage is 1e 15Cm -2～5e 16Cm -2, Implantation Energy is 20KeV～50KeV.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (10)

1. the ESD device in the RFLDMOS technique, the ESD device is nmos device, comprising:
Be formed at the polysilicon gate on the P trap, isolation has gate dielectric layer between described polysilicon gate and the described P trap;
Side, both sides at described polysilicon gate forms side wall;
In the described P trap of described polysilicon gate both sides, be formed with N-type lightly doped drain injection region and N-type source and leak the injection region, the edge of the edge of described N-type lightly doped drain injection region and its contiguous described polysilicon gate is aimed at, and the edge of injection region is leaked in described N-type source and the outer ledge of its contiguous described side wall is aimed at; The junction depth of injection region is leaked greater than the junction depth of described N-type lightly doped drain injection region in described N-type source;
It is characterized in that, also comprise:
Be formed with the 2nd P type lightly doped drain injection region for reducing the puncture voltage of described ESD device in the described P trap of drain terminal one side of described polysilicon gate, junction depth, described the 2nd P type lightly doped drain injection region that the junction depth of described the 2nd P type lightly doped drain injection region leaks the injection region greater than described N-type source are passed described N-type source and are leaked the injection region and enter into the described P trap that the bottom, injection region is leaked in described N-type source; The edge of the described polysilicon gate that the edge of described the 2nd P type lightly doped drain injection region and its are contiguous lateral separation of being separated by.
2. the ESD device in the RFLDMOS technique as claimed in claim 1 is characterized in that: the process conditions of the 2nd P type lightly doped drain injection region of the drain terminal of the P type LDMOS in the process conditions of described the 2nd P type lightly doped drain injection region and the described RFLDMOS technique are identical.
3. the ESD device in the RFLDMOS technique as claimed in claim 1 is characterized in that: the process conditions of the N-type lightly doped drain injection region of the source of the N-type LDMOS in the process conditions of described N-type lightly doped drain injection region and the described RFLDMOS technique are identical; The process conditions that the injection region is leaked in the N-type source of N-type LDMOS in the process conditions that the injection region is leaked in described N-type source and the described RFLDMOS technique are identical.
4. the ESD device in the RFLDMOS technique as claimed in claim 1, it is characterized in that: the lateral separation that the edge of the edge of described the 2nd P type lightly doped drain injection region and its contiguous described polysilicon gate is separated by is 0.5 micron～1.5 microns.
5. the manufacture method of the ESD device in the RFLDMOS technique is characterized in that, forms after gate dielectric layer and the polysilicon gate on the P trap, comprises the steps:
Step 1, carry out the N-type lightly doped drain and inject, form N-type lightly doped drain injection region in the described P trap of described polysilicon gate both sides, the edge of the edge of described N-type lightly doped drain injection region and its contiguous described polysilicon gate is aimed at;
Step 2, carry out the 2nd P type lightly doped drain and inject, in the described P trap of drain terminal one side of described polysilicon gate, form the 2nd P type lightly doped drain injection region; The edge of the described polysilicon gate that the edge of described the 2nd P type lightly doped drain injection region and its are contiguous lateral separation of being separated by
Step 3, form side wall in the side, both sides of described polysilicon gate;
Step 4, carry out the N-type source and leak to inject, form the N-type source and leak the injection region in the described P trap of described polysilicon gate both sides, the edge of injection region is leaked in described N-type source and the outer ledge of its contiguous described side wall is aimed at; The junction depth of injection region is leaked greater than the junction depth of described N-type lightly doped drain injection region in described N-type source, and the junction depth of described the 2nd P type lightly doped drain injection region passes the described P trap that described N-type source is leaked the injection region and entered into bottom, leakage injection region, described N-type source greater than junction depth, described the 2nd P type lightly doped drain injection region that the injection region is leaked in described N-type source.
6. the manufacture method of the ESD device in the RFLDMOS technique as claimed in claim 5 is characterized in that: the process conditions that the process conditions that the lightly doped drain of N-type described in the step 1 injects and the N-type lightly doped drain of the source of the N-type LDMOS of described RFLDMOS technique inject are identical.
7. the manufacture method of the ESD device in the RFLDMOS technique as claimed in claim 5 is characterized in that: the process conditions that the 2nd P type lightly doped drain of the drain terminal of the process conditions that the 2nd P type lightly doped drain described in the step 2 injects and the P type LDMOS of described RFLDMOS technique injects are identical; The lateral separation that the edge of the edge of described the 2nd P type lightly doped drain injection region and its contiguous described polysilicon gate is separated by is 0.5 micron～1.5 microns.
8. the manufacture method of the ESD device in the RFLDMOS technique as claimed in claim 7 is characterized in that: the process conditions that described the 2nd P type lightly doped drain injects are: implanted dopant is boron, and implantation dosage is 1e 12Cm -2～5e 13Cm -2, Implantation Energy is 20KeV～60KeV.
9. the manufacture method of the ESD device in the RFLDMOS technique as claimed in claim 5 is characterized in that: it is identical that the process conditions of injecting are leaked in the N-type source that the process conditions injected and the N-type LDMOS of described RFLDMOS technique are leaked in the source of N-type described in the step 4.
10. the manufacture method of the ESD device in the RFLDMOS technique as claimed in claim 9 is characterized in that: described N-type source is leaked the process conditions of injecting and is: implanted dopant is arsenic, and implantation dosage is 1e 15Cm -2～5e 16Cm -2, Implantation Energy is 20KeV～50KeV.
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