CN103035010A - Digital picture contour extraction method - Google Patents

Abstract

The invention provides a digital picture contour extraction method and relates to a digital image processing technique. The method includes the first step of observing a divided image and initiating a curve, the second step of initiating a speed evolvement function and obtaining a speed evolvement image V, the third step of carrying out expansive working on the initiated binary image A obtained from the first step to obtain an image E through expansion, and taking B as a value of a 3*3 structural element, the fourth step of updating a level set function, namely updating the binary image A, and the fifth step of returning to the third step and continuing operation. According to the characteristics of field programmable gate array (FPGA), the contour extraction method based on a form level set is put forward, and floating point arithmetic and parallel calculation for each pixel are needless; the Handel-C language which is quicker and more efficient than a traditional hardware description language is adopted; and circuits with modified structures are adopted in Dilation and Erosion submodules in an image processing submodule, the image is scanned once and image effects of the whole template operation can be obtained.

Description

A kind of digital picture contour extraction method

Technical field

The present invention relates to a kind of digital image processing techniques, particularly relate to a kind of digital picture contour extraction method based on the form level set that is suitable for Parallel Implementation on FPGA.

Background technology

The profile of digital picture extracts need to carry out a large amount of data calculating usually.Although at present the computing velocity of CPU is more and more faster, inefficiency often in the face of complicated Processing Algorithm or high-resolution image the time.

In the modern digital circuits design, FPGA is bringing into play more and more important effect.Comprise simple interface circuit design, the design of state machine and SoC, the FPGA role can not be ignored.FPGA is widely used in image processing system as a kind of device of widespread use in the at present electronic design automation tool design.

In numerous image outline extraction algorithms, be current study hotspot based on dividing method or the movable contour model of energy functional, it comprise take the Snake model as representative parametric active contour model and based on the geometric active contour model of Level Set Method.M.Kass for example, A.Witkins, the paper that D.Terzopoulos delivered in 1988 " Snakes:active contourmodels " just belongs to the former, and N.Paragios, the paper that R.Deriche delivered in 2000 " Geodesic active contoursand level sets for the detection and tracking of moving objects " then belongs to the latter.The basic thought of movable contour model is to express objective contour with continuous curve, and define an energy functional so that its independent variable comprises curve, cutting procedure is changed into the process of the minimum value of finding the solution energy functional, obtain numerical value by Eulerian equation corresponding to solved function again.But it is usually comparatively complicated to find the solution Eulerian equation, need to expend considerable time calculates, and traditional method also is unfavorable for adopting parallel mode to calculate, and more is unfavorable for realizing accelerating parallel at FPGA for the algorithm that needs are used the floating number operation.Image outline extraction algorithm based on the form level set of the present invention can be realized parallel computation, and calculates simply, does not need to carry out floating point arithmetic, thereby is adapted at the upper realization of FPGA; And the method that adopts possesses the character of curvilinear structures topology, can be applied to the medical image of environmental structure complexity, and can control comparatively easily the evolution of curve by threshold parameter is set, thereby overcome medical image brightness irregularities etc. to the impact of model extraction.

Hardware description language is most important input method in the FPGA design, and VHDL and Verilog HDL are most widely used two kinds of hardware description languages.Can describe structure, behavior, function and the interface of digital display circuit by this bilingual, thereby finish the modeling of digital display circuit.Need to be to hardware details understanding very but use VHDL and Verilog HDL language to do exploitation, this will limit the use of FPGA to a certain extent.And for comparatively complicated algorithm such as image, voice, radar, software radio etc., if adopt hardware description language to write code, will be very consuming time then, and easily mistake occur.

Summary of the invention

The object of the present invention is to provide a kind of digital picture contour extraction method.

The present invention realizes the real time algorithm that the digital picture profile extracts at FPGA, can make digital picture profile extraction algorithm meet FPGA hardware configuration and operating characteristic, and realize the hardware module of this algorithm with FPGA.This module adopts the Handel-C language to realize.

The objective of the invention is to be achieved through the following technical solutions:

Of the present invention a kind of at FPGA realization image outline extracting method, its implementation platform is FPGA, adopt the Handel-C language description to realize, whole module is divided into reading of view data, the processing of view data, and three submodules of the storage of view data, three modules adopt pipeline system parallel, wherein, the principal character of this invention is the processing submodule of view data.

In the processing submodule of above-mentioned view data, the data serial input, including again Dilation(in the submodule expands), And(with), Not(is non-), the Erosion(corrosion), the FIFO(first in first out) the secondary submodule, adopt pipeline system to walk abreast between these secondary submodules.

The processing submodule of above-mentioned view data can be realized the expansion of image outline, and the result of the expansion of image outline carries out profile to target image to extract, and the algorithm of institute's basis is based on the digital picture profile extraction algorithm of form level set.

This digital picture contour extraction method is to realize at FPGA, and is based on the form level set, thereby realizes the expansion of curved profile.

The present invention includes following steps:

1) observes divided image, one of initialization is long to be long pixel, wide is the curve of width pixel, long and width are integers, and this curve is called C, and wherein long and width can set according to divided image, the principle of setting is that this curve is fully inner at target image, on image, the initialization level set function obtains initialization bianry image A; The formula of described initialization level set function foundation is as follows:

(formula 1)

Wherein x represents the pixel position, and t represents time variable;

2) initialization speed evolution function obtains speed Evolution maps V, order

$V=\left\{\begin{array}{cc}0& ,F=\mathrm{0,1}\\ 1& ,F=-1\end{array}\right.$ (formula 2)

Wherein F is speed evolution function, and the formula of initialization evolution function foundation is as follows:

(formula 3)

3) the initialization bianry image A that step 1) is obtained carries out expansive working, obtains image E, and E is the image of expansion gained, and B is 3 * 3 structural element, and the value of this structural element can be set according to the shape and size of concrete image,

$E=A\⊕B$ (formula 4)

Expansive working wherein is defined as follows:

$A\⊕B=\left\{c\right|c=a+b,a\∈A,b\∈B\}$ (formula 5)

Wherein a represents a pixel among the A, and b represents a pixel among the B, and c represents a pixel of the rear new images of this operation;

4) upgrade level set function, namely upgrade bianry image A:

(formula 6)

Corrosion Operation Definition wherein is as follows:

A Θ B={c|c+b ∈ A, b ∈ B} (formula 7)

A wherein, b, the implication of c is with formula 5;

5) return step 3) and continue operation;

The leaching process of image outline is an iterative process, obtains objective contour by the dilation and corrosion operation, when iteration satisfies one of following two conditions, stops iteration, and image outline extracts and finishes:

(a) twice continuous objective contour image is the same;

(b) iterations reaches the maximal value of setting.

The Dilation(that processes in the submodule for above-mentioned view data expands) and the Erosion(corrosion) the secondary submodule, the present invention has adopted the circuit that improves structure, the serial data input is adopted in this input that improves structure, then through 2 * N+2 shift register, wherein N is the columns of input picture, again from wherein selecting specific 9 registers as each template that participates in calculating.Each clock, shift register moves one, and the data of 9 registers are upgraded, and produce new template and participate in calculating next time.Like this can be so that as long as scan image just can obtain the image effect of whole template operation for one time.

Useful effect of the present invention is:

The present invention is directed to the characteristics of FPGA, proposed the profile extraction algorithm based on the form level set, this algorithm need not carry out floating-point operation and adopt parallel mode to calculate to each pixel; The present invention adopts the Handel-C language that above-mentioned algorithm is realized at FPGA, than conventional hardware descriptive language rapidly and efficiently; Image of the present invention is processed Dilation (expansion) and Erosion (corrosion) submodule in the submodule, adopt the circuit that improves structure, so that as long as scan image just can obtain the image effect of whole template operation for one time, and traditional processing mode needs image scanning 9 times.

Handel-C language of the present invention is the high-level programming language of a kind of ISO/ANSI-C of originating from, and added that some simple structures and expansion form, as comprises the parallel processing that is fit to hardware, flexibly data bit width operation etc.Its standard is proposed by Celoxica company, Celoxica DK external member by the said firm's exploitation can realize quick hardware design and realize complicated algorithm, and can be convenient to use the bank code of software, even can with VHDL or Verilog program hybrid programming, accelerate design rate by reusing code, so that design is tending towards modularization.

In actual hardware is realized, by to based on the profile extraction algorithm analysis of form level set as can be known, the operation of image more complicated is Dilation and Erosion operation (being dilation and corrosion), need to use 3 * 3 square window template, spatially be continuous with pixel corresponding to delegation on the template, then there is certain space phase in the pixel of different rows.Obtain the pixel value of a bit, need 9 clocks of cost to come RAM is read 9 times, and then process, whole computation process is equivalent to an image reading 9 times.The method has seriously limited the image outline extraction rate of algorithm.Improvement hardware configuration of the present invention needs only scan image one time, just can obtain the image effect of whole template operation.

Description of drawings

Fig. 1 is the hardware realization figure that this profile extraction algorithm is realized process of expansion.

Fig. 2 is the hardware realization figure after Dilation (expansion) or Erosion (corrosion) module adopt the improvement structure.

Fig. 3 carries out the Seed Points chosen before the process of expansion.

Fig. 4 is for to carry out binaryzation to the zone at Seed Points square frame place.

Fig. 5 is the result after input picture carries out binaryzation.

Fig. 6 carries out the profile result that extracts after the process of expansion.

Embodiment

The present invention will be further described below in conjunction with drawings and Examples.Following embodiment only is used for description and interpretation the present invention, and does not consist of the restriction to technical solution of the present invention.

Select the FPGA device of xc6vhx565t-2ff1923 model, according to the profile extraction algorithm based on the form level set, with the described realization of Handel-C language, the processing module of view data wherein finally extracts the profile of image thereby this module has realized the expansion of image outline as shown in Figure 1.

The arthmetic statement of this module is carried out according to following steps:

1. choose the image of 240 * 240 resolution, observe divided image, the initialization curve C makes target fully outside in curve C, is curve C such as the Seed Points square frame among Fig. 3.On image, the Seed Points square frame is carried out binaryzation, obtain image A, as shown in Figure 4.Image A is equivalent to Contour (n) in Fig. 1.

2. initialization speed evolution function obtains speed Evolution maps V, as shown in Figure 5.This speed Evolution maps is the binaryzation result of input picture.Wherein binary-state threshold can manually be set according to different images.The binary image of this moment not only comprises the target image profile, also comprises other outer noise profiles of image outline, such as the white blocks of Fig. 5 top.Image V is equivalent to VImage in Fig. 1.

3. bianry image A is carried out expansive working and obtain image E, namely

Wherein B is 3 * 3 structural element, is defined as in this example

0	1	0
			1	1	1
0	1	0

Expansive working is corresponding to the Dilation module among Fig. 1, the DImage in the image E corresponding diagram 1.

4. the renewal level set function namely upgrades bianry image A: according to formula And in the corresponding diagram 1, Not, Erosion, And and fifo module.T among Fig. 1 is an image, and it is the image that obtains after image E and each pixel of image V are carried out step-by-step and operated; TI is for also being an image, and it is that each pixel among the image T is carried out the image that obtains after the negate; TE also is an image, and it is image TI through the Erosion module, and the image of structural element B after corroding.

View data is processed through Dilation and Erosion, the resolution of capital generation L(L and selected picture is relevant) individual delay, image adopts the streamline formal layout, at And, therefore each delay that can produce data of Not place when carrying out second And processing, needs FIFO to store L+2 data, could carry out with the data TE that the Erosion module draws And and process, reach synchronous purpose.

This moment, the A that obtains was the image outline data Contour (n+1) of iteration after once, deposited these data in SDRAM.

5. take out Contour (n) in SDRAM, when iteration satisfies one of following two conditions, stop iteration, image outline extracts and finishes:

(a) twice continuous objective contour image is the same, and namely Contour (n) equals Contour (n+1);

(b) iterations reaches the maximal value of setting.

If do not satisfy above-mentioned condition, then return step 3 and continue operation.

For the Dilation among Fig. 1 and Erosion module, the present invention has adopted the serial data input mode, and through 2 * N+2 shift register, wherein N is the columns of input picture, such as N=240 among the embodiment.From wherein selecting specific 9 registers as each template that participates in calculating, these 9 registers are DIN as shown in Figure 2, D0, D1, D2, D3, D4, D5, and the output of two shift registers again.DIN wherein is input register, and D0, D1, D2, D3, D4, D5 all are general registers.Each clock, all register datas move one, and the data of 9 registers are upgraded, and produce new template and participate in calculating next time.Like this can be so that as long as scan image just can obtain the image effect of whole template operation for one time.A0 among Fig. 2, A1, A2, B0, B1, B2, C0, C1, C2 is respectively capable adjacent three row (A0, A1, A2) of certain AA in the image that participates in expansion or corrosion operation, adjacent three row (B0, B1, B2) that BB is capable, adjacent three row (C0, C1, C2) that CC is capable, and AA, BB, CC expands or corrodes three adjacent row in the image that operates for participating in.

Above explanation only is a specific embodiment of the present invention; but protection scope of the present invention is not limited to this; those skilled in the art are in the technical scope that the present invention discloses, and the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.

Claims (1)

1. digital picture contour extraction method is characterized in that may further comprise the steps:

1) observes divided image, one of initialization is long to be long pixel, wide is the curve of width pixel, long and width are integers, and this curve is called C, and wherein long and width can set according to divided image, the principle of setting is that this curve is fully inner at target image, on image, the initialization level set function obtains initialization bianry image A; The formula of described initialization level set function foundation is as follows:

(formula 1)

Wherein x represents the pixel position, and t represents time variable;

2) initialization speed evolution function obtains speed Evolution maps V, order

$V=\left\{\begin{array}{cc}0& ,F=\mathrm{0,1}\\ 1& ,F=-1\end{array}\right.$ (formula 2)

Wherein F is speed evolution function, and the formula of initialization evolution function foundation is as follows:

(formula 3)

3) the initialization bianry image A that step 1) is obtained carries out expansive working, obtains image E, and E is the image of expansion gained, and B is 3 * 3 structural element, and the value of this structural element can be set according to the shape and size of concrete image,

$E=A\⊕B$ (formula 4)

Expansive working wherein is defined as follows: $A\⊕B=\left\{c\right|c=a+b,a\∈A,b\∈B\}$ (formula 5)

Wherein a represents a pixel among the A, and b represents a pixel among the B, and c represents a pixel of the rear new images of this operation;

4) upgrade level set function, namely upgrade bianry image A:

(formula 6)

Corrosion Operation Definition wherein is as follows:

A Θ B={c|c+b ∈ A, b ∈ B} (formula 7)

A wherein, b, the implication of c is with formula 5;

5) return step 3) and continue operation;

The leaching process of image outline is an iterative process, obtains objective contour by the dilation and corrosion operation, when iteration satisfies one of following two conditions, stops iteration, and image outline extracts and finishes:

(a) twice continuous objective contour image is the same;

(b) iterations reaches the maximal value of setting.

Images