CN103026332B

CN103026332B - Programmable device, level parallel machine, for the method that provides status information

Info

Publication number: CN103026332B
Application number: CN201180035858.6A
Authority: CN
Inventors: 保罗·德卢戈施
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2010-06-10
Filing date: 2011-06-09
Publication date: 2016-11-30
Anticipated expiration: 2031-06-09

Abstract

The present invention describes programmable device, level parallel machine and for the method providing status information.In this kind of programmable device, it is provided that programmable element.Described programmable element is configured to implement one or more finite state machines.Described programmable element is configured to receive the input of N numeral and provide M-digit output according to the input of described N numeral.The output of described M-digit includes from the status information all or fewer than described programmable element.The present invention also discloses other programmable device, level parallel machine and method.

Description

Programmable device, level parallel machine, for the method that provides status information

The cross reference of related application

Present application for patent advocate on March 1st, 2011 file an application entitled " programmable device, level parallel machine, For providing method (Programm able Device, Hierarchical the Parallel Machines, Methods of status information For Providing State Information) " the benefit of priority of the 13/037th, No. 706 U. S. application case, the described U.S. Application case according to 35U.S.C. 119 (e) money advocate to file an application for 2010 June 10 days entitled " for having System and method (the System and Method for Transferring State Between of state is transmitted between limit state machine Finite State Machine) " the benefit of priority of the 61/353rd, No. 551 U.S. Provisional Patent Application case, described application Case both of which is hereby incorporated into herein in entirety by reference.

Technical field

Background technology

One example of programmable device is parallel machine.Parallel machine includes that (such as) finite state machine (FSM) engine and scene can Programming gate array (FPGA).FSM is state representation, changes between state and action.Finite state machine can be oriented The form of flow chart is expressed.It may be used to solve asking in (such as) engineering, pattern identification, biology and artificial intelligence Topic.

Summary of the invention

Accompanying drawing explanation

The example of Fig. 1 graphic extension level parallel machine according to various embodiments of the present invention.

The reality of Fig. 2 graphic extension level parallel machine being configured for use in pattern identification according to various embodiments of the present invention Example.

The example of Fig. 3 graphic extension parallel machine according to various embodiments of the present invention.

The example of Fig. 4 graphic extension finite state machine diagram according to various embodiments of the present invention.

Another example of Fig. 5 graphic extension finite state machine diagram according to various embodiments of the present invention.

Another reality of Fig. 6 graphic extension two rank level implemented by parallel machine according to various embodiments of the present invention Example.

The example of Fig. 7 graphic extension four level levels implemented by parallel machine according to various embodiments of the present invention.

The example of Fig. 8 graphic extension finite state machine diagram group according to various embodiments of the present invention.

Another example of Fig. 9 graphic extension finite state machine diagram according to various embodiments of the present invention, is wherein polymerized to scheme The end-state of the state machine that solution mode is illustrated.

Another example of Figure 10 graphic extension finite state machine diagram group according to various embodiments of the present invention, Qi Zhongju Close the end-state of each in the most illustrated finite state machine.

The example of Figure 11 graphic extension programmable element array according to various embodiments of the present invention.

The example of Figure 12 graphic extension pattern-recognition processor stacking according to various embodiments of the present invention.

Figure 13 graphic extension four levels with feedback implemented by parallel machine according to various embodiments of the present invention The example of level.

Figure 14 graphic extension four levels with feedback implemented by parallel machine according to various embodiments of the present invention Another example of level.

Figure 15 graphic extension finite state machine engine according to various embodiments of the present invention.

The example of the block of the finite state machine engine of Figure 16 graphic extension Figure 15 according to various embodiments of the present invention.

The example of the row of the block of Figure 17 graphic extension Figure 16 according to various embodiments of the present invention.

The example of two groups in the row of Figure 18 graphic extension Figure 10 according to various embodiments of the present invention.

Source code is converted into image for volume for compiler by Figure 19 graphic extension according to various embodiments of the present invention The example of the method for the finite state machine of journey Fig. 8.

The reality of Figure 20 graphic extension computer with framework based on von Karman according to various embodiments of the present invention Example.

Detailed description of the invention

Hereinafter describe and graphic abundant graphic extension specific embodiment is so that those skilled in the art can put into practice described Specific embodiment.Other embodiments may be incorporated into structure, logic, electricity, process and other change.Some embodiments each Part and feature can be included in those parts of other embodiments and feature or substitute other embodiments those parts and Feature.

Presents also describes level parallel machine (such as, level finite state machine (HFSM) engine) and related side among other things Method.Fig. 1 shows one this kind level parallel machine 10.Each level parallel machine 10 includes that two or more are parallel Machine, such as, two or more finite state machines (FSM) engine 12.Each finite state machine engine 12 is defeated Enter to receive in bus 16 data (such as, data stream) and described data made a response and provides (example according to received data As, produce) device that exports.

Each finite state machine engine 12 can be arbitrarily complicated.In an embodiment the most demonstrated in Figure 1, Finite state machine engine 12 is through cascade, wherein by the output (such as, state) of at least one in finite state machine engine 12 There is provided (such as, transmission) to the one in the finite state machine engine 12 in the downstream in cascade or one in whole or in part Above.In one example, the last finite state machine engine in described cascade produces result, can at output bus (such as, Result bus 20) the described result of upper offer.In one embodiment, each in finite state machine engine 12 can be such as Program via corresponding programming bus 14, such as, by using programming bus 14 that program (such as, image) is loaded (example As, storage) on finite state machine engine 12.

In certain embodiments, the time that minimizing processes required for data by HPRP10 can be important.By HPRP 10 times processing data can be at least in part by data (such as, the state transmitted between finite state machine engine 12 Information, such as state vector) quantitative limitation.In some these type of embodiments, finite state machine engine 12 is with hierarchical configuration Connect, and the interface between finite state machine engine 12 can be designed to near-real-time operation.Among other things, herein Part also describes these a little Considerations and a kind of thing for the parallel unit of level (such as, 12 groups of level FSM engine) of suggestion The conventional method of reason embodiment.

In an example embodiments, implement level pattern-recognition processor (HPRP) 30, as shown in FIG. 2. Pattern-recognition processor is for receiving data (such as, symbol sebolic addressing) and producing when picking out (such as, detecting) paid close attention to sequence The device of the output of the raw notice that a certain type is provided.In simple scenario, by single input symbol on input bus 36 Number stream provides to HPRP30.HPRP30 be programmed to via programming bus 34 detect a specific incoming symbol sequence or Some specific incoming symbol sequences.Produce and result (detected sequence) can be provided on result bus 40.In Fig. 2 Show the logic interfacing (DLL 34 and data input 36) of HPRP30.

In the embodiment shown, HPRP30 can include be programmed for pattern-recognition processor (PRP) 32 two or two Individual above finite state machine engine.Each PRP32 is for detecting respective stream of data (such as, input bus 36 or input Data stream in bus 42) in the device of symbol sebolic addressing.For example, each PRP32 can mate corresponding data Corresponding pattern in stream.In the illustrated embodiment, the 2nd PRP32 receive a PRP32 output ( There is provided on output bus 38) input as it and on result bus 40, produce result.In one embodiment, can be via Corresponding programming bus 34 programs each in PRP32.To 18, exemplary PRP32 is described below with reference to Figure 15 (also referred to " content inspection processor ").In some instances, finite state machine (FSM) engine or field-programmable are used The another embodiment of gate array (FPGA) or its version or parallel machine implements HPRP30.

Two rank (such as, the level) level of level parallel machine 10 and 30 allows two stand-alone programs based on same data stream Operation.Two rank level can be similar to the visual recognition being modeled as in the human brain of not same district.Under this model, described District is actually distinct pattern-recognition processor, and each pattern-recognition processor performs similar computing function (detection data stream In symbol sebolic addressing) but use distinct program (such as, signature).By being linked together by multiple parallel machines, pass can be obtained Deeper knowledge in data stream.

For example, the first level of described level (such as, is implemented by a FSM engine 12 or a PRP32 Level) directly original data stream can be performed process.It is to say, FSM12 or PRP32 can be respectively according to defeated Enter the original data stream on bus 16 or input bus 36 and produce output stream (such as, in original data stream Join or the instruction of some couplings).As demonstrated in Figure 1, the second level is (such as, by the 2nd FSM engine 12 or the second The level that PRP32 implements) process the output stream from described first level.For example, the 2nd FSM engine 12 Receive output stream (on output bus 18 provide) from a FSM engine 12 and the 2nd FSM engine 12 processes the The output stream of one FSM engine 12.Therefore, the 2nd FSM engine 12 does not receive original data stream as input, But receive output stream produced by a FSM engine 12.Available first Programming in Digital Image Processing the 2nd FSM engine 12 With the sequence in output stream produced by detection the oneth FSM engine 12.2nd FSM engine 12 can be coupled to list Solely DLL (such as, by programming bus 14) is for receiving the second image.

In one example, HPRP30 can be programmed to implement pattern discriminating function.For example, HPRP30 implement FSM can be configured to recognize one or more data sequence in the data stream being input to HPRP30 (such as, Signature).When paid close attention to sequence during a PRP32 picks out (such as, coupling) described data stream, can always export The output stream indicating described identification is provided on line 38.In one example, described pattern identification can be a string symbol of identification Number (such as, ascii character) identifies the Malware in network data or out of Memory with (such as).

This output stream (such as, output word, detection state etc.) can be fed from the output bus 38 of a PRP32 To the input bus 42 of another PRP32, as shown in FIG. 2.This offer connected in series of two PRP32 will be about The information of past event provides the means of the 2nd PRP32 with compressed word from a PRP32.This information provides reality On can be the summary of the complicated event (such as, data stream sequences) picked out by a PRP32.

As it has been described above, in certain embodiments, the time required for transmission between the level of PRP exports that reduces can attach most importance to Want.At some in this kind of embodiment, the interface between PRP32 may be designed to support each level of HPRP30 Real-time operation.For example, presents describes these a little Considerations and advises a kind of physical implementation for HPRP30 The conventional method of scheme.

Presents the most also describes for using hierarchical structure to process the method and apparatus of data.Described hierarchical structure Can comprise multiple level (such as, layer), each of which level processes data (such as, it being performed analysis) and provides output (example As, based on described analysis).Higher level can will be provided as input into from the output of the lower-level in described hierarchical structure Level.In this way, lower-level can perform relatively basic/fundamental analysis, and higher levels can use from one or one with The output of upper lower-level performs more complicated analysis.In one example, described hierarchical structure performs pattern identification.

In one example, by the multiple finite state machine engines being coupled in cascaded fashion to implement described level knot Structure.For example, the first finite state machine engine and the coupling of the second finite state machine engine serializable are so that described second Finite state machine engine receives output as input from described first finite state machine engine.Any number finite state machine Engine can be coupling in this hierarchical structure together.

In addition to using hierarchical structure to process data, presents also describes for using from a finite state machine engine The method and apparatus of another process performed by finite state machine engine is revised in output.Use finite state mentioned above Machine engine instance, feedback information can be provided enforcement relatively low by the second finite state machine engine of the process implementing higher levels First finite state machine engine of the process of level.Described feedback information can by described first finite state machine engine be used for It is similar to revise (such as, updating) in the mode of biological brain learning process.

Fig. 3 graphic extension may be used to implement the exemplary parallel machine 100 of limited state machine engine or pattern-recognition processor. Parallel machine 100 can receive input data and provide output based on described input data.Parallel machine 100 can include for connecing Receive the data-in port 110 of input data and for providing output to the output port 114 of another device.Data are defeated Inbound port 110 provides the interface for entering data into parallel machine 100.

Parallel machine 100 includes multiple programmable element, including universal component 102 and professional component 112.Universal component 102 One or more inputs 104 and one or more output 106 can be included.Universal component 102 can be programmed into In one in multiple states.The state of universal component 102 determines what universal component 102 will provide based on given input Plant output.It is to say, the state of universal component 102 determines how given input will be made a response (example by programmable element As, response).The data that can will enter into data-in port 110 provide multiple universal component 102 to cause universal element It is taken action by part 102.The example of universal component 102 can include (such as) state machine element as discussed in detail below (SME), enumerator and/or configurable logic block and other programmable element.In one example, SME can programmed (example As, set) with provide when receiving given input at data-in port 110 a certain output (such as, high signal or " 1 " signal).When receiving the input in addition to described given input at data-in port 110, described SME Different output (such as, low signal or " 0 " signal) can be provided.In one example, configurable logic block can be set to base Boolean logic function (such as, "AND", "or", " non-is performed in the input received at data-in port 110 Or " etc.).Discuss the example of enumerator the most after a while.Professional component 112 can include memorizer (such as, RAM), logic Door, enumerator, look-up table, field programmable gate array (FPGA) and other hardware element.Professional component 112 can be with logical Alternately and special function is performed with element 102.

Parallel machine 100 may also include the DLL 111 for program (such as, image) being loaded on parallel machine 100. The state of described image (such as, setting) able to programme universal component 102.It is to say, described image configurable general is first Part 102 is to make a response to given input in a certain manner.For example, universal component 102 can be set to work as High signal is exported when receiving character ' a ' at data-in port 110.In some instances, parallel machine 100 can make The timing of the operation of universal component 102 is controlled by clock signal.In certain embodiments, at data-in port 110 Place's received data can include the fixed data set received in time or simultaneously all together or the data stream received in time.Institute State data to receive or by described source from the arbitrary source (such as data base, sensor, network etc.) being coupled to parallel machine 100 Produce.

Parallel machine 100 also includes that multiple programmable switch 108 is for optionally by the different elements (example of parallel machine 100 As, universal component 102, data-in port 110, output port 114, DLL 111 and professional component 112) It is coupled.Therefore, parallel machine 100 is included in the programmable matrix formed in the middle of described element.In one example, Programmable switch 108 optionally by coupled to each other for two or more elements together so that universal component 102 Input 104, data-in port 110, DLL 111 or professional component 112 can pass through one or more Programmable switch 108 is coupled to the output 106 of universal component 102, output port 114, DLL 111 or special Element 112.Therefore, control signal route between described element can be carried out by setting programmable switch 108.Although A certain number conductor (such as, wire) between Fig. 3 graphic extension point element and programmable switch 108, but should manage Solve, other example can use different number conductor.Although additionally, each universal component of Fig. 3 graphic extension 102 It is individually coupled to programmable switch 108, but in other example, multiple universal components 102 can as a group (such as, Block 802 illustrated in Figure 15) it is coupled to programmable switch 108.In one example, data-in port 110, Data-out port 114 and/or DLL 111 can be embodied as depositor to the write of described depositor by data Respective element is provided to or provides data from described respective element.

In one example, a physical unit is implemented single parallel machine 100, but can be at single thing in other example Reason device (such as, phy chip) is upper implements two or more parallel machines 100.In one example, multiple parallel machines Each in 100 can include differing data input port 110, different output port 114, different DLL 111 and One group of different universal component 102.Additionally, its correspondence can be inputted at FPDP 110 by each group of universal component 102 Data make a response (such as, exporting high signal or low signal).For example, corresponding to the first of the first parallel machine 100 Group universal component 102 can be made a response to corresponding to the data at the first data-in port 110 of the first parallel machine 100. Second group of universal component 102 corresponding to the second parallel machine 100 can be defeated to the second data corresponding to the second parallel machine 100 Inbound port 110 is made a response.Therefore, each parallel machine 100 includes one group of universal component 102, and wherein different groups are general Difference input data can be made a response by element 102.Similarly, each parallel machine 100 and each corresponding group universal component 102 can provide different output.In some instances, the output port 114 from the first parallel machine 100 can be coupled to The input port 110 of two parallel machines 100, so that the input data for the second parallel machine 100 can include from first The output data of parallel machine 100.

In one example, for the image that is loaded on parallel machine 100 comprise the state for setting general-purpose element 102, Multiple information bits of the professional component 112 in programming programmable switch 108 and configuration parallel machine 100.In one example, Described image can be loaded on parallel machine 100 with programming parallel machine 100 to provide to export based on some input. The reaction of the data at input port 110 can be provided from parallel machine 100 by output port 114 based on universal component 102 Output.Output from output port 114 can include being indicated to the single position of the coupling of shaping type, comprising instruction with many The coupling of individual pattern and the word of unmatched multiple and corresponding to all or some universal component 102 and professional component 112 The output vector of state.

The exemplary purposes of parallel machine 100 include pattern identification (such as, speech recognition, image identification etc.), signal processing, Imaging, computer vision, Cryptographic and other.In some instances, parallel machine 100 can comprise finite state machine (FSM) Engine, field programmable gate array (FPGA) and version thereof.Additionally, parallel machine 100 can be larger device (such as, Computer, pager, cellular phone, personal digital assistant, portable audio player, network equipment (such as, route Device, fire wall, switch or its any combination), control circuit, camera etc.) in assembly.

Parallel machine (such as, FSM engine, PRP etc.) can implement state machine.State machine is represented by directed graph.Fig. 4 exhibition Showing simple state machine Figure 150, it represents the character string found in word ' DOG '.State 152 is state machine diagram The input state of 150.State 154 is intermediateness.In the diagram, end-state 156 (being sometimes also referred to the SOT state of termination) By the dashed boundaries identification around ' G ' state.In ordinary circumstance, when arriving end-state, referred to by a certain mechanism Show matching condition.This matching condition can be by the explicit signal from parallel machine 100 (such as, FSM engine 12, PRP32) Represent, or it may be encoded as binary word and is stored in memory register.

There is not the theoretical restriction of the size to state machine.In ordinary circumstance, PRP or FSM engine can be for described Each special symbol sequence that PRP or FSM engine can detect that implements independent state machine.If it is required, then can be right State machine performs to optimize to eliminate redundancy (shared path), in order to state machine is combined into bigger embodiment or minimizes The size of particular state machine embodiment.This optimizes a bit and can reduce state machine embodiment and therefore (such as) implement state machine The polymerization size of state machine engine.Once complete this to optimize, just can implement single big state machine.

Fig. 5 shows bigger state machine Figure 200.In ordinary circumstance, state machine embodiment can have forward direction complexity and connect And backward complicated connect both.In the example shown in Figure 5, an input state 202 feeds two intermediatenesses 204.At this in a little state machines, many end-state 208 and other intermediatenesses 204 many can be there is.

Each state in state machine has the transient condition that indicative of said status is the most movable.Only active state can be to input Symbol is made a response.In one embodiment, when receiving incoming symbol on input bus 36, described state machine In each active state by described for analysis symbol to determine whether to produce activation signal.This activation signal will be in order to activate NextState in sequence.For example, it is intended that the first state 204 of character ' b ' will be movable at primary nodal point 204 And it is connected to the first state upper activation of input character ' b ' by transformation 206 when receiving character ' b ' conduct input data Second state 204 of 204.

In Figure 200, first input state 202 can be activated and can be in input Data Matching from input node 202 Downstream condition 204 is activated when changing 206.When receiving input data, can activate in this way in whole Figure 200 State 204,208.Through activating end-state 208 mating corresponding to input data and paid close attention to sequence.Therefore, activate End-state 208 indicates and receives paid close attention to sequence at input data.In the finite state implementing pattern discriminating function Power traction is held up in the background of 100, and activation end-state 208 may indicate that and specific paid close attention to pattern detected the most on the input data.

In one example, each intermediateness 204 and end-state 208 may correspond in finite state machine engine 100 Universal component 102.Each transformation 206 may correspond to the connection between universal component 102.Therefore, it is converted in another Between state 204 or end-state 208 (such as, have and be connected to another intermediateness 204 or the transformation of end-state 208 206) intermediateness 204 is corresponding to can be coupled to the universal component 102 of another universal component 102.In some special feelings In condition, beginning state 202 can have corresponding universal component 102.

When finite state machine engine 100 is programmed to implement FSM, each in universal component 102 can be at living Move or in inactive state.Data stream at input interface 110 is not made a response by inertia universal component 102.Movable Data stream at input interface 110 can be made a response by universal component 102, and can mate universal component at input traffic 102 set timed activation downstream universal component 102.When universal component 102 is corresponding to end-state 208, universal element Part 102 can be coupled to the output port 114 instruction mated with offer with external device (ED), and described external device (ED) is in some feelings It condition can be another finite state machine engine 100.

The image configurable general element 102 that is loaded on finite state machine engine 100 via DLL 111 and general Connection between element 102, so that based on the response to the data stream at input interface 110 by activating downstream shape State implements wanted FSM.In one example, universal component 102 holding activity reach individual data circulation (such as, single Character, one group of character, single dock cycles) and unless reactivated by upstream universal component 102 and otherwise then switch to not Movable.

It is believed that end-state 208 stores compressed past event history.For example, end-state 208 institute is activated One or more input data sequences needed can be represented by the activation of described end-state 208.In one example, End-state 208 provided be output as binary, say, that described output indicates whether to mate corresponding being closed Note sequence.In FSM, end-state 208 can be fairly small to the ratio of intermediateness 204.In other words, although Described FSM can exist high complexity, but the output of the most described FSM can be little.

No matter FSM engine is to implement single combined (optimized) state machine or implement many independent state machines, all exists The concept of state vector.State vector is the individual state in the state machine implemented and the individual digital (example in vector Such as, position) there is between position the one-dimensional vector of correspondence one to one.It is to say, each state in state machine and state Numeral in vector is relevant.In the case of Fig. 4, state vector be 3 bit wides (one of them position instruction state 152, The state of each in 154 and 156).In the situation in figure 5, state vector is 74 bit wides.State machine can be Arbitrarily complicated and the most total size of machine is not applied any restriction.Therefore, state vector can endless.

But, in order to implement virtual condition machine in parallel machine, generally the size of state machine is applied a certain finite limitation. Do not polarize this limit and can characteristic based on the parallel machine in order to implement state machine and determine that this limits.

Fig. 6 shows another HFSM400.In the HFSM400 shown in figure 6, three finite state power tractions Information about its corresponding state is provided one by all or part of holding up 402 uses its corresponding state vectors all numeral Individual finite state machine engine 404.In the example shown, each state machine engine (402,404) is compiled accordingly via it Journey interface (PROG) is programmed.In other embodiments, from the data of each in FSM engine 402 in order to compile Journey FSM engine 404.At some in this kind of embodiment, FSM engine 404 is designed to according to from FSM engine 402 The status information received is adjusted.

Fig. 7 shows more complicated HFSM500.In the HFSM500 of Fig. 7, multiple FSM engine 502,504, 506,508 linking together, wherein status information is provided (such as, feeding) by FSM engine 502 by bus 510 To FSM engine 504, status information is fed to FSM engine 506, and FSM by bus 512 by FSM engine 504 Status information is fed to FSM engine 508 by bus 514 by engine 506.Multiple FSM levels 502 to 508 This connects each level enforcement different conditions machine allowing level.In some exemplary HFSM, each level of level Sensitive to different types of pattern.In these exemplary HFSM, as in HFSM500, this point of hierarchy level From allowing HFSM to implement low-level identification, described low-level identification is made to be transferred through each level of level higher to realize Level identification.In an example, the result bus 516 of HFSM500 provides result, such as, specific pattern The identification of (such as, phrase).In other example, described result is from FSM engine 502,504,506 and 508 In the combination of one or more of mode bit.

As shown in fig. 7, a kind of for connecting the method for indivedual FSM engines with hierarchical fashion for being drawn by a FSM The input of next higher levels FSM engine that the output held up is connected in level.Should be understood that and can implement HFSM500, Wherein provide (such as, feedover or feed back) to other level arbitrary in level the status information from a level.Lift For example, the status information from FSM engine 502 can be sent to FSM engine 506, and can will draw from FSM Hold up the status information feedback of 508 to FSM engine 502.In general, during no matter, which kind of is considered required configuration, Status information from one or more FSM engines all can be provided the one in other FSM engine or one Above (such as, whole).

Example demonstrated in Figure 7 is corresponding to the visual identity of written language.Along with processing the higher levels proceeding to level, The knowledge of the accumulation of data stream is increased accordingly.In the embodiment shown, the FSM engine (FSM at each level Engine 502,504,506 and 508) through cascading with implementation level identification capability.The each continuous level of level can be implemented should New regulation (pattern signature) for the output of previous level.In this way, can be based on to the most basic cell information Detect and identify highly detailed object.

For example, the initial data inlet flow to level 1 (such as, a FSM engine 502) can comprise the picture of image Prime information (such as, no matter be black/white or ON/OFF to location).FSM engine 502 can be programmed to identification (example As, identify) the primitive pattern that formed of institute's rheme.In an example, FSM engine 502 is configured to identify neighbouring When the group of position forms vertical line, horizontal line, arc etc..Each in these patterns can be by from FSM engine 502 Independent carry-out bit (or signal) identify.For example, when FSM engine 502 picks out the vertical line of at least 3 positions, On the first of output word, high signal (such as, logic 1) can be sent to FSM engine 504.When FSM engine 502 When identifying the horizontal line of at least 3 positions, on the second of output word, high signal can be sent to FSM engine 504.

FSM engine 504 can be programmed to identify the pattern formed by the output 510 from FSM engine 502 simultaneously. For example, FSM engine 504 can be programmed to identify the primitive pattern (line, arc etc.) that FSM engine 502 is identified The pattern that formed of combination.For example, FSM engine 504 can be programmed to identify when horizontal line is handed over vertical line Pitch thus form letter " t ".As mentioned above, use the HFSM500 that implemented of FSM engine 504 to from The output of FSM engine 502 is made a response.Therefore, by identifying from the pattern in the carry-out bit of FSM engine 502 Carry out the combination of Recognition unit pattern.

Then the output 512 from FSM engine 504 being input in FSM engine 506, FSM engine 506 can be from The combination identification word of the letter that FSM engine 504 is identified.Then the recognizable FSM of the 4th level (FSM engine 508) draws Hold up the phrase that 506 words identified are formed.Therefore, higher levels can be programmed to identify the type in lower-level output Formula.It addition, lower-level can be programmed to identify is formed in the pattern (feeding back to lower-level) identified in higher levels Component.

Visual identity to letter is used as example.But, hierarchical method as herein described and system can be applicable to other data. For example, to the Gradation processing of the data corresponding to sound can phoneme at level 1 combination identification syllable and from layer The combination identification word of the syllable at level 2.In other example, Gradation processing can be applicable to hierarchical fashion structure with oneself The machine data built.

When implementing HPRP or HFSM (such as, HFSM500), the problem being likely encountered is that input data are with defeated Go out the asymmetrical relationship between data.When the state machine just implemented becomes sufficiently large, this unsymmetry is aggravated.For institute For each incoming symbol processed, the state vector of FSM engine may be in response to described incoming symbol and changes.At one In embodiment, each FSM includes 16 power (64K) the individual state of (such as) up to 2.If each state state to Amount has corresponding numeral, then state vector will be for 64K bit length.It is likely difficult between FSM engine transmit institute State the vector of length.This being described below reducing between the size of input data and the size of output data is the most right The method claimed.

In one embodiment, bus sends between FSM engine data.The bus of N-bit wide can be at 64Kb/N Individual circulation is transmitted 64Kb state vector.In other embodiments, described state vector compressed so that in vector only The digital communication changed in response to incoming symbol is to other FSM engine.For example, each bus cycle may bag Include the position of the numeral changed in the circulation of the previously symbol in state vector.In this case, described output can be referred to as Difference vector.

In another embodiment, each FSM engine is designed only to the digital subset from state vector is sent to it Its FSM engine.In this kind of embodiment, each FSM engine is programmed so that being delivered to other FSM draws The status information that only has held up is the status information of end-state.In ordinary circumstance, the number of end-state is less than state Total number.For example, in PRP32, the ratio of total state is depended on the state implemented in PRP by end-state Machine.For example, ratio can be high (1: 5) or at a fairly low (1: 10,000).

End-state is in the practical examples that the ratio of total state is 1: 10 and state vector is 64Kb wherein, and this implies Output vector will be for 64Kb/10 or 6,554 positions.In this example, each input circulation (8 bit signs) of PRP The corresponding output vector of 6,554 positions will be produced.

For ensuing example, the example that wherein ascii character-set will be used to be input (symbol) language.At this In situation, each incoming symbol is represented by 8 binary words.In alternative embodiments, other symbol can be used, such as, Each of which incoming symbol is N position binary word.

For example, in one embodiment, it is sent in HPRP30 (such as, HPRP30 depicted in figure 2) The output vector of the second level PRP32 can only represent the end-state of the first level PRP32.In another example, In HFSM500 (such as, HFSM500 depicted in figure 7), FSM engine 504 can produce expression, and it is final Described output vector is also sent to FSM engine 506 on output bus 514 by the output vector of state.At this kind In example, output bus 514 is 8 bit wide buses.Use from 8: 6 cited in previous case, 554 ratios, it is provided that (example As, transmitting) number of circulation required for 6,554 positions of output vector will be 6,554/8 or 820 circulations.The most just Being to say, each continuous level of level processes the output word from previous level by needing 820 input circulations.This effect Described level should be passed linearly, so that needs 820 input circulation is resolved by each continuous state with ripple form It inputs word.In this case, under to fixed-ratio, the six level levels of PRP will need 4,100 (5 × 820) individual input Circulate to allow incoming symbol with ripple form through until producing result at highest level.These numbers are used only as Example.If the ratio of total state is increased by end-state, then the ripple time will increase.Equally, if the layer of level The number of level increases, then the ripple time will increase linearly along with each continuous level.

Based on example used above, for HFSM or HPRP produces result, the delay (phase of several orders of magnitude For input circulation) it is possible.The delay of this type can be unacceptable in application in real time.As it has been described above, can lead to Cross (such as) and increase the size of bus to reduce the number of the circulation required for transferring status data.Also can reduce bus cycle Time is to reduce the time required for transferring status data.Additionally, as it has been described above, can send only identify state vector by The difference vector of the numeral changed in last symbol.It is used as other lossless compress mechanism.

Next discuss in order to reduce this other method postponed, such as, implement 1: 1 relation between input and output.

A kind of mode in order to obtain 1: 1 relation between input and output in HFSM (such as, HFSM500) is to make Input bus 518 is upper equal in size (width) with output bus 510.The width of output bus 510 can be by HFSM500 Self determine.For example, the big I of output bus 510 is true by the number of the end-state in state machine engine 502 Fixed.In general, FSM engine is programmed to identification many different types simultaneously.Each in these patterns can be implemented For individual state machine.In this way, FSM engine can implement a group state machine, its whole parallel runnings.

Fig. 8 is the reality of the group 530 of the state machine 532 of whole parallel runnings in schematically showing single FSM engine Example.In fig. 8,8 state machines 532 are shown.It practice, FSM engine is embodied as thousand up to ten thousand indivedual state machines.

Step 1: the polymerization (end-state) of state machine output

As demonstrated in Figure 9, each indivedual state machines 532 can have one or more end-state 208.Although Several end-state 208 can be there is, but any one in the end-state of particular state machine 532 has identical or relevant containing Justice.In other words, if arrive in the end-state 208 of state machine 532 any one, then think described state machine There is coupling.It practice, this means (such as) to would correspond to single state machine 532 by use OR-gate 540 The output of the programmable element of end-state 208 is coupled and is polymerized described in (such as, inclusive-OR operation is together) Whole state is to provide single output 542 as show in Figure 9.In the example shown in fig .9, state machine 532 By the inclusive-OR operation of three end-state 208 together.As can be appreciated, other logic can be used to be polymerized end-state 208.

In an example, the end-state 208 of the most each state machine 532 is the most aggregated (such as, through inclusive-OR operation), Result being just grouped (such as, collect) and becomes the logical group of N number of state machine 532, wherein N is equal to corresponding incoming symbol language The number of the numeral called the turn.Wherein the incoming symbol language pack of the first level containing 8 input words examples in, 8 each and every one Other state machine output 542 can be aggregated to provide the one providing next level arriving level in incoming symbol 546.? In Fig. 7, for example, only the first level of level receives the incoming symbol relevant to standard language (ASCII or other). The most in the illustration being described, FSM engine 502 can produce offer to 8 of FSM engine 504 on output bus 510 Output vector.The follow-up level of level receives the incoming symbol with the implication determined by previous level.

Once state machine the most grouped (such as, several groups of 8 one group), normalization input and the first of output vector Level completes the most.Use the number from the example used in the present invention, 820 can be represented with 103 8 words Individual end-state.The situation of the end-state of each 8 the indivedual state machines 532 of coding in these 8 words.Remember The total number of end-state coded in these 8 output vectors can be substantially larger than 8.This is because to same state machine 532 In the inclusive-OR operation function performed by end-state 208 can by more than 8 state inclusive-OR operations together.

In one embodiment, each FSM engine includes the input port of N-bit wide and the output port of N-bit wide.? In one embodiment, by N BITBUS network by from each level status information (such as, with the form of output vector, Such as, all or part of of state vector, or difference vector) it is distributed to next FSM engine.For example, FSM draws Hold up 502 use N position output bus 510 and status information is distributed to FSM engine 504.In one embodiment, will Same N position output vector provides (such as, distribution) to each state machine in FSM engine 504.In another embodiment, Programmable element in FSM engine 504 is grouped into some groups (such as, block) and the outfan of FSM engine 502 N position word sequence is written to FSM engine 504 and word sequence is distributed in predefined mode (such as, in order) by mouth State machine member block in FSM engine 504.The method allows to be distributed to additional status information FSM engine 504, But need additional bus circulation to transmit complete status information.

In one embodiment, the status information of a programmable element group is to include another FSM engine by transmission The address information of instruction and described FSM engine in the address of programmable element group and be sent to described FSM engine In described group.Described information can be distributed in bus 510 in (such as) Fig. 7.

The expansion of the number of the input bus in step 2:PRP

One embodiment of FSM12 or PRP32 has all shapes being broadcast to incoming symbol be implemented in PRP The single stream input of state machine 532.But, the definition of expansible FSM12 and PRP32 is to implement more than one stream input (respectively 16 and 36).In previously cited example, the total number of individual flow input will be equal to 103.For example, In order to intactly implement, HPRP is then by needs 103 8 input or the input of 820 positions being used for each PRP32 Bus.

In one embodiment, programmable element (such as, state machine element (SME)) array 560 is implemented FSM12 And PRP32.In an example, each SME is in homogeneity two-dimensional array 560.This array 560 can be subdivided into Some indivedual districts, each of which district has dedicated stream input (respectively 16 and 36) of their own.Figure 11 shows SME This two-dimensional array 560 of element.For example, Figure 11 is subdivided into the array 560 of SME group 562, the most often One SME group 562 may correspond to the block 802 in finite state machine engine 800.Whole array 560 can include (example As) 16 × 16 SME groups (256 groups altogether), each of which group 562 includes 128 containing two SME's (such as, each of which group 562 includes 16 GOT row, such as, illustrated in Figure 16 in group (GOT) Row 806).

In certain embodiments, each GOT row contains 8 GOT, extra programmable element (such as, the cloth of one (some) That logic or enumerator) and output bus 18,38 can be provided by two outputs.If crossing over FSM12 and PRP32 Use all available output, then this array can have (such as) up to 8192 positions to be driven into next level PRP32.

When constructing HFSM500 the most demonstrated in Figure 7, can be by two different semiconductor devices (such as, FSM Engine 502 and 504) in two-dimentional SME group 562 array link together.Exist and two semiconductor devices are connected Various means together.For example, when I/O counting becomes sufficiently high, cross tie part between available nude film.One In individual exemplary embodiment, as Figure 12 shows, every in 256 SME groups 562 in HPRP570 One can have 8 interfaces (such as, input bus 36,42) on the bottom of nude film and 8 on the top of described nude film Position interface (such as, output bus 38,40).When these interfaces are placed in predefined position, a PRP level (PRP1) On 582 tops that can directly be stacked in lower-level PRP (PRP0) 580, wherein input and output interface are directed at naturally And use the cross tie part (such as, silicon through hole) of such as cross tie part 574 to link together.

This alignment is effectively formed SME row (by input path 572, outgoing route 578 and cross tie part 574 and 576 Define) concept, each level of wherein said row represents the SME group being contained on same nude film.It is continuing with previously The exemplary number discussed, in each PRP level (580,582 and 584), SME group 562 can be by previously Up to 8 state machines implemented in level drive.8 state machines from previous level can be arbitrarily complicated, directly The restriction applied to SME group 562.Figure 12 shows the example (edge view) of three levels HPRP, wherein highlights One in display SME row.In each level, the packet of SME is by the status information from described level (such as, 8 encoded words) next higher levels is provided to.

Generally speaking, when configured in this manner, HPRP can follow with each level only one input clock of PRP level The delay of ring provides substantially instantaneous result.Because of input and the unsymmetry of output word, the problem that causes is addressed and whole Individual level can be with stream input 572 simultaneously operatings.

In certain embodiments, the status information from a FSM engine 12 is sent to more than one other FSM Engine 12.Fig. 6 shows this embodiment.With reference to illustrated HPRP570 in Figure 12, this embodiment is described, For example, the status information from PRP580 can be sent to PRP584.In this kind of embodiment, interconnection Part 576 and 574 forms the bus of any one status information being transferred in the block in row.For example, cross tie part 574 And 576 can comprise one or more reach through hole cross tie parts, and may be provided in every string and pass for by status information It is delivered to non-adjacent PRP.In this kind of embodiment, each PRP in stacking is connected to described reach through hole and from described Reach through hole receives information.In another embodiment, as required the input of PRP is optionally connected during manufacture process Receive reach through hole.

In other embodiments, the status information from a SME group is distributed to the contiguous block in same PRP32, And it is distributed to other PRP32 (such as, in same arranges) by those blocks.

In one embodiment, from the status information of one or more PRP32 or derive from described status information Information in order to other PRP32 in reprogramming level.The example of Figure 13 graphic extension four level level, it uses Feedback carrys out the part of level described in reprogramming.In general, can be based on from higher or lower level finite state power traction Hold up output or output based on their own and reprogramming gives PRP32 (such as, the first finite state machine engine 602). Therefore, the first finite state machine engine 602 can change to adjust according to the condition changed during runtime.? In one example, feedback is available for lower-level and carries out learning (being reprogrammed) based on higher levels.Use finite state power traction Holding up 602 as an example, feedback can receive at DLL 602B and can new in for finite state machine engine 602 Or the form of updated program.In one example, the described updated some or all of finite state of program Reprogrammable Power traction holds up 602.

Four level levels 600 in Figure 13 are implemented by four finite state machine engines 602,604,606,608, Each parallel machine have data-in port 602A, 604A, 606A, 608A, DLL 602B, 604B, 606B, 608B and output port 602C, 604C, 606C, 608C.Level 600 implemented by first finite state machine engine 602 The first level and provide output to implement the second finite state machine engine 604 of the second level of level 600.3rd Finite state machine engine 606 and the 4th finite state machine engine 608 implement the third layer level of level 600 and the 4th layer equally Level.In one example, based on level 600 to the analysis of the input data that the first finite state machine engine 602 is received The output as level 600 that exports from the 4th finite state machine engine 608 is sent to external device (ED).Therefore, come Export corresponding to the set of level 600 from the output of the 4th finite state machine engine 608.In other example, have by oneself The output of other person 602,604 or 606 in limit state machine engine may correspond to the set output of level 600.

Can be by from the second finite state machine engine the 604, the 3rd finite state machine engine 606 and the 4th finite state power traction Hold up the output of 608 each feed back to finite state machine engine 602,604,606 at following level DLL 602B, 604B、606B.For example, the 3rd finite state machine will be fed back to from the output of the 4th finite state machine engine 608 In the DLL 606B of engine 606.Therefore can based on the output from the 4th finite state machine engine 608 again Program the 3rd finite state machine engine 606.Therefore, the 3rd finite state machine engine 608 can be revised during runtime Its program.Can be based respectively on from the second finite state machine engine 604 and the output of the 3rd finite state machine engine 606 Reprogramming the first finite state machine engine 602 and the second finite state machine engine 604 the most similarly.

In one example, the feedback from the output from finite state machine engine 604,606,608 is treated (such as, Analyze and compiling) to form the program for reprogramming finite state machine engine 602,604,606.For example, come Can be analyzed also by processing means 614 before being sent to DLL 606B from the output of limited state machine engine 608 Compiling.Processing means 614 can produce for finite state machine engine based on the output from finite state machine engine 608 The updated program of 606.Processing means 614 can be analyzed described output and compile for the 3rd finite state machine engine 606 Updated program.Then by DLL 606B, described updated program can be loaded into the 3rd finite state power traction Hold up on 606 with reprogramming the 3rd finite state machine engine 606.In one example, described updated program can contain only Change from the part of present procedure.Therefore, in one example, updated program only replace finite state machine engine 602, 604, a part for the present procedure on 606,608.In another example, it is updated over program and replaces the complete of present procedure Portion or most.Equally, processing means 610,612 can be based on from the second finite state machine engine 604 and the 3rd The output of finite state machine engine 606 and analyze in a similar manner and compile feedback.Can be extra by one or more Finite state machine engine is implemented or can come by different types of machine (such as, having the computer of von Karman framework) Implement processing means 610,612,614.

In some instances, processing means 610,612,614 was analyzed from higher levels before the program that compiling is new Output.In one example, processing means 610,612,614 analyzes described output to determine how renewal lower-level journey Sequence and be next based on described analysis and compile new or updated lower-level program.Although it is given limited in level 600 Feedback at state machine engine is from directly receiving in described given finite state machine engine above layer level, but feedback can Another finite state machine engine at arbitrary level finite state machine engine to higher, relatively low or same level.Citing comes Saying, feedback can be in the programming input of finite state machine engine from the output of described same finite state machine engine or from phase Together, the output of another finite state machine engine at higher or lower level receives.It addition, finite state machine engine can be from Multiple different finite state machine engines receive feedback.Based on feedback to the reprogramming of finite state machine engine can with to input Pattern identification in data disconnect in time (such as, not along with initial data process in real time).

The information that the most back sends along level is to make lower-level exist to affect the purpose of the reprogramming of lower-level Can become more efficient when distinguishing paid close attention to pattern.In some instances, it is understood that transmit information to the higher levels of level The cost time, therefore when possible, avoid will send information to the process of higher levels.In some instances, higher levels Can be substantially in order to resolve for system the identification for new pattern.This can be similar to the new skin of brain in biological brain The used process occurred in matter.In one example, if a pattern can be resolved at lower-level completely, then answer this Sample does.Feedback mechanism for being sent to a kind of method of the lower-level of level by " study ".Information is pushed back downwards along level The upper level of this process help retaining hierarchical for processing new or unfamiliar pattern.Additionally, can be by subtracting The little data transfer through each level of level accelerates whole identification process.

Feedback can make the lower-level data stream sensitivity more observantly to input of level.This " pushes down on " information Result is can to make a policy at the lower-level of level and described decision-making can complete the soonest.Therefore, in one example, Output from lower-level finite state machine engine (such as, the first finite state machine engine 602) may correspond to from level 600 exported together with the output from the 4th finite state machine engine 608 to gathering of another device.External device (ED) can (such as) Monitor from the output of each in these finite state machine engines 602,608 to determine that level 600 identifies the most Go out pattern.

In one example, feedback information can include the identification information of the data stream corresponding to being analyzed.For example, described Identification information can include that the evident characteristics of data, the form of data, the agreement of data and/or arbitrary other type of identification are believed Breath.Described identification information can be collected by (such as) processing means 610, analyze and for adjusting the analysis for inputting data Method.Then limited state machine engine can be programmed by adapted analysis method.Identification information can include that (such as) inputs The language of data.Finite state machine engine can first be programmed to determine the language of input data and the most identified corresponding to Described finite state machine engine just can be adjusted (such as, reprogramming) by the language of input during runtime.With Adapted analysis method in finite state machine engine can be more specifically corresponding to the analysis method for identified language.? After, finite state machine engine can use adapted analysis method to analyze the input data in future.Feedback procedure can repeatedly with Make extra identification information can be found in input data to allow to adjust analysis method further.

Program (also referred to herein as " image ") for being loaded on finite state machine engine can be by below with respect to Figure 19 institute The compiler discussed produces.In general, compiling can be the process of computation-intensive, thereby increases and it is possible at compiling pattern label for the first time Name large database concept time the most obvious.At runtime operation in, the finite state machine engine of higher levels can for The form of the incremental program updates of lower-level finite state machine engine provides feedback to lower-level.Therefore, to relatively low The feedback information of level finite state machine engine can be that the compiling to original program is got up the much smaller of less computation-intensive Incremental update.

The four level levels that Figure 14 graphic extension is implemented by four finite state machine engines 702,704,706,708 Another example of 700.Herein, the second finite state machine engine the 704, the 3rd finite state machine engine 706 and the 4th layer Level finite state machine engine 708 receives input data from output and the original data stream of lower-level.Therefore, level 2, 3 and 4 can be from the combination identification pattern from lower-level Yu the pattern of initial data.

As from Figure 13 and 14, finite state machine engine almost either type can cascade, wherein can will arrive level Initial data input and the output from finite state machine engine are sent to other finite state machine engine arbitrary, including it Self.Additionally, can as input data and/or will be send as feedback to another from the output of given finite state machine engine One finite state machine engine is for updating the program for finite state machine engine.

It is as noted previously, as the time that finite state machine engine processes a position (or word) of input traffic, serial region It is associated with limit state machine engine and can increase the time being processed described input traffic by all finite state machine engines completely.Layer Secondary lowest hierarchical level generally will receive the input of minimum (the trickleest) level.Therefore, it is contemplated that lower-level compares high-level Output more active.The higher levels object it is to say, each continuous level in level can collect.In one example, Finite state machine engine has restriction how fast can be fed to the maximum input rate of finite state machine engine by input data. This input rate can be considered as individual data circulation.On each continuous data circulates, finite state machine engine has activation The probability of many end-state.It is notable that this can cause finite state machine engine (especially at the lowest hierarchical level of level) to produce Output (coupling) data of amount.For example, if providing lowest hierarchical level finite state power traction using input as byte stream Hold up, then on arbitrary data-oriented circulates, finite state machine engine can produce the status information of multiple byte.If one The information of individual byte can produce the status information of multiple byte, then the whole level of finite state machine engine should synchronize so that The information of obtaining is communicated up along level.But, feed back without synchronizing, at lower-level, more quickly receive feedback, described relatively Low-level just can more quickly be adjusted and analyze the most efficient.

As an example, the largest amount output of each level of level (implementing by single finite state machine engine) can wait The degree of depth in 1024 bytes and level can be equal to 4 levels.Input traffic data for finite state machine engine Speed can be equal to the 128MB/ second.Under these conditions, each level of level can be crossed in 7.63 microseconds.At four layers In the case of level level, total stabilization time of the whole stacking of finite state machine engine is by for 4 times or 30.5 of 7.63 microseconds Microsecond.In the case of the stabilization time of 30.5 microseconds, hint input data frequency should be limited to 32KB/s.

It is interesting to note that this depends highly on the configuration of finite state machine engine.Finite state machine engine can be configurable So that state machine size is traded off by input data rate.If it addition, generation is loaded on finite state machine engine The compiler of individual images make corresponding amendment, then be adjustable to the input word size of described finite state machine engine.

In one example, can on the machine with von Karman framework with software implement referring to figs. 1 to The method of one or more FSM described in 14.Therefore, software instruction can cause processor real to original data stream Execute the first analytic hierarchy process FSM.Output from described first level FSM then can be by described processor according to the second layer Level FSM process, etc..Additionally, feedback cycle discussed herein above can be by analyzing the level from described FSM Export and use described output to produce the processor enforcement of the one or more of new FSM in described level.

The example of Figure 15 to 18 graphic extension herein referred to as parallel machine of " FSM engine 800 ".In one example, FSM engine 800 comprises the hardware embodiments of finite state machine.Therefore, FSM engine 800 is implemented corresponding to FSM In the hardware element (such as, programmable element) of multiple alternative coupling of multiple states.The shape being similar in FSM State, hardware element can be analyzed inlet flow and activate downstream hardware element based on described inlet flow.

FSM engine 800 includes multiple programmable element, including universal component and professional component.Described universal component can be through Program to implement many difference in functionalitys.These universal components include with the hierarchical fashion tissue (institute in Figure 16 and 17 that embarks on journey 806 Show) and the SME804 of block 802 (being shown in Figure 15 and 16), 805 (being shown in Figure 18).In order to level SME804 that mode is organized, route signal between 805, use the level of programmable switch, and it includes switching between block 803 (the institute in Figure 17 that switchs 812 in (being shown in Figure 15 and 16), block in 808 (being shown in Fig. 9 and 10) of switch and row Show).SME804,805 states that may correspond to the FSM that FSM engine 800 is implemented.Can be by using hereafter Described programmable switch by SME804,805 be coupled.Therefore, can be by by SME804,805 programmings For corresponding to the function of state and by optionally by SME804,805 be coupled with corresponding to the shape in FSM Transformation between state and on FSM engine 800, implement FSM.

The general view of Figure 15 graphic extension exemplary FSM engine 800.FSM engine 800 include optionally with 803 multiple pieces 802 be coupled are switched between programmable block.It addition, block 802 can be selectively coupled to input block 809 (such as, data-in ports) are for receiving signal (such as, data) and providing data to block 802.Block 802 Can be also selectively coupled to IOB 813 (such as, output port) provides outside to fill for by signal from block 802 Put (such as, another FSM engine 800).FSM engine 800 may also include DLL 811 with by program (such as, Image) it is loaded on FSM engine 800.Described image (such as, setting) able to programme SME804, the state of 805.Also That is, described image can by SME804,805 be configured in a certain manner the given input at input block 809 be done Go out reaction.For example, SME804 can be set to when receiving character ' a ' at input block 809 export high signal.

In one example, input block 809, IOB 813 and/or DLL 811 can be embodied as depositor so that Write to described depositor provides data to respective element or provides data from described respective element.Therefore, can be in the future SME804 is loaded on, on 805 from the position of the image being stored in the depositor corresponding to DLL 811.Although figure A certain number the conductor (example between 803 is switched between 15 graphic extension blocks 802, input block 809, IOB 813 and block As, wire, trace), it should be understood that less or more conductor can be used in other example.

The example of Figure 16 graphic extension block 802.Block 802 can include optionally switching 808 couplings with in programmable block The multiple row 806 being combined.It addition, row 806 can be selectively coupled to another block 802 by switching 803 between block Another interior row 806.In one example, including buffer 801 to control the signal of switch 803 to/from between block Timing.Row 806 include being organized into element to multiple SME804 of (referred herein as two groups (GOT) 810), 805. In one example, block 802 comprises ten six (16) individual row 806.

The example of Figure 17 graphic extension row 806.GOT810 optionally can be coupled by switch 812 in row able to programme Other GOT810 in row 806 and other element 824 any.GOT810 also can be by switching 808 couplings in block Other GOT810 in other row 806, or by switching 803 other GOT being coupled in other block 802 between block 810.In one example, GOT810 has the first input 814 and the second input 816 and output 818.First input The 2nd SME805 of GOT810 is coupled in 814 SME804 being coupled to GOT810 and the second input 816.

In one example, row 806 includes more than first row interconnecting conductor 820 and more than second row interconnecting conductor 822.? In one example, the input 814,816 of GOT810 can be coupled to one or more row interconnecting conductors 820,822, And output 818 can be coupled to a row interconnecting conductor 820,822.In one example, more than first row interconnecting conductor 820 Can be coupled to each SME804 of each GOT810 in row 806.More than second row interconnecting conductor 822 can be coupled to One SME804 of each GOT810 in row 806, but not can be coupled to another SME805 of GOT804. In one example, the first the half of more than second row interconnecting conductor 822 can be coupled to the first half of the SME804 in row 806 The second the half of (from a SME804 of each GOT810) and more than second row interconnecting conductor 822 can be coupled to row The second half (from another SME804 of each GOT810) of the SME805 in 806.More than second row interconnecting conductor Limited connectivity between 822 and SME804,805 is herein referred to as " odd even ".In one example, row 806 May also include professional component 824, such as enumerator, boolean logic element able to programme, field programmable gate array (FPGA), Special IC (ASIC), programmable processor (such as, microprocessor) and other element.

In one example, professional component 824 includes enumerator (being also referred to as enumerator 824 in this article).In one example, Enumerator 824 comprises 12 reciprocal counters able to programme.12 programmable counters 824 have counting input, reset Input and zero count output.Counting input makes the value of enumerator 824 successively decrease 1 when being asserted.The input that resets is being asserted Time cause enumerator 824 from associated register load initial value.For 12 digit counters 824, can load many Reach the numerical value of 12 as described initial value.When the value of enumerator 824 is decremented to zero (0), assert that zero count exports. Enumerator 824 also has an at least two pattern: pulse and holding.When enumerator 824 is set as pulse mode, During dock cycles, assert when enumerator 824 is decremented to zero that zero count exports, and no longer assert at following clock cycle Zero count exports.When enumerator 824 is set as holding pattern, when enumerator 824 is decremented to zero in dock cycles Period asserts that zero count exports, and keeps asserting that the output of described zero count is until enumerator 824 is by the reset input just asserted Till reset.In one example, professional component 824 includes Boolean logic.In some instances, this Boolean logic can be used Information is extracted with SOT state of termination SME from FSM engine 800.The information extracted may be used to status information transmission To other FSM engine 800 and/or transmit in order to reprogramming FSM engine 800 or another FSM engine of reprogramming The programming information of 800.

The example of Figure 18 graphic extension GOT810.GOT810 include having input 814,816 and make it export 826, 828 are coupled to the OR-gate 830 and 3 SME804 and the 2nd SME805 to 1 multiplexer 842.3 Can be set to 1 multiplexer 842 output 818 of GOT810 is coupled to a SME804, the 2nd SME 805 or OR-gate 830.OR-gate 830 may be used to be coupled to form GOT by both output 826,828 The shared output 818 of 810.In one example, as discussed above, a SME804 and the 2nd SME805 represents Go out odd even, wherein the input 814 of a SME804 can be coupled to some the row interconnecting conductors in row interconnecting conductor 822 and The input 816 of the 2nd SME805 can be coupled to other row interconnecting conductor 822.In one example, configuration switch can be passed through Any one or both in 840 and make two SME804,805 cascades in GOT810 and/or be circulated back to himself. Can be by the output 826,828 of SME804,805 being coupled to other SME804, the input 814,816 of 805 And make SME804,805 cascades.Can make by the input 814,816 of their own is coupled in output 826,828 SME804,805 it is circulated back to himself.Therefore, the output 826 of a SME804 can be not coupled to a SME In the input 816 of the input 814 and the 2nd SME805 of 804 any one, be coupled to one therein or be coupled to it In both.

In one example, state machine element 804,805 comprises the Parallel coupled multiple memory cells to detection line 834 832, such as be commonly used for those memory cells in dynamic random access memory (DRAM).One this kind of memorizer Unit 832 comprises and may be set to a data mode (such as corresponding to high level or the data mode of low value (such as, 1 or 0)) Memory cell.The output of memory cell 832 be coupled to detect line 834 and to memory cell 832 input based on Data in data flow line 836 and receive signal.In one example, the input in data flow line 836 is decoded to select One in memory cell 832.The data mode that it is stored by word-select memory unit 832 arrives as output offer On detection line 834.For example, decoder can be provided (not open up received data at data-in port 809 Show) and described decoder selecting data streamline 836 in one.In one example, described decoder can be by ACSII Character is converted into 1 in 256 positions.

Therefore, the data being set as in high level and data flow line 836 when memory cell 832 correspond to memory cell 832 Time, high signal is exported detection line 834 by memory cell 832.When the data in data flow line 836 are corresponding to storage When device unit 832 and memory cell 832 are set as low value, low signal is exported detection line 834 by memory cell 832. On detection line 834, the output from memory cell 832 is sensed by testing circuit 838.In one example, input line 814, Corresponding testing circuit 838 is set as active or inactive state by the signal on 816.When being set as inactive state, Signal on the most corresponding detection line 834 how, and testing circuit 838 all exports low letter in corresponding output 826,828 Number.When being set as active state, testing circuit 838 from corresponding SME804,805 memory cell 834 in One on corresponding output lead 826,828, export high signal when high signal being detected.When being active middle, Testing circuit 838 when being low from the signal of corresponding SME804, all memory cells 834 of 805 the most defeated Low signal is exported in outlet 826,828.

In one example, SME804,805 include 256 memory cells 832 and each memory cell 832 coupling Close different pieces of information streamline 836.Therefore, SME804, the 805 selected one can being programmed in data flow line 836 Or one or more of export high signal time there is high signal thereon.For example, SME804 can be by first memory unit 832 (such as, positions 0) are set as height and are set as low by other memory cells 832 (such as, position 1 to 255) all. When corresponding testing circuit 838 is active middle, SME804 is in the data flow line 836 corresponding to position 0 thereon In output 826, high signal is exported when there is high signal.In other example, SME804 can be set to by fitting Output when one in multiple data flow line 836 has high signal thereon when memory cell 832 is set as high level High signal.

In one example, by reading position from associated register, memory cell 832 can be set as high level or low value. Therefore, can store in depositor by the image that compiler is created and the position in described depositor is loaded into relevant Connection memory cell 832 programs SME804.In one example, the image that described compiler is created include high with The binary picture of low (such as, 1 and 0) position.Described image FSM able to programme engine 800 with by cascade SME804, 805 and as FSM operate.For example, can be by testing circuit 838 being set as active state and by a SME 804 are set as active state.Oneth SME804 can be set to be had thereon in the data flow line 836 corresponding to position 0 High signal is exported when having high signal.2nd SME805 initially may be set to inactive state, but can be set in activity Time export high signal when the data flow line 836 corresponding to position 1 has high signal thereon.Can be by setting a SME The output 826 of 804 cascades a SME804 and the 2nd SME805 with the input 816 being coupled to the 2nd SME805. Therefore, when, when corresponding to sensing high signal in the data flow line 836 of position 0, a SME804 is in output 826 The high signal of upper output and the testing circuit 838 of the 2nd SME805 is set as active state.When at the number corresponding to position 1 According to when sensing high signal on streamline 836, the 2nd SME805 exports high signal to activate another SME in output 828 504, SME805 or confession export from FSM engine 800.

Source code is converted into the method 1000 being configured to program the image of parallel machine by Figure 19 graphic extension for compiler Example.Method 1000 includes source code is parsed into syntax tree (frame 1002), and described syntax tree is converted into automat (frame 1004), optimize described automat (frame 1006), described automat is converted into netlist (frame 1008), described netlist is placed in On hardware (frame 1010), it route described netlist (frame 1012) and announce gained image (frame 1014).

In one example, compiler includes allowing software developer to create for implementing FSM's on FSM engine 800 The application programming interface (API) of image.Compiler provides in order to be converted into by the input regular expression collection in source code The method being configured to program the image of FSM engine 800.Can be by the computer for having von Karman framework Described compiler is implemented in instruction.These instructions can cause the processor on computer to implement the function of compiler.Citing comes Saying, described instruction can cause processor source code accessible to described processor to perform frame when being performed by processor 1002, the action described in 1004,1006,1008,1010,1012 and 1014.Figure 20 shows have Feng Nuo The exemplary computer of Yi Man framework and being hereafter described.

In one example, source code describes the search string of the symbol pattern in distinguished symbol group.In order to describe search String, source code can include multiple regular expression (regex).Regular expression can be the string for descriptor search pattern. Regular expression is widely used in various computer realm, such as programming language, text editor, network security And other field.In one example, the regular expression that compiler is supported includes for searching for searching of unstructured data Rope criterion.Unstructured data can include the data of free form and not have the index of the word being applied in described data. Word can include any combination of the printable and unprintable byte in described data.In one example, compiler can prop up Hold multiple different language source code for implement to include Perl (such as, Perl compatibility regular expression (PCRE)), PHP, The regular expression of Java and .NET language.

At frame 1002, compiler can dissect the layout of the operator that source code connects, wherein inhomogeneity with formation relation Different functions (the difference that such as, the regular expression in source code is implemented that the operator of type is implemented corresponding to source code Function).Anatomy source code can create the generic of described source code and represent.In one example, described generic represents and comprises source generation The encoded expression of the regular expression in Ma, it is in the form of the tree diagram of referred to as syntax tree.Example as herein described relates to And the layout as syntax tree (also referred to " abstract syntax tree "), but can use in other example concrete syntax tree or Other is arranged.

As mentioned above, owing to compiler can support the polyglot of source code, therefore no matter language how to dissect all by Source code is converted into the specific expression of non-language (such as, syntax tree).Therefore, no matter the language of source code how, by compiling The process (frame 1004,1006,1008,1010) further that device is carried out all can be worked from shared input structure.

As it has been described above, syntax tree includes multiple operators that relation connects.Syntax tree can include the computing of number of different types Symbol.It is to say, the different functions that the nonidentity operation symbol regular expression that may correspond in source code is implemented.

At frame 1004, syntax tree is converted into automat.Software model that automat comprises FSM and can therefore classifying For definitiveness or uncertainty.Deterministic automation has a single execution route in preset time, and non-deterministic automata The execution route while of having multiple.Described automat comprises multiple state.In order to syntax tree is converted into automat, by language The relation between operator and operator in method tree is converted into state, has transformation between wherein said state.Real one In example, may be based partly on the hardware of FSM engine 800 and change described automat.

In one example, the incoming symbol for automat includes letter, numeral 0 to 9 and the symbol of other printable character Number.In one example, incoming symbol is represented by byte value 0 to 255 (including 0 and 255).In one example, automatically Machine is represented by directed graph, and the node of wherein said figure corresponds to state set.In one example, incoming symbol α is (namely Say, δ (p, α) is shown by from node p to the directed connection of node q from changing of state p to state q.At an example In, the reversion of automat produces new automat, and each transformation p → q in the most a certain symbol α is anti-on same symbol Turn q → p.In reversion, beginning state becomes end-state and end-state becomes beginning state.In one example, certainly It is will to arrive all of end-state when being sequentially input in described automat that motivation is accepted the language of (such as, coupling) The collection of possible character string.Every a string tracking in the language that described automat is accepted from beginning state to or one with The path of upper end-state.

At frame 1006, after structure automat, optimize described automat the most also to reduce its complexity And size.Described automat can be optimized by Combinational redundancy state.

At frame 1008, optimized automat is converted into netlist.Described automat is converted into netlist by described from Hardware element that each state of motivation is mapped on FSM engine 800 (such as, SME804,805, other element 824) And determine the connection between described hardware element.

At frame 1010, place described netlist to select the specific of each node corresponding to described netlist of destination apparatus Hardware element (such as, SME804,805, professional component 824).In one example, place based on FSM engine 800 Typically enter and output constraint and select each specific hardware element.

At frame 1012, route the netlist placed to determine for programmable switch (such as, switch 803 between block, Switch 812 in switch 808 and row in block) setting, in order to selected hardware element is coupled to realize netlist and is retouched The connection stated.In one example, be determined by FSM engine 800 will be in order to connect selected hardware element and be used for can The particular conductor of the setting of program switch determines the setting for programmable switch.Compared to the placement at frame 1010, Route may consider the particularly restriction of the connection between hardware element.Therefore it is presumed that have on FSM engine 800 The physical constraints of conductor, route may be adjusted by some hardware elements in described hardware element determined by universe placement Position is suitably to connect.

Once netlist is placed and route, and just the described netlist being placed and routeing can be converted into and draw for programming FSM Hold up multiple positions of 800.The plurality of position is herein referred to as image.

At frame 1014, compiler announces image.Described image comprises the specific hardware for programming FSM engine 800 Element and/or multiple positions of programmable switch.The most described image comprises in the embodiment of multiple position (such as, 0 and 1), Described image can be referred to as binary picture.Institute's rheme can be loaded on FSM engine 800 with programming SME804,805, Professional component 824 and the state of programmable switch, retouched so that programmed FSM engine 800 implements have source code The functional FSM stated.Place (frame 1010) and route (frame 1012) can be by the specific location in FSM engine 800 The particular state that is mapped in automat of specific hardware element.Therefore, the position specific hardware able to programme unit in described image Part and/or programmable switch are to implement wanted function.In one example, can be by machine code be saved in computer-readable Media announce described image.In another example, can by described image is shown in display device announce described Image.In a further example, can (such as be used for loading images into FSM engine by sending images to another device Programmer on 800) announce described image.In a further example, can be by loading images into parallel machine (such as, FSM engine 800) on announce described image.

In one example, can be by the place value from image being loaded directly into SME804,805 and other hardware element 824 or by described image being loaded in one or more depositors and then by the place value from described depositor It is written to SME804,805 and other hardware element 824 and described image is loaded on FSM engine 800.One In example, the state of programmable switch (such as, switching switch 812 in 803, the interior switch 808 of block and row between block).One In example, the hardware element of FSM engine 800 (such as, SME804,805, other element 824, programmable switch 803,808,812) stored device maps so that programmer and/or computer can be by being written to one by described image Or more than one storage address and described image is loaded on FSM engine 800.

Method described herein example can be machine or computer-implemented at least in part.Some examples can include with instruction The computer-readable media of coding or machine-readable medium, described instruction is operable above real to perform with configuration electronic installation Method described in example.The embodiment of these a little methods can include code, such as microcode, assembler language code, senior language Speech code etc..This code can include the computer-readable instruction for performing various method.Described code can form computer The part of program product.Additionally, described code can the term of execution or be the most visibly stored in one or one In above volatibility or non-volatile computer readable medium.These computer-readable medias can include, but is not limited to hard disk, Removable disk, CD (such as, compact disk and digital video disk), cassette tape, storage card or storage can be loaded and unloaded Rod, random access memory (RAM), read only memory (ROM) etc..

Figure 20 generally illustrate has the example of the computer 1500 of von Karman framework.Reading and understanding the present invention Content after, those skilled in the art is by once understand can computer-readable media from computer based system Activate software program in the way of the function defined in the described software program of execution.Those skilled in the art will enter one Step understanding can be used to create one or more software programs being designed to be practiced and carried out method disclosed herein Various programming languages.Object-oriented language (such as Java, C++ or one or more other languages can be used Speech) carry out structured program with OO form.Or, program language (such as compilation, C etc.) can be used with towards journey The form of sequence carrys out structured program.Component software can use the well-known several mechanism (example of those skilled in the art Such as application programming interfaces or inter-process communication techniques, including remote procedure call or other) in any one communicate.Respectively The teaching planting embodiment is not limited to arbitrary specific program design language or environment.

Therefore, other embodiments can be realized.For example, goods (such as computer, accumulator system, disk or CD, A certain other stores device or any type of electronic installation or system) can include that being coupled to storage on it has instruction 1524 The computer-readable media 1522 of (such as, computer program instructions) (such as memorizer (such as, can removable storage media with And include any memory of electricity, optics or electromagnetic conductor)) one or more processors 1502, described instruction exists Cause when being performed by one or more processors 1502 performing about any one in the action described in above method.

Computer 1500 can be taked to have directly and/or use bus 1508 to be coupled to the processor 1502 of several assemblies The form of computer system.These a little assemblies can include main storage 1504, static or nonvolatile memory 1506 and Mass storage device 1516.Other assembly being coupled to processor 1502 can include output device 1510 (such as video Display), input equipment 1512 (such as keyboard) and cursor control device 1514 (such as mouse).In order to by processor 1502 And other assembly is coupled to the Network Interface Unit 1520 of network 1526 and may also couple to bus 1508.Can be utilized several Any one in well-known transportation protocol (such as, HTTP) is enterprising at network 1526 via Network Interface Unit 1520 One step transmission or reception instruction 1524.Any one being coupled in these elements of bus 1508 can be depending on to be achieved Specific embodiment and do not exist, individualism or with plural number number exist.

In one example, processor 1502, memorizer 1504,1506 or storage device 1516 in one or one with On can each include can causing upon execution computer 1500 perform any one in method described herein or one with On instruction 1524.In alternative embodiments, computer 1500 maybe can connect (such as, networking) as self-contained unit operation To other device.In networked environment, computer 1500 can be with server or visitor in server-client network environment The qualification of family end device or operate as peer in equity (or distributed) network environment.Computer 1500 can include Personal computer (PC), flat board PC, Set Top Box (STB), personal digital assistant (PDA), cellular phone, Network device Tool, network router, switch or bridger or be able to carry out is specified and is treated that the instruction set of action taked by described device is (suitable Sequence or otherwise) any device.Although additionally, the only single computer of graphic extension 1500, but term " calculates Machine " shall also be taken to include and individually or collectively perform an instruction set (or multiple instruction set) to perform method discussed herein In any one or one or more of any device set.

Computer 1500 may also include o controller 1528 for using one or more communication protocols (such as, USB (universal serial bus) (USB), IEEE1394 etc.) and peripheral communication.O controller 1528 can (such as) by image There is provided to the programmer 1530 being communicably coupled to computer 1500.Programmer 1530 can be configured with programming Parallel machine (such as, parallel machine 100, FSM engine 800).In other example, programmer 1530 can be with computer 1500 integrate and are coupled to bus 1508 or can be via Network Interface Unit 1520 or another device and computer 1500 communications.

Although computer-readable media 1524 being shown as single medium, but term " computer-readable media " should be regarded as Including storing the single medium of one or more instruction set 1524 or multiple media (such as, centralized or distributed number According to storehouse, or associated cache and server, and/or various storage media, such as processor 1502 are deposited Device, memorizer 1504,1506 and storage device 1516).Term " computer-readable media " shall also be taken to include can Storage, coding or carrying instruction set perform for described computer and cause described computer to perform in the method for the present invention Any one or one or more of maybe can store, encode or number that this instruction set of carrying is utilized or is associated with this instruction set Arbitrary media according to structure.Term " computer-readable media " therefore should be regarded as including, but is not limited to tangible medium (such as Solid-state memory), optical media and magnetic medium.

Thering is provided abstract of invention to meet 37C.F.R. 1.72 (b) money, it needs that permission reader finds out described technology and discloses interior The essence held and the summary of purport.Submit this summary to based on the understanding that it not in order to limit or will explain claim The scope of book or implication.Hereby being incorporated in detailed description by appended claims, each of which claim self is made For independent embodiment.

Example embodiments

Example 1 includes a kind of programmable device, and it has multiple programmable element, and wherein said programmable element is configured To implement one or more finite state machines, wherein said multiple programmable elements are configured to receive the input of N numeral And provide M-digit output, the output of wherein said M-digit to include from all or fewer than described according to the input of described N numeral The status information of programmable element.

Example 2 includes a kind of level parallel machine, and it has: the first parallel machine, it comprises multiple programmable element, wherein Described programmable element is configured to implement one or more finite state machines, wherein said multiple programmable element warps Configuring to receive the input of N numeral and provide M-digit output according to the input of described N numeral, wherein said M-digit exports Including from the status information all or fewer than described programmable element；And second parallel machine, it is configured to receive and process It is at least some of that described M-digit exports.

Example 3 includes a kind of programmable device, and it has multiple programmable element, and wherein said programmable element is configured To implement one or more finite state machines, wherein said multiple programmable elements are configured to receive the input of N numeral And according to described N numeral input provide M-digit output, wherein said M-digit output be by compression from described can The status information of each in programmed element and formed.

Example 4 includes a kind of level parallel machine, and it has: the first parallel machine, it comprises multiple programmable element, wherein Described programmable element is configured to implement one or more finite state machines, wherein said multiple programmable element warps Configuring to receive the input of N numeral and provide M-digit output according to the input of described N numeral, wherein said M-digit exports It is to be formed from the status information of each in described programmable element by compression.

Example 5 includes a kind of method providing another device from parallel machine by status information, and wherein said parallel machine includes Multiple programmable elements, each in wherein said programmable element is configured to have corresponding states.Described method bag Include: determine each in the described programmable element that status information, wherein said status information comprise in described parallel machine State；Compress described status information；And provide another device described by described compressed status information.

Example 6 includes a kind of level parallel machine, and it has the input of at least one N numeral and the output of multiple N numeral The first level parallel machine, wherein said N numeral output in each correspond to institute on described first level parallel machine The relevant groups of the N number of state machine implemented.

Example 7 includes a kind of multiple programmable elements parallel comprising and being configured to implement at least one finite state machine Machine.Described parallel machine is configured to: determine that status information, wherein said status information comprise in described programmable element The state of each；Compress described status information；And provide another device by described compressed status information.

In example 8, the subject matter of any one in example 1 to 7 optionally includes wherein said multiple unit able to programme Part comprises the one in two or more programmable element groups.

In example 9, the subject matter of any one of example 1 to 8 optionally includes: N digital input interface, its coupling Close one programmable element group and be configured to receive the input of described N numeral；And M-digit output interface, It is coupled to one programmable element group and is configured to provide described M-digit to export.

In example 10, the subject matter of any one in example 1 to 9 optionally include wherein said one able to programme Element group comprises programmable element block.

In example 11, the subject matter of any one in example 1 to 10 optionally includes wherein said programmable element Block comprises multiple programmable element row, and each in wherein said row is coupled in multiple pieces the corresponding one in switch.

In example 12, it is each that the subject matter of any one in example 1 to 11 optionally includes in wherein said row Programmable element in person comprises: multiple groups of two state machine elements；And another programmable element.

In example 13, the subject matter of any one in example 1 to 12 optionally includes: programmable switch, its warp Configure optionally one programmable element group to be coupled to the another one in described programmable element group；Defeated Inbound port；And/or output port.

In example 14, the subject matter of any one in example 1 to 13 optionally includes depositor, described depositor It is configured to store and is configured to program the plurality of programmable element and the program of the plurality of programmable switch.

In example 15, the subject matter of any one in example 1 to 14 optionally includes that wherein N is equal to M.

In example 16, the subject matter of any one in example 1 to 15 optionally includes that wherein M is the integer of N Multiple.

In example 17, the subject matter of any one in example 1 to 16 optionally includes "or" logic, described "or" Logic be configured to be polymerized from described programmable element in order to implement two of same one in described finite state machine Person or the output that both are above.

In example 18, the subject matter of any one in example 1 to 17 optionally includes wherein said programmable element Being configured to implement the logical group of N number of state machine, the described output of wherein said N number of state machine is aggregated to provide Described M-digit exports.

In example 19, example 1 to ▲ in the subject matter of any one optionally include that wherein said logic comprises "or" Door.

In example 20, the subject matter of any one in example 1 to 19 optionally includes that wherein said M-digit exports Described status information included by comprises compressed status information.

In example 21, the subject matter of any one in example 1 to 20 optionally includes wherein said multiple able to programme Element comprises state machine element.

In example 22, the subject matter of any one in example 1 to 21 optionally includes that wherein said M-digit exports Comprise difference vector.

In example 23, the subject matter of any one in example 1 to 22 optionally includes wherein said implemented one Each state in individual or more than one finite state machine corresponding to the respective digital in state vector, and wherein said difference to Amount only includes those numbers changed in response to offer in described state vector to the incoming symbol of described programmable device Word.

In example 24, the subject matter of any one in example 1 to 23 optionally includes wherein said implemented one Each state in individual or more than one finite state machine is corresponding to the respective digital in state vector, and wherein said M number Word output only comprises the subset of the described numeral in described state vector.

In example 25, the subject matter of any one in example 1 to 24 optionally includes described in wherein said numeral Subset comprises those numerals corresponding to the end-state in one or more than one finite state machine.

In example 26, the subject matter of any one in example 1 to 25 optionally includes institute the most in said device The all state machines implemented receive the input of described N numeral.

In example 27, the subject matter of any one in example 1 to 26 optionally includes wherein said multiple able to programme Element comprises the one in two or more programmable element groups, and each in wherein said group has it certainly Oneself special input.

In example 28, the subject matter of any one in example 1 to 27 optionally includes that wherein said N numeral inputs On the bottom of semiconductor die, and wherein said M-digit exports on the top of described semiconductor die.

In example 29, the subject matter of any one in example 1 to 28 optionally includes wherein said multiple able to programme Element comprises the one in two or more programmable element groups, and wherein said programmable device be configured to by Status information one from described group provides the another one in the described group in described programmable device.

In example 30, the subject matter of any one in example 1 to 29 optionally includes wherein said second parallel machine It is configured to receive and process the output of described whole M-digit.

In example 31, the subject matter of any one in example 1 to 30 optionally includes: input bus, its coupling To described first parallel machine and be configured to provide described N numeral to input；And output bus, it is coupled in described first also Between row machine and described second parallel machine, described output bus is configured to carry what described M-digit exported at least partially It is fed to described second parallel machine.

In example 32, the subject matter of any one in example 1 to 31 optionally include wherein said input bus with Output bus is the most equal.

In example 33, the subject matter of any one in example 1 to 32 optionally include wherein said first and second Described corresponding group in parallel machine is coupled by corresponding cross tie part group.

In example 34, the subject matter of any one in example 1 to 33 optionally includes that the output of described M-digit is carried It is fed to each state machine implemented in described second parallel machine.

In example 35, the subject matter of any one in example 1 to 34 optionally includes wherein said second parallel machine Comprising the multiple programmable elements being grouped into multiple group, the output of wherein said M-digit is to provide according to predefined mode Corresponding one in described group.

In example 36, the subject matter of any one in example 1 to 35 optionally includes wherein said second parallel machine Comprise the multiple programmable elements being configured to that address information is sent to described second parallel machine, wherein said address information The output of described M-digit is just being provided which one in the described group in described second parallel machine by instruction.

In example 37, the subject matter of any one in example 1 to 36 optionally includes that wherein said parallel machine is heap Fold.

In example 38, the subject matter of any one in example 1 to 37 optionally includes wherein said multiple able to programme Element comprises the one in two or more programmable element groups, and it comprises patrolling corresponding to each group further Volume, wherein corresponding to the corresponding one in described group described logical aggregate from two in described group or two with The status information of upper programmable element, and wherein from described group described M-digit export one or more number Word is the function of this logic.

In example 39, the subject matter of any one in example 1 to 38 optionally includes that wherein said M-digit exports It is to be formed from the status information of described programmable element by compression.

In example 40, the subject matter of any one in example 1 to 39 optionally includes logic, and described logic is through joining Put with polymerization from described programmable element in order to implement same one in described finite state machine both or both Above output.

In example 41, the subject matter of any one in example 1 to 40 optionally includes wherein said programmable element Being configured to implement the logical group of N number of state machine, the described output of wherein said N number of state machine is aggregated to provide Described M-digit exports.

In example 42, the subject matter of any one in example 1 to 41 optionally includes wherein compressing described state letter Breath includes described status information application lossless compression algorithm.

In example 43, the subject matter of any one in example 1 to 42 optionally includes wherein by described compressed shape State information provides another device described to comprise and provides another parallel machine by described compressed status information.

In example 44, the subject matter of any one in example 1 to 43 optionally includes wherein by described compressed shape State information provides another device described to comprise and provides system storage by described compressed status information.

In example 45, the subject matter of any one in example 1 to 44 optionally includes wherein compressing described state letter Breath comprises the end-state being aggregated on described parallel machine in the finite state machine implemented.

In example 46, the subject matter of any one in example 1 to 45 optionally includes the first level parallel machine, its There is the input of at least one N numeral and the output of multiple N numeral, each corresponding in the output of wherein said N numeral The relevant groups of the N number of state machine implemented on described first level parallel machine.

In example 47, the subject matter of any one in example 1 to 46 optionally includes wherein in described first level At least one in the described state machine implemented on parallel machine include corresponding at least one state machine described multiple Multiple programmable elements of whole state, wherein would correspond to the plurality of programmable element defeated of the plurality of end-state Go out the numeral condensing together to provide the one in the output of described N numeral.

In example 48, the subject matter of any one in example 1 to 47 optionally includes wherein defeated in described N numeral The described phase of N number of state machine that the data encoding provided in the one gone out is implemented on described first level parallel machine Answer the situation of the described end-state of group.

In example 49, the subject matter of any one in example 1 to 48 optionally includes wherein said first level also Row machine comprises limited state machine engine.

In example 50, the subject matter of any one in example 1 to 49 optionally includes wherein said finite state machine Engine comprises each in programmable element group array, and wherein said programmable element group and is coupled to described N number Corresponding one in word output.

In example 51, the subject matter of any one in example 1 to 50 optionally includes wherein said first level also Row facility have each in the input of multiple N numeral and wherein said programmable element group to be coupled to described first level Corresponding one in the described N numeral input of parallel machine.

In example 52, the subject matter of any one in example 1 to 51 optionally includes wherein said second level also Row machine comprises limited state machine engine.

In example 53, the subject matter of any one in example 1 to 52 optionally includes wherein said finite state machine Engine comprises each in programmable element group array, and wherein said programmable element group and is coupled to described N number Corresponding one in word input.

In example 54, the subject matter of any one in example 1 to 53 optionally includes wherein said second level also Row facility have each in the output of multiple N numeral and wherein said programmable element group to be coupled to described second level Corresponding one in the described N numeral output of parallel machine.

In example 55, the subject matter of any one in example 1 to 54 optionally includes wherein said first parallel machine Comprise the first nude film, and described second parallel machine comprises the second nude film together with described first die stack.

In example 56, it is parallel that the subject matter of any one in example 1 to 55 optionally includes comprising the 3rd further Machine and bus, wherein said 3rd parallel machine comprises the 3rd together with described first nude film and described second die stack Nude film, between wherein said second nude film described first nude film and described 3rd nude film in described stacking, and wherein institute State bus and be configured to transferring status data between described first parallel machine and described 3rd parallel machine.

In example 57, the subject matter of any one in example 1 to 56 optionally includes that wherein said bus packet is containing many Individual cross tie part.

In example 58, the subject matter of any one in example 1 to 57 optionally includes that wherein said cross tie part comprises Reach through hole cross tie part.

In example 59, the subject matter of any one in example 1 to 58 optionally includes that wherein said parallel machine comprises Finite state machine engine.

In example 60, the subject matter of any one in example 1 to 59 optionally includes wherein said finite state machine Engine comprises pattern-recognition processor.

In example 61, the subject matter of any one in example 1 to 60 optionally includes that wherein said parallel machine comprises Field programmable gate array.

In example 62, the subject matter of any one in example 1 to 61 optionally includes wherein said first level also At least one N numeral described input of row machine is configured to receive initial data.

In example 63, the subject matter of any one in example 1 to 62 optionally includes wherein said second level also The N number of state each corresponding to be implemented on described second level parallel machine in the described N numeral input of row machine The relevant groups of machine, each group of the N number of state machine wherein implemented on described second level parallel machine is by described The most N number of state machine implemented on first level parallel machine drives.

In example 64, the subject matter of any one in example 1 to 63 optionally includes that wherein another device comprises Two parallel machines, wherein said second parallel machine is configured to receive and process described compressed status information.

In example 65, the subject matter of any one in example 1 to 64 optionally includes that wherein said parallel machine is through joining Put to compress described status information to comprise described parallel machine and be configured to be aggregated on described parallel machine the limited shape implemented The end-state of state machine.

In example 66, the subject matter of any one in example 1 to 65 optionally includes being configured to described in polymerization The Boolean logic of whole state.

In example 67, the subject matter of any one in example 1 to 66 optionally includes that wherein said parallel machine is through joining Putting to compress described status information to comprise described parallel machine and be configured to export difference vector, wherein said difference vector has only identified Those states changed in response to incoming symbol.

In example 68, the subject matter of any one in example 1 to 67 optionally includes that wherein said parallel machine is through joining Putting to compress described status information to comprise described parallel machine and be configured to export output vector, wherein said output vector only carries The status information of the end-state in the finite state machine that confession is implemented on described parallel machine.

Claims

1. a programmable device, it comprises:

Multiple programmable elements, wherein said programmable element is configured to implement more than one finite state machine, Wherein said multiple programmable element includes that state machine element, the most each described state machine element include multiple storage Device unit and be configured to sense that the testing circuit of output of the plurality of memory cell, wherein said multiple compiles Journey element is configured to receive the input of N numeral and provide M-digit output according to the input of described N numeral, wherein said M-digit output includes from the status information all or fewer than described programmable element, wherein said multiple units able to programme Part comprises the one in two or more programmable element group.

Programmable device the most according to claim 1, it comprises further:

N digital input interface, it is coupled in said two above programmable element group and is configured To receive the input of described N numeral；And

M-digit output interface, it is coupled in said two above programmable element group and is configured To provide the output of described M-digit.

Programmable device the most according to claim 1, a bag in wherein said two or more programmable element group Containing programmable element block.

Programmable device the most according to claim 3, wherein said programmable element block comprises multiple programmable element row, Each in wherein said row is coupled in multiple pieces the corresponding one in switch.

Programmable device the most according to claim 4, each in wherein said row comprises:

Multiple state machine elements pair；And

Another programmable element.

Programmable device the most according to claim 1, it comprises further:

Programmable switch, it is configured to optionally by above for said two programmable element group It is coupled to another one, input port and/or the output port in described programmable element group.

Programmable device the most according to claim 6, it comprises further:

Depositor, it is configured to storage and is configured to program the plurality of programmable element and described programmable switch The program closed.

Programmable device the most according to claim 1, wherein N is equal to M.

Programmable device the most according to claim 1, wherein M is the integer multiple of N.

Programmable device the most according to claim 1, it comprises further:

"or" logic, its be configured to be polymerized from described programmable element in order to implement described limited shape Both above outputs of same one in state machine.

11. programmable devices according to claim 10, wherein said programmable element is configured to implement N number of state The logical group of machine, the output of wherein said N number of state machine is aggregated to provide the output of described M-digit.

12. programmable devices according to claim 10, wherein said logic comprises OR-gate.

13. programmable devices according to claim 1, described status information included in the output of wherein said M-digit Comprise compressed status information.

14. programmable devices according to claim 1, the output of wherein said M-digit comprises difference vector.

15. programmable devices according to claim 14, each shape in more than one finite state machine wherein implemented State is corresponding to the respective digital in state vector, and wherein said difference vector only includes the response in described state vector In providing those numerals changed to the incoming symbol of described programmable device.

16. programmable devices according to claim 1, each shape in more than one finite state machine wherein implemented State is corresponding to the respective digital in state vector, and the output of wherein said M-digit only comprises in described state vector The subset of described numeral.

17. programmable devices according to claim 16, the described subset of wherein said numeral comprises corresponding to one Those numerals of end-state in above finite state machine.

18. programmable devices according to claim 1, all state machines implemented the most in said device receive institute State the input of N numeral.

19. programmable devices according to claim 1, each in wherein said group has the special defeated of their own Enter.

20. programmable devices according to claim 1, wherein said N numeral inputs on the bottom of semiconductor die, And wherein said M-digit exports on the top of described semiconductor die.

21. programmable devices according to claim 1, wherein said programmable device is configured to described dress able to programme Put and provide the another one in described group by status information one from described group.

22. 1 kinds of level parallel machines, it comprises:

First parallel machine, it comprises multiple programmable element, and wherein said programmable element is configured to implement one Individual above finite state machine, wherein said multiple programmable elements include state machine element, the most each described state Machine element include multiple memory cell and be configured to sense that the plurality of memory cell output detection electricity Road, wherein said multiple programmable elements are configured to receive the input of N numeral and provide according to the input of described N numeral M-digit exports, and the output of wherein said M-digit includes from the status information all or fewer than described programmable element； And

Second parallel machine, it is configured to receive and process at least some of of described M-digit output.

23. level parallel machines according to claim 22, wherein said second parallel machine is configured to receive and described in process M-digit exports.

24. level parallel machines according to claim 22, it comprises further:

Input bus, it is coupled to described first parallel machine and is configured to provide described N numeral to input；And

Output bus, it is coupled between described first parallel machine and described second parallel machine, described output bus At least some of offer being configured to export described M-digit arrives described second parallel machine.

25. level parallel machines according to claim 24, wherein said input bus is the most equal with output bus.

26. level parallel machines according to claim 25, the correspondence unit able to programme in first and second parallel machine wherein said Part group is coupled by corresponding cross tie part group.

27. level parallel machines according to claim 22, the output of wherein said M-digit is provided to described second also The each state machine implemented in row machine.

28. level parallel machines according to claim 22, wherein said second parallel machine comprises that to be grouped into multiple group many Individual programmable element, the output of wherein said M-digit is to provide corresponding in described group according to predefined mode Person.

29. level parallel machines according to claim 22, wherein said second parallel machine comprise be grouped into multiple group and It is configured to be sent to address information multiple programmable elements of described second parallel machine, wherein said address information The output of described M-digit is just being provided which one in the described group in described second parallel machine by instruction.

30. level parallel machines according to claim 22, wherein said first parallel machine and described second parallel machine are stacking 's.

31. level parallel machines according to claim 22, it is able to programme that wherein said multiple programmable elements comprise two or more One in element group, it comprises the logic corresponding to each group further, wherein corresponding in described group The described logical aggregate of corresponding one from the status information of the two or more programmable element in described group, and The function that more than one numeral is this logic wherein exported from the described M-digit of described group.

32. level parallel machines according to claim 22, wherein said M-digit output be by compression from described can The status information of programmed element and formed.

33. 1 kinds of programmable devices, it comprises:

Multiple programmable elements, wherein said programmable element is configured to implement more than one finite state machine, Wherein said multiple programmable element includes that state machine element, the most each described state machine element include multiple storage Device unit and be configured to sense that the testing circuit of output of the plurality of memory cell, wherein said multiple compiles Journey element is configured to receive the input of N numeral and provide M-digit output according to the input of described N numeral, wherein said M-digit output is to be formed from the status information of each in described programmable element by compression.

34. programmable devices according to claim 33, wherein N is equal to M.

35. programmable devices according to claim 33, wherein M is the integer multiple of N.

36. programmable devices according to claim 33, it comprises further:

Logic, its be configured to be polymerized from described programmable element in order to implement in described finite state machine Both above outputs of same one.

37. programmable devices according to claim 36, wherein said programmable element is configured to implement N number of state The logical group of machine, the described output of wherein said N number of state machine is aggregated to provide the output of described M-digit.

38. 1 kinds of level parallel machines, it comprises:

First parallel machine, it comprises multiple programmable element, and wherein said programmable element is configured to implement one Individual above finite state machine, wherein said multiple programmable elements include state machine element, the most each described state Machine element include multiple memory cell and be configured to sense that the plurality of memory cell output detection electricity Road, wherein said multiple programmable elements are configured to receive the input of N numeral and provide according to the input of described N numeral M-digit exports, and the output of wherein said M-digit is by compressing the shape from each in described programmable element State information and formed.

39. according to the level parallel machine described in claim 38, and wherein N is equal to M.

40. according to the level parallel machine described in claim 38, and wherein M is the integer multiple of N.

41. 1 kinds of methods providing another device from parallel machine by status information, wherein said parallel machine includes multiple able to programme Element, wherein said multiple programmable elements include state machine element, and the most each described state machine element includes many Individual memory cell and be configured to sense that the testing circuit of output of the plurality of memory cell, wherein said can Each in programmed element is configured to have corresponding states, and described method comprises:

Determine in the described programmable element that status information, wherein said status information comprise in described parallel machine The described state of each；

Compress described status information；And

Compressed status information is provided another device described.

42. methods according to claim 41, wherein compress described status information and include: to described status information application nothing Damage compression algorithm.

43. methods according to claim 41, wherein provide another device bag described by described compressed status information Contain: provide another parallel machine by described compressed status information.

44. methods according to claim 41, wherein provide another device bag described by described compressed status information Contain: provide system storage by described compressed status information.

45. methods according to claim 41, wherein compress described status information and comprise: be aggregated in institute on described parallel machine End-state in the finite state machine implemented.

46. 1 kinds of level parallel machines, it comprises:

First level parallel machine, it has the input of at least one N numeral and the output of multiple N numeral, Qi Zhongsuo State the phase of the N number of state machine each corresponding to be implemented on described first level parallel machine in the output of N numeral Answering group, at least one in the described state machine wherein implemented on described first level parallel machine includes correspondence In multiple programmable elements of multiple end-state, wherein said multiple programmable elements include state machine element, its In each described state machine element include multiple memory cell and be configured to sense that the plurality of memory cell The testing circuit of output.

47. level parallel machines according to claim 46, wherein would correspond to the plurality of of the plurality of end-state can The output of programmed element condenses together to provide a numeral of the one in the output of described N numeral.

48. level parallel machines according to claim 46, the number wherein provided in the one in described N numeral exports The end-state of the described relevant groups of N number of state machine implemented on described first level parallel machine according to coding Situation.

49. level parallel machines according to claim 46, wherein said first level parallel machine comprises finite state machine and draws Hold up.

50. level parallel machines according to claim 49, wherein said finite state machine engine comprises programmable element group Each in group, and wherein said programmable element group is coupled to the corresponding one in the output of described N numeral.

51. level parallel machines according to claim 50, it is defeated that wherein said first level parallel machine has multiple N numeral Enter, and each in wherein said programmable element group is coupled to the described N number of described first level parallel machine Corresponding one in word input.

52. level parallel machines according to claim 46, it comprises the second level parallel machine, described second level further Parallel machine comprises limited state machine engine.

53. level parallel machines according to claim 52, wherein said finite state machine engine comprises programmable element group Each in group, and wherein said programmable element group is coupled to the corresponding one in the input of described N numeral.

54. level parallel machines according to claim 53, it is defeated that wherein said second level parallel machine has multiple N numeral Go out, and each in wherein said programmable element group is coupled to the described N number of described second level parallel machine Corresponding one in word output.

55. level parallel machines according to claim 46, it comprises the second level parallel machine further, and wherein said first Hierarchical parallel machine comprises the first nude film, and described second level parallel machine comprises together with described first die stack The second nude film.

56. level parallel machines according to claim 55, it comprises third layer level parallel machine and bus, Qi Zhongsuo further State third layer level parallel machine and comprise the 3rd nude film together with described first nude film and described second die stack, its Described between second nude film described first nude film and described 3rd nude film in described stacking, and wherein said always Line is configured to transferring status data between described first level parallel machine and described third layer level parallel machine.

57. level parallel machines according to claim 56, wherein said bus packet contains multiple cross tie parts.

58. level parallel machines according to claim 57, wherein said cross tie part comprises reach through hole cross tie part.

59. level parallel machines according to claim 49, wherein said finite state machine engine comprises pattern identification and processes Device.

60. level parallel machines according to claim 46, wherein said first level parallel machine comprises field-programmable gate array Row.

61. level parallel machines according to claim 46, at least one N described of wherein said first level parallel machine Numeral input is configured to receive initial data.

62. level parallel machines according to claim 46, it comprises the second level parallel machine further, and wherein said second Each corresponding in the described N numeral input of hierarchical parallel machine is implemented on described second level parallel machine The relevant groups of N number of state machine, the N number of state machine wherein implemented on described second level parallel machine each Group is driven by the most N number of state machine implemented on described first level parallel machine.

63. 1 kinds of parallel machines comprising the multiple programmable elements being configured to implement at least one finite state machine, wherein said Multiple programmable elements include state machine element, the most each described state machine element include multiple memory cell and It is configured to sense that the testing circuit of the output of the plurality of memory cell, wherein said parallel machine are configured to:

Determine that status information, wherein said status information comprise the state of each in described programmable element；

Compress described status information；And

Another device is provided by compressed status information.

64. parallel machines according to claim 63, another device wherein said comprises the second parallel machine, and wherein said second Parallel machine is configured to receive and process described compressed status information.

65. parallel machines according to claim 63, wherein said parallel machine is configured to compress described status information and comprises:

Described parallel machine is configured to be aggregated on described parallel machine the end-state of the finite state machine implemented.

66. parallel machines according to claim 65, it comprises the boolean being configured to be polymerized described end-state further and patrols Volume.

67. parallel machines according to claim 63, wherein said parallel machine is configured to compress described status information and comprises:

Described parallel machine is configured to export difference vector, and wherein said difference vector only identifies and changed in response to incoming symbol Those states.

68. parallel machines according to claim 63, wherein said parallel machine is configured to compress described status information bag Contain: described parallel machine is configured to export output vector, and wherein said output vector is provided in only on described parallel machine The status information of the end-state in the finite state machine implemented.