CN103023423A - Advanced phase compensation control unit and method for double-CPU (central processing unit) intelligent wound-rotor motor - Google Patents
Advanced phase compensation control unit and method for double-CPU (central processing unit) intelligent wound-rotor motor Download PDFInfo
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- CN103023423A CN103023423A CN2012105641830A CN201210564183A CN103023423A CN 103023423 A CN103023423 A CN 103023423A CN 2012105641830 A CN2012105641830 A CN 2012105641830A CN 201210564183 A CN201210564183 A CN 201210564183A CN 103023423 A CN103023423 A CN 103023423A
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Abstract
The invention discloses advanced phase compensation control unit and method for a double-CPU (central processing unit) intelligent wound-rotor motor. The control unit comprises a master control CPU, a CPLD (complex programmable logic device) logic control circuit, a co-CPU (central co-processing unit), an input/output interface end, an analog/digital conversion circuit, an SIM (subscriber identity module) storage card interface, a storage circuit, a first crystal oscillator, a first reset chip, a second reset chip, a second crystal oscillator and an external device. The analog/digital conversion circuit receives a command from the master control CPU, converts real-time system operational alternating-current electrical signals into digital signals and transmits the digital signals to the master control CPU. The master control CPU acquires system operational electrical quantity and calculates electrical parameters and control algorithm. The co-CPU receives pulse signal calculation results output from the master control CPU and outputs trigger pulse signals. The CPLD logic control circuit receives the trigger pulse signals from the co-CPU, formats the signals and outputs the signals to a thyristor. The control unit and method allow for high-intelligence, high-stability, high-reliability, distributed and high-precision control of variable frequency and variable velocity controllers, and save production cost.
Description
Technical field
The present invention relates to large power winding formula motor and advance phase compensation control system technical field, be specifically related to a kind of dual-cpu structure Intelligent wire wound motor and advance phase compensating controller and control method.
Background technology
In power transmission system, the asynchronous motor range of application is the most extensive.Design from asynchronous motor, power factor is the highest during at rated load operation is generally 0.85 when asynchronous motor, asynchronous motor often is not to move under rated power in the real work, its power factor reduction this moment, loss increase, so in the electric drive system that uses asynchronous machine, often adopt device compensation method to improve power factor, the minimizing reactive power of motor.
Carry out for powerful wire wound asynchronous motor that power factor compensation is normal to adopt following method: method 1, adopt the stator side shunt capacitor at asynchronous motor, method 2, adopt voltage and the revolutional slip of variable frequency regulating speed control method regulating electric machine stator.Reactive power and the interrupted switched capacitor capacity of method 1 on can only the compensation network line, can't Continuous Compensation and reliability lower, method 2 adopts thyristor as the composition of variable-frequency speed-regulating controller, and this variable-frequency speed-regulating controller can realize carrying out continuously the purpose of Reactive Power Control.
At present, abroad aspect Compensating Capacitance for Reactive Power of Asynchronous Motor, the control system complicated structure, the controller cost that generally adopt are higher.And China often adopts with the core control structure of single-chip microcomputer as the motor frequency change controller in the research of motor frequency change controller, and this motor frequency change controller ' s intellectualization degree is low, stability is low, reliability is low, can't realize distributed control.
When in the higher control system of electric current, because the motor frequency change controller lacks intelligent protection, so that after breaking down, the phenomenon of components and parts occurs burning.In addition, owing to adopting single-chip microcomputer as the core control structure of motor frequency change controller, so that the controller of single CPU structure is difficult to the control coordination in control algolithm and hardware logic output facet, and difficult realization aspect the high performance control algolithm of design, cause motor frequency change controller performance processed not good, can't realize high-precision control needs.
Therefore, based on the problems referred to above, the invention provides a kind of dual-cpu structure Intelligent wire wound motor and advance phase compensating controller and control method.
Summary of the invention
Goal of the invention: the objective of the invention is to provide a kind of dual-cpu structure Intelligent wire wound motor to advance phase compensating controller and control method, realize high-intelligentization, high stability, high reliability, distributed control and the high accuracy control purpose of variable-frequency speed-regulating controller.
Technical scheme: an aspect of of the present present invention, provide a kind of and advance the phase compensating controller for dual-cpu structure Intelligent wire wound motor, comprise that master cpu, CPLD logic control circuit, association process CPU, input/output interface end, mould/number conversion circuit, SIM memory card interface, memory circuitry, the first crystal oscillator, the first reset chip, the second reset chip, the second crystal oscillator and external equipment; Described CPLD logic control circuit, input/output interface end, mould/number conversion circuit, SIM memory card interface, memory circuitry, the first crystal oscillator and the reset chip of being connected all are connected with master cpu; Described mould/number conversion circuit connects the input/output interface end; Described CPLD logic control circuit connects the input/output interface end and association processes CPU; Described input/output interface end, the second reset chip and the crystal oscillator of being connected are all processed CPU with association and are connected; Described external equipment connects the input/output interface end.
Described external equipment comprises power supply, LCD panel and keyboard; Described power supply is powered to controller system; The operating state of described LCD panel display controller system; Described keyboard input service instruction.
Described master cpu reads parameter preset and carries out initialization; The real-time ac signal that described mould/instruction of number conversion circuit reception master cpu moves system is converted to digital quantity and transfers to master cpu; Described master cpu acquisition system operation electric parameters is also carried out the calculating of electrical quantity and control algolithm, obtains thyristor delay angle pulse signal and output; Described master cpu and association process CPU by realizing Real time data share with the cooperation of CPLD logic control circuit interface and communicate by letter, and LCD panel, keyboard connect the input/output interface end and carry out interaction by the CPLD logical circuit with master cpu and the processing CPU of association; Described association processes CPU and receives the thyristor delay angle pulse signal result of calculation of master cpu output and export satisfactory start pulse signal by the input/output interface termination; Described CPLD logic control circuit receives association and processes the CPU start pulse signal, standardizes to process to output to thyristor by the input/output interface end.
Described master cpu is responsible for that control algolithm is processed, mould/number circuit conversion is controlled, the adjustment of order parameter and setting and cooperate with CPLD logical circuit interface, finishes human-computer interaction by LCD panel and keyboard; Described master cpu is provided with standard serial port and built-in communication protocol.
Described master cpu utilizes the external SIM storage card of SIM memory card interface, can upgrade by various system configuration parameters and algorithm routine module that the SIM storage card is deposited.
Described new algorithm program module can be deposited card by SlM and be downloaded to the renewal that master cpu is finished algorithm routine.
The system configuration parameter that described memory stores sets in advance and algorithm routine module.
Described the first crystal oscillator, the first reset chip provide stable, accurate frequency of oscillation for master cpu and prevent that master cpu from sending false command, execution error operation.
Described the second crystal oscillator, the second reset chip provide stable, accurate frequency of oscillation and prevent that association from processing CPU and sending false command, execution error operation for association processes CPU.
Another aspect of the present invention provides a kind of dual-cpu structure Intelligent wire wound motor to advance the phase compensating control method, and the method may further comprise the steps:
(1) turn on the power switch, master cpu reads parameter preset and carries out initialization, and master cpu is converted to the digital quantity instruction to the real-time ac signal that mould/number conversion circuit sends system's operation.
(2) mould/number conversion circuit connects real-time ac signal with system operation and is converted to digital quantity and transfers to master cpu.
(3) the master cpu acquisition system is moved electric parameters and is carried out the calculating of electrical quantity and control algolithm, obtains thyristor delay angle pulse signal and output.
(4) association processes CPU by the thyristor delay angle pulse signal result of calculation of input/output interface termination receipts master cpu output and exports satisfactory trigger impulse.
(5) the CPLD logic control circuit receives association and processes the CPU start pulse signal, standardizes to process to output to thyristor by the input/output interface end.
Compared with prior art, beneficial effect of the present invention is:
Adopt the controller system of biplate machine structure, cooperated CPLD logic controller circuit, satisfied real-time calculating and the rapidity requirement of controlling in real time.Complicated control algolithm and real-time pulse trigger control task and are born by master cpu and the processing CPU of association respectively, intelligent control algorithm is separated with in real time hardware signal control, avoided the single CPU structural burden heavy, Software for Design is difficult to satisfy algorithm and calculates the shortcoming of controlling with real-time hardware signal, increase LCD panel and keyboard interaction interface, thereby realized high-intelligentization, high stability, high reliability, distributed control and the high accuracy control purpose of motor frequency change controller.Can carry out in real time the renewal of system configuration parameter and algorithm routine module by the SIM memory card interface, to adapt to different model motor and various complex work environment, save production cost.
Description of drawings
Fig. 1 is the structured flowchart of the embodiment of the invention;
Fig. 2 is the structural representation of the master cpu of the embodiment of the invention;
Fig. 3 is the structural representation that the association of the embodiment of the invention processes CPU;
Fig. 4 is the structural representation of the CPLD logic control circuit of the embodiment of the invention;
Fig. 5 is the memory construction schematic diagram of the embodiment of the invention;
Fig. 6 is the structural representation of the mould/number conversion circuit of the embodiment of the invention;
Fig. 7 is the structural representation of the input/output interface end of the embodiment of the invention;
Wherein, sequence number is as follows among the figure: 1-master cpu, 2-CPLD logic control circuit, 3-association process CPU, 4-input/output interface end, 5-mould/number conversion circuit, 6-SIM memory card interface, 7-memory, 8-the first crystal oscillator, 9-the first reset chip, 10-the second crystal oscillator, 11-the second reset chip, 12-external equipment.
Embodiment
The Intelligent wire wound motor that a kind of dual-cpu structure is provided of the present invention is advanced the phase compensating controller and control method elaborates below in conjunction with specific embodiment:
As shown in Figure 1, the Intelligent wire wound motor of dual-cpu structure advances the phase compensating controller, comprises that master cpu 1, CPLD logic control circuit 2, association process CPU3, input/output interface end 4, mould/number conversion circuit 5, SIM memory card interface 6, memory circuitry 7, the first crystal oscillator 8, the first reset chip 9, the second reset chip 10, the second crystal oscillator 11 and external equipment 12; CPLD logic control circuit 2, input/output interface end 4, mould/number conversion circuit 5, SIM memory card interface 6, memory circuitry 7, the first crystal oscillator 8 and the reset chip 9 of being connected all are connected with master cpu 1; Mould/number conversion circuit 5 connects input/output interface end 4; CPLD logic control circuit 2 connects input/output interface end 4 and association processes CPU3; Input/output interface end 4, the second reset chip 10 and the crystal oscillator equal 11 of being connected are processed CPU3 with association and are connected; External equipment 12 connects I/O end 4.
Further shown in Fig. 2-7, master cpu 1 reads parameter preset and carries out initialization; The real-time ac signal that mould/1 instruction of number conversion circuit 5 reception master cpus moves system is converted to digital quantity and transfers to master cpu 1; Master cpu 1 acquisition system operation electric parameters is also carried out the calculating of electrical quantity and control algolithm, obtains thyristor delay angle pulse signal and output; Master cpu 1 and association process CPU2 by realizing Real time data share with the cooperation of CPLD logic control circuit 3 interfaces and communicate by letter, and LCD panel, keyboard connect input/output interface end 4 to be processed CPU3 by CPLD logical circuit 2 with master cpu 1 and association and carry out interaction; Association processes CPU3 and receives the thyristor delay angle pulse signal result of calculation of master cpu 1 output and export satisfactory trigger impulse by input/output interface end 4; CPLD logic control circuit 2 receives association and processes the CPU3 start pulse signal, standardizes to process by 4 distribution of input/output interface end to output to accurately thyristor, and regulating electric machine stator voltage and revolutional slip are finished the requirement of continuous adjusting reactive power.
Master cpu 1 is responsible for that control algolithm is processed, the adjustment of mould/number conversion circuit control, order parameter and setting and cooperate with CPLD logical circuit 2 interfaces, finishes human-computer interaction by LCD panel and keyboard; Master cpu 1 is provided with standard serial port and built-in communication protocol, can realize distributed remote control, LCD panel real-time display system operation operating state, utilization can in time be carried out the eliminating of fault to the supervision of LCD panel, improves system's Operation safety and reduce the later stage to cause the expenditures for maintenance that causes behind the major break down.
Master cpu 1 utilizes SIM memory card interface 6 external SIM storage cards, can upgrade by various system configuration parameters and algorithm routine module that the SlM storage card is deposited.
The new algorithm program module can be deposited card by SIM and be downloaded to the renewal that master cpu 1 is finished algorithm routine.
System configuration parameter and algorithm routine module that memory 7 storages set in advance.
The first crystal oscillator 8, the first reset chip 9 provide stable, accurate frequency of oscillation for master cpu 1 and prevent that master cpu 1 from sending false command, execution error operation.
The second crystal oscillator 10, the second reset chip 11 provide stable, accurate frequency of oscillation and prevent that association from processing CPU3 and sending false command, execution error operation for association processes CPU3.
Further, the method can be advanced by the Intelligent wire wound motor of above-mentioned dual-cpu structure the phase compensating controller and realize, may further comprise the steps:
(1) turn on the power switch, give system power supply, master cpu 1 reads parameter preset and carries out initialization, and master cpu 1 is converted to the digital quantity instruction to the real-time ac signal that mould/number conversion circuit 5 sends system's operation.
(2) mould/number conversion circuit 5 is converted to digital quantity with the real-time ac signal of system operation and transfers to master cpu 1.
(3) master cpu 1 acquisition system is moved electric parameters and is carried out the calculating of electrical quantity and control algolithm, obtains thyristor delay angle pulse signal and output.
(4) association processes CPU3 by the thyristor delay angle pulse signal result of calculation of input/output interface end 4 reception master cpus 1 output and exports satisfactory trigger impulse.
(5) CPLD logic control circuit 2 receives association and processes the CPU3 start pulse signal, standardizes to process to output to thyristor by input/output interface end 4.
Following table forms pin annexation between the device for each:
| Device name | Pin numbering | The place accompanying drawing number | The device name that links to each other | Pin numbering | The place accompanying drawing number |
| Master cpu 1 | 1 | Fig. 2 | I/O end interface 4 | A15 | Fig. 7 |
| Master cpu 1 | 4 | Fig. 2 | I/O end interface 4 | B30 | Fig. 7 |
| Master cpu 1 | 1 | Fig. 2 | Master cpu 1 | 2 | Fig. 2 |
| Master cpu 1 | 12 | Fig. 2 | Master cpu 1 | 3 | Fig. 2 |
| Master cpu 1 | 23 | Fig. 2 | Master cpu 1 | 4 | Fig. 2 |
| Master cpu 1 | 34 | Fig. 2 | Master cpu 1 | 5 | Fig. 2 |
| Master cpu 1 | 11 | Fig. 2 | I/O end interface 4 | B7 | Fig. 7 |
| Master cpu 1 | 13 | Fig. 2 | I/O end interface 4 | B8 | Fig. 7 |
| Master cpu 1 | 15 | Fig. 2 | SIM |
20 | Fig. 6 |
| Master cpu 1 | 17 | Fig. 2 | SIM |
21 | Fig. 6 |
| Master cpu 1 | 18 | Fig. 2 | CPLD |
21 | Fig. 4 |
| Master cpu 1 | 19 | Fig. 2 | CPLD |
22 | Fig. 4 |
| Master cpu 1 | 9 | Fig. 2 | Memory 7 | 5 | Fig. 5 |
| Master cpu 1 | 6 | Fig. 2 | Memory 7 | 6 | Fig. 5 |
| Master cpu 1 | 2 | Fig. 2 | SIM |
19 | Fig. 6 |
| Master cpu 1 | 3 | Fig. 2 | SIM |
7 | Fig. 6 |
| Master cpu 1 | 4 | Fig. 2 | SIM |
6 | Fig. 6 |
| Master cpu 1 | 5 | Fig. 2 | SIM |
23 | Fig. 6 |
| Master cpu 1 | 43 | Fig. 2 | CPLD |
13 | Fig. 4 |
| Master cpu 1 | 42 | Fig. 2 | CPLD |
14 | Fig. 4 |
| Master cpu 1 | 41 | Fig. 2 | CPLD |
15 | Fig. 4 |
| Master cpu 1 | 40 | Fig. 2 | CPLD |
16 | Fig. 4 |
| Master cpu 1 | 39 | Fig. 2 | CPLD |
17 | Fig. 4 |
| Master cpu 1 | 38 | Fig. 2 | CPLD |
18 | Fig. 4 |
| Master cpu 1 | 37 | Fig. 2 | CPLD |
19 | Fig. 4 |
| Master cpu 1 | 36 | Fig. 2 | CPLD |
20 | Fig. 4 |
| Master cpu 1 | 2 | Fig. 2 | Memory 7 | 10 | Fig. 5 |
| Master cpu 1 | 5 | Fig. 2 | Memory 7 | 9 | Fig. 5 |
| Master cpu 1 | 6 | Fig. 2 | Memory 7 | 8 | Fig. 5 |
| Master cpu 1 | 9 | Fig. 2 | Memory 7 | 7 | Fig. 5 |
| Master cpu 1 | 12 | Fig. 2 | Memory 7 | 6 | Fig. 5 |
| Master cpu 1 | 15 | Fig. 2 | Memory 7 | 5 | Fig. 5 |
| Master cpu 1 | 16 | Fig. 2 | Memory 7 | 4 | Fig. 5 |
| Master cpu 1 | 19 | Fig. 2 | Memory 7 | 3 | Fig. 5 |
| Master cpu 1 | 24 | Fig. 2 | Memory 7 | 25 | Fig. 5 |
| Master cpu 1 | 25 | Fig. 2 | Memory 7 | 24 | Fig. 5 |
| Master cpu 1 | 26 | Fig. 2 | Memory 7 | 21 | Fig. 5 |
| Master cpu 1 | 27 | Fig. 2 | Memory 7 | 23 | Fig. 5 |
| Master cpu 1 | 28 | Fig. 2 | Memory 7 | 2 | Fig. 5 |
| Master cpu 1 | 29 | Fig. 2 | Memory 7 | 26 | Fig. 5 |
| Master cpu 1 | 30 | Fig. 2 | Memory 7 | 1 | Fig. 5 |
| Master cpu 1 | 31 | Fig. 2 | CPLD |
24 | Fig. 4 |
| Association processes CPU3 | 1 | Fig. 3 | I/O end interface 4 | B15 | Fig. 7 |
| Association processes CPU3 | 4 | Fig. 3 | I/O end interface 4 | B30 | Fig. 7 |
| Association processes |
15 | Fig. 3 | I/O end interface 4 | A7 | Fig. 7 |
| |
12 | Fig. 3 | I/O end interface 4 | A8 | Fig. 7 |
| Association processes CPU3 | 1 | Fig. 3 | I/O end interface 4 | A9 | Fig. 7 |
| Association processes CPU3 | 11 | Fig. 3 | I/O end interface 4 | B9 | Fig. 7 |
| |
13 | Fig. 3 | I/O end interface 4 | B10 | Fig. 7 |
| Association processes CPU3 | 14 | Fig. 3 | I/O end interface 4 | A10 | Fig. 7 |
| |
17 | Fig. 3 | CPLD |
11 | Fig. 4 |
| Association processes CPU3 | 18 | Fig. 3 | CPLD |
25 | Fig. 4 |
| Association processes |
19 | Fig. 3 | CPLD |
29 | Fig. 4 |
| Association processes CPU3 | 24 | Fig. 3 | I/O end interface 4 | A11 | Fig. 7 |
| Association processes CPU3 | 25 | Fig. 3 | I/O end interface 4 | A12 | Fig. 7 |
| Association processes CPU3 | 26 | Fig. 3 | I/O end interface 4 | A13 | Fig. 7 |
| Association processes CPU3 | 27 | Fig. 3 | I/O end interface 4 | A14 | Fig. 7 |
| Association processes CPU3 | 28 | Fig. 3 | I/O end interface 4 | B11 | Fig. 7 |
| Association processes |
29 | Fig. 3 | I/O end interface 4 | B12 | Fig. 7 |
| Association processes |
30 | Fig. 3 | I/O end interface 4 | B13 | Fig. 7 |
| Association processes CPU3 | 31 | Fig. 3 | I/O end interface 4 | B14 | Fig. 7 |
| Association processes CPU3 | 4 | Fig. 3 | CPLD |
92 | Fig. 4 |
| Association processes CPU3 | 5 | Fig. 3 | CPLD |
93 | Fig. 4 |
| Association processes |
6 | Fig. 3 | CPLD |
94 | Fig. 4 |
| Association processes CPU3 | 7 | Fig. 3 | CPLD |
95 | Fig. 4 |
| Association processes CPU3 | 8 | Fig. 3 | CPLD |
96 | Fig. 4 |
| Association processes CPU3 | 9 | Fig. 3 | CPLD |
97 | Fig. 4 |
| |
2 | Fig. 3 | CPLD |
98 | Fig. 4 |
| |
3 | Fig. 3 | CPLD |
99 | Fig. 4 |
| |
43 | Fig. 3 | CPLD |
1 | Fig. 4 |
| Association processes CPU3 | 42 | Fig. 3 | CPLD |
5 | Fig. 4 |
| Association processes CPU3 | 41 | Fig. 3 | CPLD |
6 | Fig. 4 |
| |
40 | Fig. 3 | CPLD |
3 | Fig. 4 |
| Association processes CPU3 | 39 | Fig. 3 | CPLD |
4 | Fig. 4 |
| Association processes CPU3 | 38 | Fig. 3 | CPLD |
8 | Fig. 4 |
| Association processes CPU3 | 37 | Fig. 3 | CPLD |
9 | Fig. 4 |
| Association processes CPU3 | 36 | Fig. 3 | CPLD |
10 | Fig. 4 |
| CPLD |
12 | Fig. 4 | CPLD |
20 | Fig. 5 |
| CPLD |
26 | Fig. 4 | CPLD |
27 | Fig. 4 |
| CPLD |
26 | Fig. 4 | CPLD |
30 | Fig. 4 |
| CPLD |
31 | Fig. 4 | CPLD |
32 | Fig. 4 |
| CPLD |
31 | Fig. 4 | CPLD |
34 | Fig. 4 |
| CPLD |
35 | Fig. 4 | CPLD |
36 | Fig. 4 |
| CPLD |
35 | Fig. 4 | CPLD |
37 | Fig. 4 |
| CPLD |
38 | Fig. 4 | CPLD |
39 | Fig. 4 |
| CPLD |
38 | Fig. 4 | CPLD |
41 | Fig. 4 |
| CPLD |
42 | Fig. 4 | CPLD |
43 | Fig. 4 |
| CPLD |
42 | Fig. 4 | CPLD |
44 | Fig. 4 |
| CPLD |
45 | Fig. 4 | CPLD |
48 | Fig. 4 |
| CPLD |
45 | Fig. 4 | CPLD |
51 | Fig. 4 |
| CPLD |
83 | Fig. 4 | I/O end interface 4 | B16 | Fig. 7 |
| CPLD |
81 | Fig. 4 | I/O end interface 4 | B17 | Fig. 7 |
| CPLD |
79 | Fig. 4 | I/O end interface 4 | B18 | Fig. 7 |
| CPLD |
76 | Fig. 4 | I/O end interface 4 | B19 | Fig. 7 |
| CPLD |
87 | Fig. 4 | I/O end interface 4 | A7 | Fig. 7 |
| CPLD |
88 | Fig. 4 | I/O end interface 4 | A8 | Fig. 7 |
| CPLD |
89 | Fig. 4 | I/O end interface 4 | A9 | Fig. 7 |
| CPLD |
78 | Fig. 4 | I/O end interface 4 | A19 | Fig. 7 |
| CPLD |
80 | Fig. 4 | I/O end interface 4 | A18 | Fig. 7 |
| CPLD |
82 | Fig. 4 | I/O end interface 4 | A17 | Fig. 7 |
| CPLD |
84 | Fig. 4 | I/O end interface 4 | 1 | Fig. 7 |
| CPLD |
66 | Fig. 4 | I/O end interface 4 | A24 | Fig. 7 |
| CPLD |
65 | Fig. 4 | I/O end interface 4 | B24 | Fig. 7 |
| CPLD |
63 | Fig. 4 | I/O end interface 4 | A25 | Fig. 7 |
| CPLD |
62 | Fig. 4 | I/O end interface 4 | B25 | Fig. 7 |
| CPLD |
61 | Fig. 4 | I/O end interface 4 | A26 | Fig. 7 |
| CPLD |
60 | Fig. 4 | I/O end interface 4 | B26 | Fig. 7 |
| CPLD |
58 | Fig. 4 | I/O end interface 4 | A27 | Fig. 7 |
| CPLD |
57 | Fig. 4 | I/O end interface 4 | B27 | Fig. 7 |
| CPLD |
56 | Fig. 4 | I/O end interface 4 | A28 | Fig. 7 |
| CPLD |
55 | Fig. 4 | I/O end interface 4 | B28 | Fig. 7 |
| CPLD |
54 | Fig. 4 | I/O end interface 4 | A29 | Fig. 7 |
| CPLD |
52 | Fig. 4 | I/O end interface 4 | B29 | Fig. 7 |
| CPLD |
74 | Fig. 4 | I/O end interface 4 | A20 | Fig. 7 |
| CPLD |
72 | Fig. 4 | I/O end interface 4 | A21 | Fig. 7 |
| CPLD |
69 | Fig. 4 | I/O end interface 4 | A22 | Fig. 7 |
| CPLD |
67 | Fig. 4 | I/O end interface 4 | A23 | Fig. 7 |
| CPLD |
75 | Fig. 4 | I/O end interface 4 | B20 | Fig. 7 |
| CPLD |
73 | Fig. 4 | I/O end interface 4 | B21 | Fig. 7 |
| CPLD |
70 | Fig. 4 | I/O end interface 4 | B22 | Fig. 7 |
| CPLD |
68 | Fig. 4 | I/O end interface 4 | B23 | Fig. 7 |
| CPLD |
91 | Fig. 4 | SIM |
22 | Fig. 6 |
| CPLD |
21 | Fig. 4 | Memory 7 | 27 | Fig. 5 |
| CPLD |
22 | Fig. 4 | Memory 7 | 22 | Fig. 5 |
| Memory 7 | 11 | Fig. 5 | CPLD |
13 | Fig. 4 |
| Memory 7 | 12 | Fig. 5 | CPLD |
14 | Fig. 4 |
| Memory 7 | 13 | Fig. 5 | CPLD |
15 | Fig. 4 |
| Memory 7 | 15 | Fig. 5 | CPLD |
16 | Fig. 4 |
| Memory 7 | 16 | Fig. 5 | CPLD |
17 | Fig. 4 |
| Memory 7 | 17 | Fig. 5 | CPLD |
18 | Fig. 4 |
| Memory 7 | 18 | Fig. 5 | CPLD |
19 | Fig. 4 |
| Memory 7 | 19 | Fig. 5 | CPLD |
20 | Fig. 4 |
| SIM |
17 | Fig. 6 | I/O end interface 4 | A30 | Fig. 7 |
| SIM |
1 | Fig. 6 | I/O end interface 4 | A31 | Fig. 7 |
| SIM |
1 | Fig. 6 | I/O end interface 4 | A32 | Fig. 7 |
| SIM |
1 | Fig. 6 | I/O end interface 4 | B31 | Fig. 7 |
| SIM |
1 | Fig. 6 | I/O end interface 4 | B32 | Fig. 7 |
| SIM |
5 | Fig. 6 | Master cpu 1 | 6 | Fig. 2 |
The above only is preferred implementation of the present invention, should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention, can also make some improvement, and these improvement also should be considered as protection scope of the present invention.
Claims (10)
1. the Intelligent wire wound motor of a dual-cpu structure advances the phase compensating controller, it is characterized in that: comprise that master cpu (1), CPLD logic control circuit (2), association process CPU(3), input/output interface end (4), mould/number conversion circuit (5), SIM memory card interface (6), memory circuitry (7), the first crystal oscillator (8), the first reset chip (9), the second reset chip (10), the second crystal oscillator (11) and external equipment (12); Described CPLD logic control circuit (2), input/output interface end (4), mould/number conversion circuit (5), SIM memory card interface (6), memory circuitry (7), the first crystal oscillator (8) and the reset chip (9) of being connected all are connected with master cpu (1); Described mould/number conversion circuit (5) connects input/output interface end (4); Described CPLD logic control circuit (2) connects input/output interface end (4) and association processes CPU(3); Described input/output interface end (4), the second reset chip (10) and the crystal oscillator of being connected all (11) are processed CPU(3 with association) be connected; Described external equipment (12) connects input/output interface end (4).
2. the Intelligent wire wound motor according to dual-cpu structure as claimed in claim 1 advances the phase compensating controller, it is characterized in that: described external equipment (12) comprises power supply, LCD panel and keyboard.
3. the Intelligent wire wound motor according to dual-cpu structure as claimed in claim 1 advances the phase compensating controller, it is characterized in that: described master cpu (1) reads parameter preset and carries out initialization; The real-time ac signal that described mould/instruction of number conversion circuit (5) reception master cpu (1) moves system is converted to digital quantity and transfers to master cpu (1); Described master cpu (1) acquisition system operation electric parameters is also carried out the calculating of electrical quantity and control algolithm, obtains thyristor delay angle pulse signal and output; Described master cpu (1) and association process CPU(3) by realizing Real time data share with the cooperation of CPLD logic control circuit (2) interface and communicate by letter, LCD panel, keyboard connect the input/output interface end by CPLD logical circuit (2) with master cpu (1) and assist processing CPU(3) carry out interaction; Described association processes CPU(1) receive the thyristor delay angle pulse signal result of calculation of master cpu (1) output and export satisfactory trigger impulse by input/output interface end (4); Described CPLD logic control circuit (2) receives association and processes CPU(3) start pulse signal, standardizing to process outputs to thyristor by input/output interface end (4).
4. the Intelligent wire wound motor according to dual-cpu structure as claimed in claim 1 advances the phase compensating controller, it is characterized in that: described master cpu (1) is responsible for that control algolithm is processed, mould/number circuit conversion is controlled, the adjustment of order parameter and setting and cooperate with CPLD logical circuit (2) interface, finish human-computer interaction by LCD panel and keyboard, wherein master cpu (1) is provided with the standard serial port, built-in communication protocol.
5. the Intelligent wire wound motor according to dual-cpu structure as claimed in claim 1 advances the phase compensating controller, it is characterized in that: described master cpu (1) utilizes the external SIM storage card of SIM memory card interface (6), can upgrade by various system configuration parameters and algorithm routine module that the SIM storage card is deposited.
6. the Intelligent wire wound motor according to dual-cpu structure as claimed in claim 1 advances the phase compensating controller, it is characterized in that: described new algorithm program module can be deposited card by SIM and be downloaded to the renewal that master cpu (1) is finished algorithm routine.
7. the Intelligent wire wound motor according to dual-cpu structure as claimed in claim 1 advances the phase compensating controller, it is characterized in that: system configuration parameter and algorithm routine module that described memory (7) storage sets in advance.
8. the Intelligent wire wound motor according to dual-cpu structure as claimed in claim 1 advances the phase compensating controller, it is characterized in that: described the first crystal oscillator, the first reset chip are that master cpu (1) provides stable, accurate frequency of oscillation and prevents that master cpu (1) from sending false command, execution error operation.
9. the Intelligent wire wound motor according to dual-cpu structure as claimed in claim 1 advances the phase compensating controller, it is characterized in that: described the second crystal oscillator, the second reset chip are processed CPU(3 for association) stable, accurate frequency of oscillation is provided and prevents that association from processing CPU(3) false command, execution error operation sent.
10. dual-cpu structure Intelligent wire wound motor advances the phase compensating control method, it is characterized in that, may further comprise the steps:
(1) turn on the power switch, master cpu (1) reads parameter preset and carries out initialization, and master cpu (1) is converted to the digital quantity instruction to the real-time ac signal that mould/number conversion circuit (5) sends system's operation;
(2) mould/number conversion circuit (5) is converted to digital quantity with the real-time ac signal of system operation and transfers to master cpu (1);
(3) master cpu (1) acquisition system is moved electric parameters and is carried out the calculating of electrical quantity and control algolithm, obtains thyristor delay angle pulse signal and output;
(4) association processes CPU(3) receive the thyristor delay angle pulse signal result of calculation of master cpu (1) output and export satisfactory trigger impulse by input/output interface end (4);
(5) CPLD logic control circuit (2) receives association and processes CPU(3) start pulse signal, standardizing to process outputs to thyristor by input/output interface end (4).
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012105641830A CN103023423A (en) | 2012-12-21 | 2012-12-21 | Advanced phase compensation control unit and method for double-CPU (central processing unit) intelligent wound-rotor motor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105641830A CN103023423A (en) | 2012-12-21 | 2012-12-21 | Advanced phase compensation control unit and method for double-CPU (central processing unit) intelligent wound-rotor motor |
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| JPS55125086A (en) * | 1979-03-20 | 1980-09-26 | Hitachi Ltd | Motor controlling device |
| CN200953475Y (en) * | 2006-09-25 | 2007-09-26 | 襄樊万洲电气集团有限公司 | Variable load phase modifier |
| CN101626215A (en) * | 2009-05-27 | 2010-01-13 | 株洲变流技术国家工程研究中心有限公司 | Soft start and local compensation method of asynchronous electric motor and device thereof |
| CN101667025A (en) * | 2009-09-30 | 2010-03-10 | 航天科工卫星技术有限公司 | Real-time monitoring circuit aiming to carrier device |
| CN203206175U (en) * | 2012-12-21 | 2013-09-18 | 东南大学 | Intelligent wound-rotor type motor phase advancement compensation controller based on double-CPU structure |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55125086A (en) * | 1979-03-20 | 1980-09-26 | Hitachi Ltd | Motor controlling device |
| CN200953475Y (en) * | 2006-09-25 | 2007-09-26 | 襄樊万洲电气集团有限公司 | Variable load phase modifier |
| CN101626215A (en) * | 2009-05-27 | 2010-01-13 | 株洲变流技术国家工程研究中心有限公司 | Soft start and local compensation method of asynchronous electric motor and device thereof |
| CN101667025A (en) * | 2009-09-30 | 2010-03-10 | 航天科工卫星技术有限公司 | Real-time monitoring circuit aiming to carrier device |
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Application publication date: 20130403 |