CN103022045A - Non-volatile memory with P+ single polycrystal architecture and having PMOS (P-channel metal oxide semiconductor) transistor without light doped area and preparation method of non-volatile memory - Google Patents
Non-volatile memory with P+ single polycrystal architecture and having PMOS (P-channel metal oxide semiconductor) transistor without light doped area and preparation method of non-volatile memory Download PDFInfo
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Abstract
The invention relates to a non-volatile memory with a P+ single polycrystal architecture and having a PMOS (P-channel metal oxide semiconductor) transistor without a light doped area and a preparation method of the non-volatile memory. The non-volatile memory comprises a semiconductor substrate and a memory cell which comprises a control capacitor and the PMOS transistor without the light doped area. A floating gate electrode is arranged on a gate dielectric layer which is deposited on the surface of the semiconductor substrate, the floating gate electrode covers and penetrates through the corresponding gate dielectric layer above the control capacitor and the PMOS transistor without the light doped area, and side protection layers are deposited on two sides of the floating gate electrode. The PMOS transistor without the light doped area comprises a first N-type region, a P-type source region and a P-type drain region, and the control capacitor comprises a second P-type region, a first P-type doped region and a second P-type doped region. The non-volatile memory is compact in structure and compatible with the CMOS (complementary metal oxide semiconductor) process, chip cost is reduced, and safety and reliability in storage are improved.
Description
Technical field
The present invention relates to a kind of non-volatility memory and preparation method thereof, especially a kind of P+ of having and PMOS transistor do not have the non-volatility memory and preparation method thereof of the single polycrystalline architecture of lightly doped region, belong to the technical field of integrated circuit.
Background technology
Use for SOC (system on a chip) (SoC), it is that many functional blocks are integrated in the integrated circuit.The most frequently used SOC (system on a chip) comprises the logical block of a microprocessor or microcontroller, static RAM (SRAM) module, non-volatility memory and various specific functions.Yet, the process in traditional non-volatility memory, this uses folded grid or splitting bar memory cell usually, and is incompatible with traditional logic process.
Non-volatility memory (NVM) technique and traditional logic process are different.Non-volatility memory (NVM) technique and traditional logic process are combined, and will make technique become a more complicated and expensive combination; Because the typical usage of nonvolatile memory that SoC uses is little at the chip size that is related to integral body, therefore this way is worthless.Simultaneously, because the operation principle of existing non-volatility memory affects the reliability of using so that data writing is lost easily.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, non-volatility memory of the single polycrystalline architecture that a kind of P+ of having and PMOS transistor do not have lightly doped region and preparation method thereof is provided, its PMOS transistor does not have lightly doped region, make write hot electron the time lower voltage, designability when improving design circuit, its compact overall structure, can with the CMOS process compatible, reduce chip cost, improve the security reliability of storage.
According to technical scheme provided by the invention, the described P+ of having and PMOS transistor do not have the non-volatility memory of the single polycrystalline architecture of lightly doped region, comprise semiconductor substrate; Top in the described semiconductor substrate is provided with some memory body cells for storage, and described memory body cell comprises does not have the PMOS of lightly doped region transistor and control capacitance; Mutually isolate by the field areas of dielectric in the semiconductor substrate between the described PMOS transistor that does not have a lightly doped region and control capacitance; Be deposited with gate dielectric layer on the surface of semiconductor substrate, described gate dielectric layer is provided with floating gate electrode, described floating gate electrode covers and runs through does not have gate dielectric layer corresponding to the PMOS of lightly doped region transistor and control capacitance top, the both sides of floating gate electrode are deposited with the lateral protection layer, and the lateral protection layer covers the sidewall of floating gate electrode; Do not have the PMOS transistor of lightly doped region to comprise the first N-type zone and be positioned at P type source area and the P type drain region of described the first N-type zone internal upper part, control capacitance comprises the second p type island region territory and is positioned at a P type doped region and the 2nd P type doped region of described the second p type island region territory internal upper part; The one P type doped region, the 2nd P type doped region, P type source area and P type drain region are corresponding with the floating gate electrode of top, and contact with corresponding gate dielectric layer and field areas of dielectric respectively.
The material of described semiconductor substrate comprises silicon, and semiconductor substrate is P conduction type substrate or N conduction type substrate.
When described semiconductor substrate was P conduction type substrate, described do not have the PMOS transistor of lightly doped region isolated with the P-type conduction type of substrate by the first N-type zone of the zone of the second N-type in the P-type conduction type of substrate and top, the second N-type zone.Described control capacitance access transistor is isolated by the second p type island region territory and the P-type conduction type of substrate of the zone of the second N-type in the P-type conduction type of substrate and top, the second N-type zone.
A described P type doped region comprises that a P type heavily doped region reaches and the lateral protection layer, and a P type heavily doped region contacts with the field areas of dielectric.
Described the 2nd P type doped region comprises the 2nd P type heavily doped region and in the 2nd corresponding P type lightly doped region of lateral protection layer, the 2nd P type heavily doped region contacts with the field areas of dielectric after extending from the end of the 2nd P type lightly doped region.
Described floating gate electrode comprise conductive polycrystalline silicon.The material of described gate dielectric layer comprises silicon dioxide; Described lateral protection layer is silicon nitride or silicon dioxide.
A kind of P+ of having and PMOS transistor do not have the non-volatility memory and preparation method thereof of the single polycrystalline architecture of lightly doped region, and described preparation method comprises the steps:
A, provide semiconductor substrate, described semiconductor substrate comprises the first interarea and the second interarea;
B, growth obtains the field areas of dielectric in semiconductor substrate; The first interarea at semiconductor substrate carries out required barrier layer deposition, barrier etch and autoregistration Implantation, to form required the first N-type zone, the second N-type zone, the second p type island region territory in semiconductor substrate;
C, on the first interarea corresponding to above-mentioned semiconductor substrate the deposit gate dielectric layer, described gate dielectric layer covers the first interarea of semiconductor substrate;
D, on the first interarea of above-mentioned semiconductor substrate the deposit floating gate electrode, described floating gate electrode is covered on the gate dielectric layer and runs through on gate dielectric layer corresponding to the second p type island region territory, the first N-type zone top;
E, on above-mentioned gate dielectric layer deposit the 4th barrier layer, and optionally shelter and etching the 4th barrier layer, remove the first N-type zone, corresponding the 4th barrier layer that covers floating gate electrode, top, the second p type island region territory;
F, the p type impurity ion is injected in autoregistration above above-mentioned the 4th barrier layer, and the top in the second p type island region territory obtains a P type lightly doped region and the 2nd P type lightly doped region;
G, remove above-mentioned the 4th barrier layer, and on the first interarea deposit lateral protection material, form the lateral protection layer with the both sides at floating gate electrode;
H, on above-mentioned the first interarea deposit the 5th barrier layer, and optionally shelter and etching the 5th barrier layer the 5th barrier layer that covers to remove the second p type island region territory, the corresponding deposit in top, the first N-type zone;
I, the p type impurity ion is injected in autoregistration again above above-mentioned the 5th barrier layer, top in the second p type island region territory obtains a P type heavily doped region and the 2nd P type heavily doped region, and the top in the first N-type zone obtains the 3rd P type heavily doped region and the 4th P type heavily doped region;
The 5th barrier layer on j, removal the first interarea.
In described step a, when semiconductor substrate was P conduction type substrate, described step b comprised
B1, on the first interarea of P conduction type substrate deposit the first barrier layer, and optionally shelter and described the first barrier layer of etching, the N-type foreign ion is injected in autoregistration above the first barrier layer, to obtain the second N-type zone in semiconductor substrate;
B2, growth obtains the field areas of dielectric in semiconductor substrate;
B3, remove the first barrier layer on corresponding the first interarea of above-mentioned P conduction type substrate, and on the first interarea deposit the second barrier layer;
B4, optionally shelter and etching the second barrier layer, and the N-type foreign ion is injected in autoregistration above the second barrier layer, to form the first N-type zone in semiconductor substrate, the first N-type district is positioned at the top in the second N-type zone;
B5, remove the second barrier layer on corresponding the first interarea of above-mentioned P conduction type substrate, and on the first interarea deposit the 3rd barrier layer;
B6, optionally shelter and etching the 3rd barrier layer, and the p type impurity ion is injected in autoregistration above the 3rd barrier layer, above the second N-type zone, to form the second p type island region territory.
In described step a, when semiconductor substrate was N conduction type substrate, described step b comprised
S1, growth obtains the field areas of dielectric in semiconductor substrate;
S2, on the first interarea deposit the second barrier layer, and optionally shelter and etching the second barrier layer;
S3, the N-type foreign ion is injected in autoregistration above above-mentioned the second barrier layer, obtains required the first N-type zone with the top in N conduction type substrate;
S4, remove the second barrier layer on the first interarea, and on the first interarea deposit the 3rd barrier layer;
S5, optionally shelter and etching the 3rd barrier layer, and the p type impurity ion is injected in autoregistration above the 3rd barrier layer, in N conduction type substrate, to obtain the second p type island region territory.
Described the 4th barrier layer and the 5th barrier layer are silicon dioxide or silicon nitride.Described field areas of dielectric is silicon dioxide.
Field dielectric layer among described step b2 and the s1 is the transistorized electrode grid oxide layer of the I/O in the CMOS technique; The thickness of the transistorized electrode grid oxide layer of I/O in the described CMOS technique is 7 nanometers normally.
Advantage of the present invention: at least one memory body cell is set in the semiconductor substrate, the memory body cell comprises does not have the PMOS of lightly doped region transistor and control capacitance, does not have the PMOS transistor of lightly doped region and control capacitance mutually to isolate by the field areas of dielectric; On the gate dielectric layer of semiconductor substrate floating gate electrode is set, described floating gate electrode connects to run through does not have the PMOS of lightly doped region transistor and control capacitance; When floating gate electrode and do not have the PMOS transistorized P type source area of lightly doped region and P type drain region between voltage difference be when voltage difference is analog value between analog value and P type source area and P type drain region, can be to data writing in the floating gate electrode; Or with the data erase in the floating gate electrode, flow through the transistorized electric current of the PMOS that does not have lightly doped region by detection and can know the residing programming write state of floating gate electrode or erase status, the somatic preparation flow of whole memory can be compatible mutually with existing CMOS logic process, compact conformation, can cut down finished cost, improve the adaptability of nonvolatile memory and CMOS logical circuit; The one P type doped region and the 2nd P type doped region of the P type source area of the PMOS transistor internal upper part by there not being lightly doped region and P type drain region, control capacitance internal upper part, can so that data writing keeps is more of a specified duration, improve the safety and reliability of non-volatility memory.Its PMOS transistor does not have lightly doped region, make write hot electron the time lower voltage, the designability when improving design circuit.
Description of drawings
Fig. 1 is the structural representation of the embodiment of the invention 1.
Fig. 2 is the structural representation of the embodiment of the invention 2.
Fig. 3 ~ Figure 13 is the implementation technique cutaway view of the embodiment of the invention 1, wherein:
Fig. 3 is the cutaway view of P conduction type substrate of the present invention.
Fig. 4 is the cutaway view that obtains behind the second N-type zone.
Fig. 5 is the cutaway view that obtains after the areas of dielectric of field.
Fig. 6 is the cutaway view that obtains behind the first N-type zone and the 3rd N-type zone.
Fig. 7 is the cutaway view that obtains behind the second p type island region territory.
Fig. 8 is the cutaway view that obtains behind the gate dielectric layer.
Fig. 9 is the cutaway view that obtains behind the floating gate electrode.
Figure 10 is that the cutaway view after the P foreign ion obtains lightly doped region is injected in autoregistration.
Figure 11 is the cutaway view that obtains behind the lateral protection layer.
Figure 12 is that the cutaway view after the P foreign ion obtains heavily doped region is injected in autoregistration.
Figure 13 is the cutaway view behind removal the 5th barrier layer.
Figure 14 ~ Figure 23 is the implementation technique cutaway view of the embodiment of the invention 2, wherein:
Figure 14 is the cutaway view of N conduction type substrate of the present invention.
Figure 15 is the cutaway view that obtains after the areas of dielectric of field.
Figure 16 is the cutaway view that obtains behind the first N-type zone and the second N-type zone.
Figure 17 is the cutaway view that obtains behind the second p type island region territory.
Figure 18 is the cutaway view that obtains behind the gate dielectric layer.
Figure 19 is the cutaway view that obtains behind the floating gate electrode.
Figure 20 is that the cutaway view after the P foreign ion obtains lightly doped region is injected in autoregistration.
Figure 21 is the cutaway view that obtains behind the lateral protection layer.
Figure 22 is that the cutaway view after the P foreign ion obtains heavily doped region is injected in autoregistration.
Figure 23 is the cutaway view behind removal the 5th barrier layer.
Description of reference numerals: 200-memory body cell; 201-P conduction type substrate; 202-the first N-type zone; 203-the second N-type zone; 204-the 3rd N-type zone; 205-the second p type island region territory; 206-the one P type doped region; 207-the one P type heavily doped region; 208-the one P type lightly doped region; 209-the 2nd P type doped region; 210-does not have the PMOS transistor of lightly doped region; 211-the 2nd P type lightly doped region; 212-the 2nd P type heavily doped region; 213-P type source area; 214-field areas of dielectric; the 215-gate dielectric layer; the 216-floating gate electrode; 217-lateral protection layer; 219-the 3rd P type heavily doped region; the 220-control capacitance; 221-P type drain region; 223-the 4th P type heavily doped region; 232-the first interarea; 233-the second interarea; 234-the first barrier layer; 235-the second barrier layer; 236-the 3rd barrier layer; 237-the 4th barrier layer; 238-the 5th barrier layer and 239-N conduction type substrate.
Embodiment
The invention will be further described below in conjunction with concrete drawings and Examples.
Embodiment 1
Such as Fig. 1 with shown in Figure 13: for can be so that non-volatility memory and CMOS logic process be compatible mutually, simultaneously can be so that non-volatility memory can be stored the longer time, non-volatility memory comprises P conduction type substrate 201, and the material of P conduction type substrate 201 is silicon.Top in the P conduction type substrate 201 is provided with at least one memory body cell 200, described memory body cell 200 comprises does not have the PMOS of lightly doped region transistor 210 and control capacitance 220, deposit is coated with gate dielectric layer 215 on the surface of P conduction type substrate 201, described gate dielectric layer 215 covers the corresponding surface that forms memory body cell 200, does not have the PMOS transistor 210 of lightly doped region and 220 field areas of dielectric 214 of passing through in the P conduction type substrate 201 of control capacitance mutually to isolate.Be deposited with floating gate electrode 216 on the gate dielectric layer 215, described floating gate electrode 216 is covered on the gate dielectric layer 215, and run through to cover and do not have the PMOS transistor 210 of lightly doped region and the gate dielectric layer 215 of control capacitance 220 correspondences, thereby will there be the PMOS transistor 210 of lightly doped region and control capacitance 220 to interconnect cooperation.The both sides of floating gate electrode 216 are coated with lateral protection layer 217, and described lateral protection layer 217 covers the outer wall surface of floating gate electrode 216 correspondences.
The described PMOS transistor 210 that does not have a lightly doped region and control capacitance 220 by the outside the 3rd N-type zone 204 and the P conductivity type regions isolation in the second N-type zone 203 of below and the P conduction type substrate 201, the P conductive regions in the P conduction type substrate 201 form the first p type island region territory.The material of floating gate electrode 216 comprises conductive polycrystalline silicon, and gate dielectric layer 215 is silicon dioxide, and lateral protection layer 217 is silicon dioxide or silicon nitride; Field areas of dielectric 214 is silicon dioxide.
Described do not have the PMOS transistor 210 of lightly doped region to comprise the first N-type zone 202, tops in described the first N-type zone 202 are provided with symmetrical P type source area 213 and P type drain region 221, and described P type source area 213, P type drain region 221 contact with corresponding field areas of dielectric 214 and the gate dielectric layer 215 of top.P type source area 213 comprises the 3rd P type heavily doped region 219.P type drain region 221 comprises the 4th P type heavily doped region 223.The 3rd P type lightly doped region 218 and the 4th P type lightly doped region 222 are same manufacturing layer, and the 3rd P type heavily doped region 219 and the 4th P type heavily doped region 223 are same manufacturing layer.The 3rd P type lightly doped region 218 contacts with the 3rd P type heavily doped region 219, and contacts with field areas of dielectric 214 by the 3rd P type heavily doped region 219.
Control capacitance 220 comprises the second p type island region territory 205, and the top in described the second p type island region territory 205 is provided with a P type doped region 206 and the 2nd P type doped region 209; A described P type doped region 206 and the 2nd P type doped region 209 are symmetrically distributed in the second p type island region territory 205.The one P type doped region 206, the 2nd P type doped region 209 contact with corresponding field areas of dielectric 214 and gate dielectric layer 215.The one P type doped region 206 comprises a P type lightly doped region 208 and a P type heavily doped region 207; the one P type lightly doped region 208 contacts with field areas of dielectric 214 by a P type heavily doped region 207, and the extended distance of a P type lightly doped region 208 in the second p type island region territory 205 is consistent with the thickness of lateral protection layer 217.The 2nd P type doped region 209 comprises the 2nd P type lightly doped region 211 and the 2nd P type heavily doped region 212, described the 2nd P type lightly doped region 211 contacts with field areas of dielectric 214 by the 2nd P type heavily doped region 212, and the 2nd P type lightly doped region 211 arranges consistent with the distribution of a P type lightly doped region 208.205 in the second p type island region territory of floating gate electrode 216 and gate dielectric layer 215 and gate dielectric layer 215 belows forms capacitance structure, and namely control capacitance 220.
Can be to memory body cell 200 be carried out data writing, perhaps with the data erase in the memory body cell 200 by the PMOS transistor 210 that does not have lightly doped region; Can read storing data state in the memory body cell 200 by the PMOS transistor 210 that does not have lightly doped region, magnitude of voltage can be passed on the floating gate electrode 216 by control capacitance 220, realize the raceway groove of floating gate electrode 216 and PMOS transistor 210 or 202 magnitudes of voltage in the first N-type zone of PMOS transistor 210, can realize that according to corresponding magnitude of voltage data write, wipe and read operation.
Such as Fig. 3 ~ shown in Figure 13: the non-volatility memory of said structure can realize by following processing step, particularly:
A, provide P conduction type substrate 201, described P conduction type substrate 201 comprises the first interarea 232 and the second interarea 233; As shown in Figure 3: described P conduction type substrate 201 is compatible consistent mutually with stand CMOS preparation requirement, and the material of P conduction type substrate 201 can be selected silicon commonly used, and the first interarea 232 is corresponding with the second interarea 233;
B, carry out required barrier layer deposition, barrier etch and autoregistration Implantation at the first interarea 232 of P conduction type substrate 201, with in the first required N-type zone 202 of P conduction type substrate 201 interior formation, the 3rd N-type zone 204,205, the three N-type zones 204, the second p type island region territory be positioned at the outside in the second p type island region territory 205;
Such as Fig. 4 ~ shown in Figure 7, forming process is particularly:
B1, on the first interarea 232 of P conduction type substrate 201 deposit the first barrier layer 234, and optionally shelter and described the first barrier layer 234 of etching, the N-type foreign ion is injected in autoregistration above the first barrier layer 234, to obtain the second N-type zone 203 in P conduction type substrate 201; As shown in Figure 4, described the first barrier layer 234 is silicon dioxide or silicon nitride; Behind deposit the first barrier layer 234 on the first interarea 232, by the first barrier layer 234 of etching central area, after the N-type foreign ion is injected in autoregistration, can in P conduction type substrate 201, obtain the second N-type zone 203; Described N-type foreign ion is foreign ion commonly used in the semiconductor technology, and dosage and energy by control N-type foreign ion injects can form the second required N-type zone 203;
B2, obtain field areas of dielectric 214 in above-mentioned P conduction type substrate 201 interior growths, as shown in Figure 5: field areas of dielectric 214 is silicon dioxide, can obtain by the thermal oxide growth of routine;
B3, remove the first barrier layer 234 on above-mentioned P conduction type substrate 201 corresponding the first interareas 232, and on the first interarea 232 deposit the second barrier layer 235;
B4, optionally shelter and etching the second barrier layer 235, and the N-type foreign ion is injected in autoregistration above the second barrier layer 235, all to be positioned at the top in the second N-type zone 203 in the 202 and the 3rd N-type zone 204,204, the first N-types zone, the 202 and the 3rd N-type zone, semiconductor substrate 201 interior formation the first N-type zones; As shown in Figure 5: optionally shelter with etching the second barrier layer 235 after, the second barrier layer 235 that needs is formed the 202 and the 3rd N-type zone, the first N-type zone 204 top correspondences etches away, after injecting the N-type foreign ion, can form the outside in the 204 and first N-type zone 202,204, the three N-types zone, the 202 and the 3rd N-type zone, the first N-type zone;
B5, remove the second barrier layer 235 on above-mentioned P conduction type substrate 201 corresponding the first interareas 232, and on the first interarea 232 deposit the 3rd barrier layer 236;
B6, optionally shelter and etching the 3rd barrier layer 236, and the p type impurity ion is injected in autoregistration above the 3rd barrier layer 236, above the second N-type zone 203, to form the second p type island region territory 205;
As shown in Figure 7: during etching the 3rd barrier layer 236, the 3rd barrier layer 236 of the second p type island region territory 205 top correspondences is removed, after the p type impurity ion is injected in autoregistration, can form the second p type island region territory 205;
C, on the first interarea 232 of above-mentioned P conduction type substrate 201 correspondences deposit gate dielectric layer 215, described gate dielectric layer 215 covers the first interarea 232 of semiconductor substrates 201; As shown in Figure 8: described gate dielectric layer 215 is silicon dioxide, and gate dielectric layer 215 is covered in the surface of field areas of dielectric 214 and semiconductor substrate 201 correspondences;
D, on the first interarea 232 of above-mentioned P conduction type substrate 201 deposit floating gate electrode 216, described floating gate electrode 216 be covered on the gate dielectric layer 215 and run through the second p type island region territory 205 and the gate dielectric layer 215 of the first N-type zone 202 top correspondences on; As shown in Figure 9: the floating gate electrode 216 of the second p type island region territory 205 and the first N-type zone 202 top correspondences be same manufacturing layer among the figure, and interconnects and be integral; In order to show structure of the present invention, adopt the interval method of analysing and observe to obtain cutaway view of the present invention herein; Floating gate electrode 216 is in T shape on gate dielectric layer 215;
E, on above-mentioned gate dielectric layer 215 deposit the 4th barrier layer 237, and optionally shelter and etching the 4th barrier layer 237, remove corresponding the 4th barrier layer 237 that covers floating gate electrode 216,205 tops, the 202 and second p type island region territory, the first N-type zone;
F, the p type impurity ion is injected in autoregistration above above-mentioned the 4th barrier layer 237, top in the second p type island region territory 205 obtains a P type lightly doped region 208 and the 2nd P type lightly doped region 211, and as shown in figure 10: the 4th barrier layer 237 is silicon dioxide or silicon nitride; When optionally shelter with etching the 4th barrier layer 237 after so that corresponding zone all can stop in the p type impurity Implantation P-type conduction type of substrate 201 except the second p type island region territory 205 and the first N-type zone 202; Adopt conventional autoregistration to inject the p type impurity ion, can obtain simultaneously required P type lightly doped region;
G, remove above-mentioned the 4th barrier layer 237, and on the first interarea 232 deposit lateral protection material, form lateral protection layer 217 with the both sides at floating gate electrode 216; As shown in figure 11: the material of described lateral protection layer 217 is silica or silicon dioxide, can form required heavily doped region by lateral protection layer 217, simultaneously can be so that corresponding lightly doped region and lateral protection layer 217 are corresponding to the same;
H, on above-mentioned the first interarea 232 deposit the 5th barrier layer 238, and optionally shelter and etching the 5th barrier layer 238 the 5th barrier layer 238 that covers to remove the corresponding deposit in 202 tops, the second p type island region territory 205 and the first N-type zone; Deposit is also optionally sheltered and etching the 5th barrier layer 238, mainly is to avoid when forming heavily doped region, avoids in Implantation P-type conduction type of substrate 201 interior other zones; The 5th barrier layer 238 is silicon dioxide or silicon nitride;
I, the p type impurity ion is injected in autoregistration again above above-mentioned the 5th barrier layer 238, top in the second p type island region territory 205 obtains a P type heavily doped region 207 and the 2nd P type heavily doped region 212, and the top in the first N-type zone 202 obtains the 3rd P type heavily doped region 219 and the 4th P type heavily doped region 223; As shown in figure 12: described autoregistration is injected the concentration of p type impurity ion greater than the ion concentration of step g, because stopping of the 5th barrier layer 238 and lateral protection layer 217 arranged, can be so that form heavily doped region in the position of corresponding formation lightly doped region, and the lightly doped region that keeps can be consistent with lateral protection layer 217, thereby obtain required single polycrystalline architecture;
The 5th barrier layer 238 on j, removal the first interarea 232.As shown in figure 13: remove the 5th barrier layer 238, obtain required non-volatility memory.
Embodiment 2
Such as Fig. 2 and shown in Figure 23: semiconductor substrate is N conduction type substrate 239 in the present embodiment, after adopting N conduction type substrate 239, in N conduction type substrate 239, need not form the second N-type zone 203 and namely the second p type island region territory 205 directly contact with N-type conduction type substrate 239, simultaneously, the first N-type zone 202 also directly contacts with N conduction type substrate 239 with the 3rd N-type zone 204.All the other structures behind the employing N conduction type substrate 239 are all identical with arranging of embodiment 1.
Such as Figure 14 ~ shown in Figure 23: the non-volatility memory of said structure can realize by following processing step, particularly:
A, provide N conduction type substrate 239, described N conduction type substrate 239 comprises the first interarea 232 and the second interarea 233; As shown in figure 14, the material of N conduction type substrate 239 can be silicon;
B, carry out required barrier layer deposition, barrier etch and autoregistration Implantation at the first interarea 232 of semiconductor substrate, in semiconductor substrate, to form the outside that required the first N-type zone 202, the 3rd N-type zone 204,205, the three N-type zones 204, the second p type island region territory are positioned at the second p type island region territory 205;
The forming process of step b can be divided into:
S1, in above-mentioned semiconductor substrate the growth obtain field areas of dielectric 214, as shown in figure 15;
S2, on the first interarea 232 deposit the second barrier layer 235, and optionally shelter and etching the second barrier layer 235;
S3, the N-type foreign ion is injected in autoregistration above above-mentioned the second barrier layer 235, obtains regional the 202 and second N-type zone 204 of the first required N-type with the top N conduction type substrate 239 in, as shown in figure 16;
S4, remove the second barrier layer 235 on the first interarea 232, and on the first interarea 232 deposit the 3rd barrier layer 236;
S5, optionally shelter and etching the 3rd barrier layer 236, and the p type impurity ion is injected in autoregistration above the 3rd barrier layer 236, in N conduction type substrate 239, to obtain the second p type island region territory 205, as shown in figure 17;
C, on the first interarea 232 corresponding to above-mentioned semiconductor substrate deposit gate dielectric layer 215, described gate dielectric layer 215 covers the first interarea 232 of semiconductor substrates 201, as shown in figure 18;
D, on the first interarea 232 of above-mentioned semiconductor substrate deposit floating gate electrode 216, described floating gate electrode 216 is covered on the gate dielectric layer 215 and runs through on the gate dielectric layer 215 of the second p type island region territory 205, the first N-type zone 202 top correspondences, as shown in figure 19;
E, on above-mentioned gate dielectric layer 215 deposit the 4th barrier layer 237, and optionally shelter and etching the 4th barrier layer 237, remove corresponding the 4th barrier layer 237 that covers floating gate electrode 216,205 tops, 202, the second p type island region territories, the first N-type zone;
F, the p type impurity ion is injected in autoregistration above above-mentioned the 4th barrier layer 237, and the top in the second p type island region territory 205 obtains a P type lightly doped region 208 and the 2nd P type lightly doped region 211, as shown in figure 20;
G, remove above-mentioned the 4th barrier layer 237, and on the first interarea 232 deposit lateral protection material, form lateral protection layer 217 with the both sides at floating gate electrode 216, as shown in figure 21;
H, on above-mentioned the first interarea 232 deposit the 5th barrier layer 238, and optionally shelter and etching the 5th barrier layer 238 the 5th barrier layer 238 that covers to remove the corresponding deposit in 202 tops, the second p type island region territory 205 and the first N-type zone;
I, the p type impurity ion is injected in autoregistration again above above-mentioned the 5th barrier layer 238, top in the second p type island region territory 205 obtains a P type heavily doped region 207 and the 2nd P type heavily doped region 212, top in the first N-type zone 202 obtains the 3rd P type heavily doped region 219 and the 4th P type heavily doped region 223, as shown in figure 22;
The 5th barrier layer 238 on j, removal the first interarea 232, as shown in figure 23.
Such as Fig. 1 and shown in Figure 13: for single memory body cell 200, it can realize writing, read and wiping of single binary data.Below by single memory body cell 200 being write, reads and erase process illustrating the working mechanism of nonvolatile memory of the present invention.When needs write the input according to the time, p type island region territory voltage in the P conduction type substrate 201 is set to 0 current potential all the time, the first N-type zone 202, the 203 and the 3rd N-type zone, the second N-type zone 204 equal set 5v current potentials, the second p type island region territory 205 is set 0v current potential also, a P type doped region 206 of control capacitance 220 and the 2nd P type doped region 209 equal set 0V; Because the transfer function of control capacitance 220, the magnitude of voltage of 0V can be delivered on the floating gate electrode 216, produce the magnitude of voltage of 1 ~ 2V on the floating gate electrode 216, the P type drain region 221 set 5v that do not have the PMOS transistor 210 of lightly doped region do not have the P type source area 213 set 0v of the PMOS transistor 210 of lightly doped region.Like this, do not have lightly doped region PMOS transistor 210 P type source area and do not have the first N-type zone 202 of the PMOS transistor 210 of lightly doped region that the reverse bias voltage difference of 5v is arranged.Thereby carry out the electron ion collision by the electric field that enough high reverse bias voltage differences produces and produce freely electronics.Do not have the both sides of raceway groove of the PMOS transistor 210 of lightly doped region do not have lightly doped region PMOS transistor 210 P type drain region 221 and not have the voltage difference of P type source area 213 of the PMOS transistor 210 of lightly doped region be 5v. electron ion collision collision and produce electronics freely and form hot electron at the electric field acceleration of the raceway groove of the PMOS transistor 210 that does not have lightly doped region.The existing picture that the hot electron of the PMOS that Here it is does injects, hot electron will arrive in the floating gate electrode 216 by gate dielectric layer 215, realizes writing of data.Because floating gate electrode 216 belows are isolated by gate dielectric layer 215, the side completely cuts off by lateral protection layer 217, so electronic energy is in 216 interior can reservations for a long time of floating gate electrode.
During data in needs are wiped memory body cell 200, p type island region territory voltage in the P conduction type substrate 201 is set to 0 current potential all the time, the first N-type zone 202, the equal set 5V of the voltage voltage in the 203 and the 3rd N-type zone 204, the second N-type zone, voltage set-the 5V in the second p type island region territory 205, the one P type doped region 206, equal set-the 5V of voltage of the 2nd P type doped region 209, under control capacitance 220 effects, can be so that floating gate electrode 216 generation-4V ~-voltage of 5V, this moment regional 202 of floating gate electrode 216 and the first N-type gate dielectric layer about in the of 215 magnitude of voltage be-9 ~-10V, will reach field emission characteristic and be also referred to as FN(Fowler-Nordheim) the required electric field of tunnel effect, electrons enters by gate dielectric layer 215 in the raceway groove of the PMOS transistor 210 that does not have lightly doped region in the first N-type zone 202, thereby realizes floating gate electrode 216 interior data erases.
During data in needs read memory body cell 200, p type island region territory voltage in the P conduction type substrate 201 is set to 0 current potential all the time, the first N-type zone 202, the equal set 0.5V of the voltage voltage in the 203 and the 3rd N-type zone 204, the second N-type zone, second p type island region territory 205 set-1V, the one P type doped region 206 and the 2nd P type doped region 209 equal set-1V, do not have the PMOS source transistor polar region 213 set 0.5V of lightly doped region and do not have the PMOS transistor drain district 221 set 0V of lightly doped region, after loading above-mentioned magnitude of voltage, under the state at data writing in the memory body cell 200, a large amount of electronics are arranged in the floating gate electrode 216, under the state that memory body cell 200 interior data are wiped free of, electronics is from floating gate electrode 216 interior outflows, and floating gate electrode 216 is states of cation; When in the floating gate electrode 216 electronics being arranged, the electric current of the PMOS source transistor polar region 213 by there not being lightly doped region is larger, states of cation when floating gate electrode 216, the electric current of the PMOS source transistor polar region 213 by there not being lightly doped region is less, thereby according to the size of corresponding electric current, can know that memory body cell 200 is data writing states or is in the data erase state.
Owing to transportable anion (electronics) in the corresponding P+ zone in a P type doped region 206, the 2nd P type doped region 209, P type source area 213, the P type drain region 221 is minority, just is not easy volatilization and runs off.More of a specified duration when what the data that suck were managed like this, more safe and reliable when storage is used.
Such as Fig. 2 and shown in Figure 23: adopt the non-volatility memory of the N conduction type substrate 239 corresponding single polycrystalline architectures that form, need to carry out write, wipe and read the time, need corresponding on-load voltage, write accordingly, wipe and read operation realizing.Particularly, voltage was consistent when the voltage-drop loading that writes accordingly, wipes and read operated with the non-volatility memory of the single polycrystalline architecture that adopts the 201 corresponding formation of P conduction type substrate, no longer was described in detail herein.
At least one memory body cell 200 is set in the semiconductor substrate of the present invention, and memory body cell 200 comprises does not have the PMOS of lightly doped region transistor 210, control capacitance 220; There are not PMOS transistor 210 and the control capacitance 220 of lightly doped region mutually to isolate by field areas of dielectric 214; On the gate dielectric layer 215 of semiconductor substrate 201 floating gate electrode 216 is set, described floating gate electrode 216 connects to run through does not have the PMOS of lightly doped region transistor 210 and control capacitance 220; When floating gate electrode 216 is analog value with the PMOS transistor 210 interior voltage differences that do not have lightly doped region, can be to floating gate electrode 216 interior data writings or with the data erase in the floating gate electrode 216, flow through the electric current that does not have the PMOS of lightly doped region transistor 210 by detection and can know floating gate electrode 216 residing programming write state or erase statuses, the preparation flow of whole memory body cell 200 can be compatible mutually with existing CMOS logic process, compact conformation, can cut down finished cost, improve the adaptability of nonvolatile memory and CMOS logical circuit; The one P type doped region 206 and the 2nd P type doped region 209 of the P type source area 213 of PMOS transistor 210 internal upper parts by there not being lightly doped region and P type drain region 221, control capacitance 220 internal upper parts, can so that data writing keeps is more of a specified duration, improve the safety and reliability of non-volatility memory.
Claims (11)
1. one kind has the non-volatility memory that P+ and PMOS transistor do not have the single polycrystalline architecture of lightly doped region, comprises semiconductor substrate; It is characterized in that: the top in the described semiconductor substrate is provided with some memory body cells (200) for storage, described memory body cell (200) comprises does not at least have the PMOS of lightly doped region transistor (210) and control capacitance (220), and floating gate electrode (216) is linked together the PMOS transistor (210) that does not have lightly doped region and control capacitance (220).
2. a kind of P+ of having according to claim 1 and PMOS transistor do not have the non-volatility memory of the single polycrystalline architecture of lightly doped region, it is characterized in that: it is in order to reduce the voltage when writing hot electron that the PMOS transistor (210) in the described memory body cell (200) does not have lightly doped region.
3. a kind of P+ of having according to claim 1 and PMOS transistor do not have the non-volatility memory of the single polycrystalline architecture of lightly doped region, it is characterized in that: described memory body cell (200) is the non-volatility memory of single polycrystalline architecture.
4. a kind of P+ of having according to claim 1 and PMOS transistor do not have the non-volatility memory of the single polycrystalline architecture of lightly doped region, it is characterized in that: floating gate electrode (216) is the single polycrystalline body of P+ type.
5. one kind has the non-volatility memory that P+ and PMOS transistor do not have the single polycrystalline architecture of lightly doped region, comprises semiconductor substrate; It is characterized in that: the top in the described semiconductor substrate is provided with some memory body cells (200) for storage, and described memory body cell (200) comprises does not have the PMOS of lightly doped region transistor (210) and control capacitance (220); Between the described PMOS transistor (210) that does not have a lightly doped region, control capacitance (220) by mutually isolation of the field areas of dielectric (214) in the semiconductor substrate; Be deposited with gate dielectric layer (215) on the surface of semiconductor substrate, described gate dielectric layer (215) is provided with floating gate electrode (216), described floating gate electrode (216) covers and runs through does not have gate dielectric layer (215) corresponding to the PMOS of lightly doped region transistor (210) and control capacitance (220) top, the both sides of floating gate electrode (216) are deposited with lateral protection layer (217), and lateral protection layer (217) covers the sidewall of floating gate electrode (216); Do not have the PMOS transistor (210) of lightly doped region to comprise the first N-type zone (202) and be positioned at the P type source area (213) and P type drain region (221) of described the first N-type zone (202) internal upper part, the P type doped region (206) that control capacitance (220) comprises the second p type island region territory (205) and is positioned at described the second p type island region territory (205) internal upper part is corresponding with the floating gate electrode (216) of top with the 2nd P type doped region (209), and contacts with corresponding gate dielectric layer (215) and field areas of dielectric (214) respectively.
6. a kind of P+ of having according to claim 5 and PMOS transistor do not have the non-volatility memory of the single polycrystalline architecture of lightly doped region, it is characterized in that: when described semiconductor substrate was P conduction type substrate (201), the described PMOS transistor (210) that does not have a lightly doped region and control capacitance (220) were isolated with P-type conduction type of substrate (201) by the 3rd N-type zone (204) of the zone of the second N-type in the P-type conduction type of substrate (201) (203) and top, the second N-type zone (203).
7. a kind of P+ of having according to claim 5 and PMOS transistor do not have the non-volatility memory of the single polycrystalline architecture of lightly doped region, it is characterized in that: described floating gate electrode (216) comprise conductive polycrystalline silicon.
8. a kind of P+ of having according to claim 5 and PMOS transistor do not have the non-volatility memory of the single polycrystalline architecture of lightly doped region, it is characterized in that: described gate dielectric layer (215) is the transistorized electrode grid oxide layer of I/O in the technique.
9. one kind has the non-volatility memory and preparation method thereof that P+ and PMOS transistor do not have the single polycrystalline architecture of lightly doped region, and it is characterized in that: described preparation method comprises the steps:
(a), provide semiconductor substrate, described semiconductor substrate to comprise the first interarea (232) and the second interarea (233);
(b), growth obtains field areas of dielectric (214) in above-mentioned semiconductor substrate, carry out required barrier layer deposition, barrier etch and autoregistration Implantation with the first interarea (232) at semiconductor substrate, in semiconductor substrate, to form required the first N-type zone (202), the 3rd N-type zone (204), the second p type island region territory (205);
(c), at the upper deposit gate dielectric layer (215) of the first interarea (232) corresponding to above-mentioned semiconductor substrate, first interarea (232) of described gate dielectric layer (215) covering semiconductor substrate (201);
(d), at the upper deposit floating gate electrode (216) of first interarea (232) of above-mentioned semiconductor substrate, it is upper and run through on the gate dielectric layer (215) of the second p type island region territory (205) and top, the first N-type zone (202) correspondence that described floating gate electrode (216) is covered in gate dielectric layer (215);
(e), on upper deposit the 4th barrier layer (237) of above-mentioned gate dielectric layer (215), and optionally shelter and etching the 4th barrier layer (237), remove the first N-type zone (202), corresponding the 4th barrier layer (237) that covers floating gate electrode (216), top, the second p type island region territory (205);
(f), inject the p type impurity ion in the autoregistration of above-mentioned the 4th barrier layer (237) top, the top in the second p type island region territory (205) obtains a P type lightly doped region (208) and the 2nd P type lightly doped region (211);
(g), remove above-mentioned the 4th barrier layer (237), and at the upper deposit lateral protection material of the first interarea (232), form lateral protection layer (217) with the both sides at floating gate electrode (216);
(h), on upper deposit the 5th barrier layer (238) of above-mentioned the first interarea (232), and optionally shelter and etching the 5th barrier layer (238), to remove the 5th barrier layer (238) of the second p type island region territory (205), the corresponding deposit covering in top, the first N-type zone (202);
(i), in above-mentioned the 5th barrier layer (238) top again autoregistration inject the p type impurity ion, top in the second p type island region territory (205) obtains a P type heavily doped region (207) and the 2nd P type heavily doped region (212), and the top in the first N-type zone (202) obtains the 3rd P type heavily doped region (219) and the 4th P type heavily doped region (223);
(j), the 5th barrier layer (238) on removal the first interarea (232).
10. a kind of P+ of having according to claim 9 and PMOS transistor do not have the preparation method of non-volatility memory of the single polycrystalline architecture of lightly doped region to have, it is characterized in that: in described step (a), when semiconductor substrate was P conduction type substrate (201), described step (b) comprised
(b1), on upper deposit the first barrier layer (234) of first interarea (232) of P conduction type substrate (201), and optionally shelter and described the first barrier layer of etching (234), the N-type foreign ion is injected in the top autoregistration in the first barrier layer (234), to obtain the second N-type zone (203) in semiconductor substrate (201);
(b2), growth obtains field areas of dielectric (214) in above-mentioned P conduction type substrate (201);
(b3), remove the first barrier layer (234) on above-mentioned P conduction type substrate (201) corresponding the first interareas (232), and on upper deposit the second barrier layer (235) of the first interarea (232);
(b4), optionally shelter and etching the second barrier layer (235), and at the second barrier layer (235) top autoregistration injection N-type foreign ion, to form the first N-type zone (202) and the 3rd N-type zone (204) in semiconductor substrate (201), the first N-type zone (202) and the 3rd N-type zone (204) all are positioned at the top in the second N-type zone (203);
(b5), remove the second barrier layer (235) on above-mentioned P conduction type substrate (201) corresponding the first interareas (232), and on upper deposit the 3rd barrier layer (236) of the first interarea (232);
(b6), optionally shelter and etching the 3rd barrier layer (236), and inject the p type impurity ion in the 3rd barrier layer (236) top autoregistration, to form the second p type island region territory (205) in top, the second N-type zone (203).
11. a kind of P+ of having and PMOS transistor do not have the non-volatility memory and preparation method thereof of the single polycrystalline architecture of lightly doped region according to claim 9, it is characterized in that: in described step (a), when semiconductor substrate was N conduction type substrate (239), described step (b) comprised
(s1), growth obtains field areas of dielectric (214) in above-mentioned P conduction type substrate (201);
(s2), on upper deposit the second barrier layer (235) of the first interarea (232), and optionally shelter and etching the second barrier layer (235);
(s3), inject the N-type foreign ion in the autoregistration of the top on above-mentioned the second barrier layer (235), obtain required the first N-type zone (202) and the second N-type regional (204) with the top N conduction type substrate (239) in;
(s4), remove the second barrier layer (235) on the first interarea (232), and on upper deposit the 3rd barrier layer (236) of the first interarea (232);
(s5), optionally shelter and etching the 3rd barrier layer (236), and inject the p type impurity ion in the 3rd barrier layer (236) top autoregistration, in N conduction type substrate (239), to obtain the second p type island region territory (205).
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