CN103021945B - Array substrate, manufacturing method of array substrate, and display device with array substrate - Google Patents
Array substrate, manufacturing method of array substrate, and display device with array substrate Download PDFInfo
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- CN103021945B CN103021945B CN201210593034.7A CN201210593034A CN103021945B CN 103021945 B CN103021945 B CN 103021945B CN 201210593034 A CN201210593034 A CN 201210593034A CN 103021945 B CN103021945 B CN 103021945B
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- scan line
- short circuit
- grid scan
- circuit connecting
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Abstract
The invention provides an array substrate, a manufacturing method of the array substrate, and a display device with the array substrate, and belongs to the field of liquid crystal display. The manufacturing method of the array substrate includes: depositing a gate metal layer on a substrate to form gate scan lines composed of the gate metal layer and a shorting bar; after a gate insulating layer is formed, forming through holes at the positions of the shorting bar and the gate scan lines; depositing a conducting layer connected with the shorting bar and the gate scan lines through the through holes. The shorting bar is disconnected with the gate scan lines. According to the technical scheme, connection of the shorting bar with the gate scan lines is guaranteed, and the requirement for array test is met.
Description
Technical field
The present invention relates to field of liquid crystal display, refer to a kind of array base palte and manufacture method, display unit especially.
Background technology
In prior art, after manufacture completes array base palte, need the grid scan line input signal of array substrate to carry out array test.At FFS(fringe field switching) in the manufacture process of type array base palte, as shown in Figure 1, usually, while formation gate electrode and grid scan line 1, grid metal level 3 is utilized to form the short circuit connecting line (Array Test shorting bar) 2 of the array test linked together by each bar grid scan line 1.But in ensuing gate insulation layer depositing operation, at CVD(Chemical Vapor Deposition, chemical vapour deposition (CVD)) easily produce electrostatic in chamber, the static discharge phenomenon occurred between grid scan line 1 can blow short circuit connecting line 2, has influence on the effect of array test.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and manufacture method, display unit, can ensure the connection between short circuit connecting line and grid scan line, meets the needs of array test.
For solving the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:
On the one hand, a kind of manufacture method of array base palte is provided, comprises:
Substrate deposits grid metal level, and form the grid scan line and short circuit connecting line that are made up of described grid metal level, the connection between described short circuit connecting line and described grid scan line is off;
After formation gate insulation layer, form via hole in the position of correspondence described short circuit connecting line and described grid scan line;
Depositing conducting layer, described conductive layer connects described short circuit connecting line and described grid scan line by described via hole.
Further, described on substrate, deposit grid metal level before also comprise:
At substrate deposition first transparency conducting layer, form the syndeton in order to connect described short circuit connecting line and described grid scan line be made up of described first transparency conducting layer.
Further, described syndeton is square waveform.
Further, described after formation gate insulation layer, form via hole, depositing conducting layer in the position of correspondence described short circuit connecting line and described grid scan line, described conductive layer connects described short circuit connecting line by described via hole and described grid scan line comprises:
Before substrate deposits data metal layer, form via hole in the position of correspondence described short circuit connecting line and described grid scan line;
The substrate being formed with described via hole deposits data metal layer, and described data metal layer connects described short circuit connecting line and described grid scan line by described via hole.
Further, described after formation gate insulation layer, form via hole, depositing conducting layer in the position of correspondence described short circuit connecting line and described grid scan line, described conductive layer connects described short circuit connecting line by described via hole and described grid scan line comprises:
After substrate forms passivation layer, form via hole in the position of correspondence described short circuit connecting line and described grid scan line;
The substrate being formed with described via hole deposits the second transparency conducting layer, and described second transparency conducting layer connects described short circuit connecting line and described grid scan line by described via hole.
The embodiment of the present invention additionally provides a kind of array base palte, and described array base palte comprises:
The grid scan line formed by grid metal level and short circuit connecting line, wherein, the position of corresponding described short circuit connecting line and described grid scan line is formed with via hole, and described short circuit connecting line is connected by the conductive layer that described via hole deposits with described grid scan line.
Further, described array base palte also comprises the syndeton in order to connect described short circuit connecting line and described grid scan line be made up of the first transparency conducting layer.
Further, described syndeton is square waveform.
Further, described via hole runs through the gate insulation layer of array base palte, and described conductive layer is the data metal layer forming source electrode and drain electrode.
Further, described via hole runs through gate insulation layer and the passivation layer of array base palte, and described conductive layer is the second transparency conducting layer forming pixel electrode.
The embodiment of the present invention additionally provides a kind of display unit, comprises array base palte as above.
Embodiments of the invention have following beneficial effect:
In such scheme, when being formed grid scan line and short circuit connecting line by grid metal level, connection between short circuit connecting line and grid scan line is off, via hole is formed afterwards in the position of correspondence described short circuit connecting line and described grid scan line, the conductive layer deposited by subsequent technique connects short circuit connecting line and grid scan line, the connection between short circuit connecting line and grid scan line can be ensured like this, meet the needs of array test.
Accompanying drawing explanation
Fig. 1 is the connection diagram of short circuit connecting line and grid scan line in existing FFS type array base palte;
Fig. 2 is the schematic diagram that the embodiment of the present invention forms syndeton;
Fig. 3 is the schematic diagram that the embodiment of the present invention forms short circuit connecting line and grid scan line;
Fig. 4 is the schematic diagram that the embodiment of the present invention forms via hole;
Fig. 5 is the schematic diagram that the embodiment of the present invention forms the conductive layer connecting short circuit connecting line and grid scan line.
Reference numeral
1 grid scan line
2 short circuit connecting lines
3 grid metal levels
4 syndetons
5 via holes
6 conductive layers
Embodiment
For embodiments of the invention will be solved technical problem, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
Embodiments of the invention in prior art formation gate electrode and grid scan line while, grid metal level is utilized to form the short circuit connecting line of the array test linked together by each bar grid scan line, but in ensuing gate insulation layer depositing operation, easily electrostatic is produced in CVD chamber, the static discharge phenomenon occurred between grid scan line can blow short circuit connecting line, have influence on the problem of the effect of array test, a kind of array base palte and manufacture method thereof are provided, display unit, the connection between short circuit connecting line and grid scan line can be ensured, meet the needs of array test.
Embodiments provide a kind of manufacture method of array base palte, comprising:
Substrate deposits grid metal level, and form the grid scan line and short circuit connecting line that are made up of described grid metal level, the connection between described short circuit connecting line and described grid scan line is off;
After formation gate insulation layer, form via hole in the position of correspondence described short circuit connecting line and described grid scan line;
Depositing conducting layer, described conductive layer connects described short circuit connecting line and described grid scan line by described via hole.
The manufacture method of the array base palte of the embodiment of the present invention, when being formed grid scan line and short circuit connecting line by grid metal level, connection between short circuit connecting line and grid scan line is off, via hole is formed afterwards in the position of correspondence described short circuit connecting line and described grid scan line, the conductive layer deposited by subsequent technique connects short circuit connecting line and grid scan line, the connection between short circuit connecting line and grid scan line can be ensured like this, meet the needs of array test.
Due in the manufacture process of FFS type array base palte, before deposition grid metal level, the first transparency conducting layer can be utilized to form the public electrode of array base palte, therefore, can while formation public electrode, utilize the syndeton of the first transparency conducting layer formation in order to connect short circuit connecting line and grid scan line, after forming grid scan line and short circuit connecting line like this, just each grid scan line can be coupled together by short circuit connecting line and syndeton.Because the resistance ratio of the first transparency conducting layer is comparatively large, therefore, in ensuing gate insulation layer depositing operation, the electrostatic in CVD chamber between each grid scan line just can be discharged by high-resistance syndeton.Therefore, described on substrate, deposit grid metal level before also comprise: at substrate deposition first transparency conducting layer, form the syndeton in order to connect described short circuit connecting line and described grid scan line be made up of described first transparency conducting layer.Further, in order to improve the resistance of syndeton, syndeton can also be designed to square waveform, to increase the length of syndeton, thus increase the resistance of syndeton.
Wherein, the conductive layer connecting described short circuit connecting line and described grid scan line can for forming the data metal layer of source electrode and drain electrode, via hole runs through gate insulation layer, now, described after formation gate insulation layer, form via hole, depositing conducting layer in the position of correspondence described short circuit connecting line and described grid scan line, described conductive layer connects described short circuit connecting line by described via hole and described grid scan line comprises:
Before substrate deposits data metal layer, form via hole in the position of correspondence described short circuit connecting line and described grid scan line;
The substrate being formed with described via hole deposits data metal layer, and described data metal layer connects described short circuit connecting line and described grid scan line by described via hole.
Further, the conductive layer connecting described short circuit connecting line and described grid scan line can also for forming the second transparency conducting layer of pixel electrode, via hole runs through passivation layer and gate insulation layer, now, described after formation gate insulation layer, form via hole, depositing conducting layer in the position of correspondence described short circuit connecting line and described grid scan line, described conductive layer connects described short circuit connecting line by described via hole and described grid scan line comprises:
After substrate forms passivation layer, form via hole in the position of correspondence described short circuit connecting line and described grid scan line;
The substrate being formed with described via hole deposits the second transparency conducting layer, and described second transparency conducting layer connects described short circuit connecting line and described grid scan line by described via hole.
The embodiment of the present invention additionally provides a kind of array base palte, and described array base palte comprises:
The grid scan line formed by grid metal level and short circuit connecting line, wherein, the position of corresponding described short circuit connecting line and described grid scan line is formed with via hole, and described short circuit connecting line is connected by the conductive layer that described via hole deposits with described grid scan line.
Further, described array base palte also comprises the syndeton in order to connect described short circuit connecting line and described grid scan line be made up of the first transparency conducting layer.
Further, described syndeton is square waveform.
Further, described via hole runs through the gate insulation layer of array base palte, and described conductive layer is the data metal layer forming source electrode and drain electrode.
Further, described via hole runs through gate insulation layer and the passivation layer of array base palte, and described conductive layer is the second transparency conducting layer forming pixel electrode.
The array base palte of the embodiment of the present invention, when being formed grid scan line and short circuit connecting line by grid metal level, connection between short circuit connecting line and grid scan line is off, via hole is formed afterwards in the position of correspondence described short circuit connecting line and described grid scan line, the conductive layer deposited by subsequent technique connects short circuit connecting line and grid scan line, the connection between short circuit connecting line and grid scan line can be ensured like this, meet the needs of array test; And the array base palte of the embodiment of the present invention is formed with high-resistance syndeton between grid scan line, solve the problem that static discharge occurs between grid scan line in CVD chamber.
Below in conjunction with accompanying drawing 2-5 and specific embodiment, array base palte of the present invention and manufacture method thereof are introduced further:
Embodiment one:
The manufacture method of the array base palte of the present embodiment comprises the following steps:
Step a1: provide a substrate, deposits the first transparency conducting layer on the substrate, as shown in Figure 2, is formed the public electrode and syndeton 4 that are made up of the first transparency conducting layer by patterning processes;
Step a2: deposit grid metal level 3 on the substrate through step a1, as shown in Figure 3, the gate electrode, grid scan line 1 and the short circuit connecting line 2 that are made up of grid metal level 3 is formed by patterning processes, as seen from Figure 3, connection between grid scan line 1 and short circuit connecting line 2 disconnects, and connected between each grid scan line 1 by syndeton 4 simultaneously.Because the resistance ratio of the first transparency conducting layer is comparatively large, therefore, in ensuing gate insulation layer depositing operation, the electrostatic in CVD chamber between each grid scan line 1 just can be discharged by high-resistance syndeton 4.Further, in order to improve the resistance of syndeton 4, as shown in Figure 3, syndeton 4 is in square waveform;
Step a3: deposit gate insulation layer and semiconductor layer successively on the substrate through step a2, forms the figure of semiconductor layer by patterning processes;
Step a4: deposit ohmic contact layer and source and drain metal level successively on the substrate through step a3, forms the figure of the figure of ohmic contact layer, source electrode, drain electrode and data wire by patterning processes;
Step a5: deposit passivation layer on the substrate through step a4, forms the figure including the passivation layer of pixel electrode via hole and via hole 5 by patterning processes.As shown in Figure 4, this step, while formation pixel electrode via hole, utilizes and forms in the position of corresponding grid scan line 1 and short circuit connecting line 2 via hole 5 running through gate insulation layer and passivation layer with a patterning processes;
Step a6: deposit the second transparency conducting layer on the substrate through step a5, as shown in Figure 5, second transparency conducting layer 6 connects short circuit connecting line 2 and grid scan line 1 by via hole 5, thus realizes the connection between each bar grid scan line 1 and the short circuit connecting line 2 of array test.
In the present embodiment, when being formed grid scan line and short circuit connecting line by grid metal level, connection between short circuit connecting line and grid scan line is off, via hole is formed afterwards in the position of correspondence described short circuit connecting line and described grid scan line, the conductive layer deposited by subsequent technique connects short circuit connecting line and grid scan line, the connection between short circuit connecting line and grid scan line can be ensured like this, meet the needs of array test.The present embodiment, by forming pixel electrode via hole and via hole 5 with a patterning processes simultaneously, can complete the making of via hole 5 under the prerequisite not increasing patterning processes; And the array base palte of the present embodiment is formed with high-resistance syndeton between grid scan line, solve the problem that static discharge occurs between grid scan line in CVD chamber.
Embodiment two:
The manufacture method of the array base palte of the present embodiment comprises the following steps:
Step b1: provide a substrate, deposits the first transparency conducting layer on the substrate, as shown in Figure 2, is formed the public electrode and syndeton 4 that are made up of the first transparency conducting layer by patterning processes;
Step b2: deposit grid metal level 3 on the substrate through step b1, as shown in Figure 3, the gate electrode, grid scan line 1 and the short circuit connecting line 2 that are made up of grid metal level 3 is formed by patterning processes, as seen from Figure 3, connection between grid scan line 1 and short circuit connecting line 2 disconnects, and connected between each grid scan line 1 by syndeton 4 simultaneously.Because the resistance ratio of the first transparency conducting layer is comparatively large, therefore, in ensuing gate insulation layer depositing operation, the electrostatic in CVD chamber between each grid scan line 1 just can be discharged by high-resistance syndeton 4.Further, in order to improve the resistance of syndeton 4, as shown in Figure 3, syndeton 4 is in square waveform;
Step b3: deposit gate insulation layer and semiconductor layer, ohmic contact layer on the substrate through step b2 successively, forms the figure of semiconductor layer and ohmic contact layer by patterning processes;
Step b4: as shown in Figure 4, forms in the position of corresponding grid scan line 1 and short circuit connecting line 2 via hole 5 running through gate insulation layer;
Step b5: deposit source and drain metal level 6 on the substrate through step b4, as shown in Figure 5, source and drain metal level 6 connects short circuit connecting line 2 and grid scan line 1 by via hole 5, thus realizes the connection between each bar grid scan line 1 and the short circuit connecting line 2 of array test.
In the present embodiment, when being formed grid scan line and short circuit connecting line by grid metal level, connection between short circuit connecting line and grid scan line is off, via hole is formed afterwards in the position of correspondence described short circuit connecting line and described grid scan line, the conductive layer deposited by subsequent technique connects short circuit connecting line and grid scan line, the connection between short circuit connecting line and grid scan line can be ensured like this, meet the needs of array test; And the array base palte of the present embodiment is formed with high-resistance syndeton between grid scan line, solve the problem that static discharge occurs between grid scan line in CVD chamber.
The embodiment of the present invention additionally provides a kind of display unit, comprise array base palte as above, described display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. a manufacture method for array base palte, is characterized in that, comprising:
Substrate deposits grid metal level, form the grid scan line and short circuit connecting line that are made up of described grid metal level, connection between described short circuit connecting line and described grid scan line is off, and each grid scan line includes that two or more disconnects each other, discrete part;
After formation gate insulation layer, form via hole in the position of correspondence described short circuit connecting line and described grid scan line;
Depositing conducting layer, described conductive layer connects described short circuit connecting line and described grid scan line by described via hole;
Wherein, described on substrate, deposit grid metal level before also comprise:
At substrate deposition first transparency conducting layer, form the syndeton be made up of described first transparency conducting layer, connected by described syndeton between the different piece that same grid scan line disconnects.
2. the manufacture method of array base palte according to claim 1, is characterized in that, described syndeton is square waveform.
3. the manufacture method of array base palte according to claim 1, it is characterized in that, described conductive layer is data metal layer, described after formation gate insulation layer, via hole is formed in the position of correspondence described short circuit connecting line and described grid scan line, depositing conducting layer, described conductive layer connects described short circuit connecting line by described via hole and described grid scan line comprises:
Before substrate deposits data metal layer, form in the position of correspondence described short circuit connecting line and described grid scan line the via hole running through described gate insulation layer;
The substrate being formed with described via hole deposits data metal layer, and described data metal layer connects described short circuit connecting line and described grid scan line by described via hole.
4. the manufacture method of array base palte according to claim 1, it is characterized in that, described conductive layer is the second transparency conducting layer, described after formation gate insulation layer, via hole is formed in the position of correspondence described short circuit connecting line and described grid scan line, depositing conducting layer, described conductive layer connects described short circuit connecting line by described via hole and described grid scan line comprises:
After substrate forms gate insulation layer, form the figure of semiconductor layer, ohmic contact layer and source and drain metal level successively;
Form passivation layer, and form in the position of correspondence described short circuit connecting line and described grid scan line the via hole running through described gate insulation layer and described passivation layer;
The substrate being formed with described via hole deposits the second transparency conducting layer, and described second transparency conducting layer connects described short circuit connecting line and described grid scan line by described via hole.
5. an array base palte, is characterized in that, described array base palte comprises:
The grid scan line formed by grid metal level and short circuit connecting line, wherein, the position of corresponding described short circuit connecting line and described grid scan line is formed with via hole, described short circuit connecting line is connected by the conductive layer that described via hole deposits with described grid scan line, and each grid scan line includes that two or more disconnects each other, discrete part;
By the first transparency conducting layer form in order to connect same grid scan line disconnect different piece between syndeton.
6. array base palte according to claim 5, is characterized in that, described syndeton is square waveform.
7. array base palte according to claim 5, is characterized in that, described via hole runs through the gate insulation layer of array base palte, and described conductive layer is the data metal layer forming source electrode and drain electrode.
8. array base palte according to claim 5, is characterized in that, described via hole runs through gate insulation layer and the passivation layer of array base palte, and described conductive layer is the second transparency conducting layer forming pixel electrode.
9. a display unit, is characterized in that, comprises the array base palte according to any one of claim 5-8.
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| CN108196407A (en) * | 2017-12-28 | 2018-06-22 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof, display device |
| US10685988B2 (en) | 2017-12-28 | 2020-06-16 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Display panel having connection line connected to end portions of scan lines and manufacturing method thereof, and display device |
| CN109801909A (en) * | 2018-06-12 | 2019-05-24 | 京东方科技集团股份有限公司 | Array substrate motherboard and its manufacturing method, array substrate, display device |
| CN109461384B (en) * | 2018-12-18 | 2021-03-16 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of display panel or array assembly for preventing static electricity and display panel |
| CN111638617A (en) | 2020-06-05 | 2020-09-08 | 武汉华星光电技术有限公司 | Electrostatic protection circuit, electrostatic protection circuit manufacturing method and display panel |
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| US6653160B2 (en) * | 1999-12-13 | 2003-11-25 | Lg. Philips Lcd Co. Ltd | Method of manufacturing array substrate for use in liquid crystal display device |
| US7220611B2 (en) * | 2003-10-14 | 2007-05-22 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display panel and fabricating method thereof |
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| CN102289115A (en) * | 2010-06-21 | 2011-12-21 | 北京京东方光电科技有限公司 | Method for manufacturing master board and TFT (Thin Film Transistor) array substrate |
| CN102566169A (en) * | 2010-12-31 | 2012-07-11 | 上海天马微电子有限公司 | Detection device and testing method of liquid crystal display device |
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