CN103021851A

CN103021851A - Preparation method of multi-grid-electrode field effect transistor

Info

Publication number: CN103021851A
Application number: CN201110280744XA
Authority: CN
Inventors: 洪中山
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2011-09-21
Filing date: 2011-09-21
Publication date: 2013-04-03
Anticipated expiration: 2031-09-21
Also published as: CN103021851B

Abstract

The invention provides a preparation method of a multi-grid-electrode field effect transistor. The preparation method of the multi-grid-electrode field effect transistor comprises the steps of firstly providing a semiconductor base comprising a semiconductor layer containing Si at the bottom, an insulation layer as well as a semiconductor layer containing Si at the top; depositing a hard mask on the semiconductor base; forming a hard mask with patterns through a plurality of steps, and forming fins; depositing another insulation layer on the insulation layer, the fins and the hard mask; removing the redundant insulation layer, and reserving partial insulation layer on the bottom of the fins; and finally removing the hard mask. The invention also provides a multi-grid-electrode field effect transistor structure which comprises a semiconductor layer containing Si at the bottom, an insulation layer positioned on the semiconductor layer containing Si on the bottom as well as semiconductor fins embedded into the insulation layer partially, wherein the heights of the semiconductor fins embedded into the insulation layer partially are 1/10-1/3 of the total heights of the semiconductor fins.

Description

A kind of manufacture method of multiple gate field effect transistor

Technical field

The present invention relates to a kind of manufacture method of semiconductor device, particularly relate to a kind of manufacture method of multiple gate field effect transistor.

Background technology

In the microelectronic integrated circuit semiconductor device fabrication process, along with the requirement to device performance is more and more higher, need to makes metal oxide semiconductor transistor (MOSFET) device dimensions shrink, and avoid short-channel effect as far as possible.In circuit, increase the number of fins of fin-shaped field effect transistor (FinFET), can make to drive the intensity increase, thereby improve circuit computing speed.

In order to improve the device density in the integrated circuit, can obtain less size and spacing by two kinds of methods.A kind of method is that the radiation wavelength that will be used for exposure is reduced to deep ultraviolet (DUV), far ultraviolet (FUV) or extreme ultraviolet (EUV) scope, and this method is to carrying out the equipment of photoetching and having relatively high expectations of photoresist.Another kind method is by conventional photoetching process being combined with etching technics, obtaining less characteristic size and feature pitch by multiexposure, multiple exposure or etching; Perhaps adopt the formation of sidewall image transfer (Sidewall Image Transfer, SIT) technology less than the live width of critical dimension (Critical Dimension, CD).Sidewall image transfer technique provides the high-density device structure that has nothing to do with photoetching resolution and pitch, this process forms separator at the sidewall of the axle of optics definition, and define following layer structure with separator as mask, thereby make the live width of device and the restriction that density surpasses photoetching, obtain the fin pitch less than minimum lithographic pitch.

Form the fin of multiple gate field effect transistor by SIT technique, its fin height (H _Fin) determined by series of parameters, the influencing factor that wherein plays a decisive role is fin pitch (P _Fin), fin pitch (P _Fin) narrower, fin height (H _Fin) less, as shown in Figure 1.In order to save cost, simplify technique, guarantee simultaneously device performance, wish in semiconductor device manufacturing process, to obtain higher fin height (H _Fin), prevent from occurring in the manufacturing process subsiding and the problem such as coming off of fin.

Summary of the invention

The present invention relates to a kind of manufacture method of semiconductor device, particularly relate to a kind of manufacture method of multiple gate field effect transistor, comprising:

Semiconductor base is provided, and described semiconductor base comprises that the bottom contains Si semiconductor layer, insulating barrier and top and contains the Si semiconductor layer; Form hard mask at described semiconductor base; The described hard mask of patterning; Form fin; At described insulating barrier, described fin and described hard another insulating barrier of mask deposition; Remove unnecessary described another insulating barrier, the part of described hard mask and described fin is come out.

Preferably, wherein said semiconductor base is silicon-on-insulator.

Preferably, wherein said hard mask is silicon nitride.

Preferably, wherein the method for the described hard mask of patterning adopts at least a in double-pattern photoetching technique, electron beam lithography, nanometer embossing or the extreme ultraviolet lithography.

Preferably, the method that wherein deposits another insulating barrier adopts mobile chemical vapor deposition method, spin coating process or high-density plasma technique.

Preferably, wherein adopt the depression etching to remove unnecessary described another insulating barrier.

Preferably, wherein before described recess etch step, also comprise the step of removing described another insulating barrier on described hard mask top by cmp.

Preferably, wherein remove described another insulating barrier after, another thickness of insulating layer that is retained that is positioned at described fin bottom is 1/10 ~ 1/3 of fin total height.

Preferably, wherein remove described another insulating barrier after, also comprise the step of removing described hard mask.

The present invention relates to a kind of multiple gate field effect transistor structure, comprising:

The bottom contains the Si semiconductor layer, is positioned at the semiconductor fin that described bottom contains the insulating barrier on the Si semiconductor layer and is partially submerged into described insulating barrier.

Preferably, the semiconductor fin height that wherein is partially submerged into insulating barrier is 1/10 ~ 1/3 of semiconductor fin total height.

Description of drawings

Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of one embodiment of the present of invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,

Fig. 1 is the fin sectional view of the multiple gate field effect transistor of available technology adopting SIT technique formation;

Fig. 2 A-2G is the sectional view according to each step in the manufacture method flow process of one embodiment of the invention making multiple gate field effect transistor;

Fig. 3 is the process chart of making multiple gate field effect transistor according to one embodiment of the invention.

Symbol description:

Fig. 1

110: fin, 120: hard mask

Fig. 2

200: semiconductor base, 201: the bottom contains Si semiconductor layer, 202: insulating barrier, 203: the top contains Si semiconductor layer, 210: hard mask, 220: fin, 230: insulating barrier, 231: insulating barrier, 232: insulating barrier.

Embodiment

Next, more intactly describe the present invention in connection with accompanying drawing, the cross-sectional view as the schematic diagram of desirable embodiment of the present invention (and intermediate structure) shown in the accompanying drawing is described inventive embodiment.Same reference numerals represents identical element from start to finish.The present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.

Should be noted that as used herein that the purpose of term only is to describe specific embodiment and not as restriction of the present invention.In the accompanying drawings, for clear, size and the relative size in floor and district may be exaggerated.And, owing to for example manufacturing technology and/or tolerance, change of shape shown in causing.Therefore, embodiments of the invention should not be confined to the specific size shape in district shown here, but comprise owing to for example making the form variations that causes." one " of singulative, " one " and " described/as to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context.Also should be noted that, term " composition " and/or " comprising ", when in these specifications, using, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.

At first, please refer to shown in Fig. 2 A, semiconductor substrate 200 is provided, this semiconductor base is silicon-on-insulator (Silicon on insulator, SOI) substrate is perhaps for utilizing deposition or growth technique in the substrate of the class soi structure that contains Si substrate formation insulating barrier and top semiconductor layer.Described semiconductor base 200 comprises that the bottom contains Si semiconductor layer 201, insulating barrier 202 and top and contains Si semiconductor layer 203.The illustrative examples that contains the Si semi-conducting material comprises Si, SiGe, SiC, SiGeC, amorphous Si and their sandwich construction.Described insulating barrier 202 is crystalline state or non-crystal oxide or nitride.

Then, please refer to Fig. 2 B, at the hard mask 210 of described semiconductor base 200 depositions.The deposition process of hard mask for example adopts chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition, chemical solution deposition, evaporation, and perhaps by heat treatment, for example oxidation or nitrogenize forms hard mask.Hard mask comprises oxide, nitride, oxynitride or their multiple layer combination.Preferably, described hard mask 210 is silicon nitride (SiN) material.

Then, please refer to shown in Fig. 2 C and the 2D, remove the hard mask 210 of a part and contain Si semiconductor layer 203 by some processing steps, form hard mask 210 and the fin 220 of patterning.Described processing step is photoetching process and etching.Conventional photoetching process is included in the upper photoresist that forms in hard mask top, and this photoresist that exposes forms required composition, and uses developer that composition is developed.Conventional etching technics comprises dry etching and/or wet etching, and the photoresist of figure behind the composition transferred to hard mask and understructure.Photoresist behind the composition is removed after figure is transferred to hard mask.Preferably, the present invention can adopt the double-pattern photoetching technique, also can adopt the hard mask 210 of electron beam lithography, nanometer embossing or extreme ultraviolet lithography formation patterning and form fin 220.

Next, depositing insulating layer 230 on described insulating barrier 202, fin 220 and described hard mask 210.Preferably, described insulating barrier 230 is silicon dioxide (SiO ₂) material.Insulating barrier 230 can adopt mobile chemical vapour deposition (CVD) (Flowable CVD, FCVD) technique, rotary coating (Spin On Dielectric, SOG) technique or high-density plasma (High Density Plasma, HDP) technique, at insulating barrier 202 and the thicker earth silicon material of hard mask 210 upper surfaces deposition, form thinner earth silicon material at fin 220 sidewalls, shown in the insulating barrier 231 among Fig. 2 E.Insulating barrier 220 can also adopt other depositing operation, forms thicker silicon dioxide layer, shown in the insulating barrier 232 among Fig. 2 F.

Next, please refer to Fig. 2 G, remove the insulating barrier 230 on unnecessary fin 220 sidewalls and hard mask 210 upper surfaces, the part of hard mask 210 and fin 220 is come out, and keep the insulating barrier 220 of a part of fin 220 bottoms.Preferably, remove described insulating barrier 230 by depression (recess) etch step.Preferably, when described insulating barrier 230 is thicker, in the time of for example shown in the insulating barrier 232 among Fig. 2 F, before described recess etch step, also comprise the step of removing the insulating barrier 230 on described hard mask top by cmp (CMP).Preferably, insulating barrier 230 thickness that are retained that are positioned at fin 220 bottoms are 1/10 ~ 1/3 of fin 220 total heights, thereby make fin height (H _Fin) 1/10 ~ 1/3 embed bottom insulation layer.Preferably, when described insulating barrier 230 be silicon dioxide (SiO ₂) during material, adopt based on the wet etching of hydrofluoric acid (HF) and remove insulating barrier 220.At last, remove hard mask 210.Next make grid, source-drain electrode etc., form final multiple gate field effect transistor, above-mentioned technique all is well-known to those skilled in the art, does not here give unnecessary details one by one.

As shown in Figure 3, for make a kind of process chart of multiple gate field effect transistor according to one embodiment of the invention.In step 301, the semiconductor substrate at first is provided, this semiconductor base comprises that the bottom contains Si semiconductor layer, insulating barrier and top and contains the Si semiconductor layer.In step 302, at the hard mask of described semiconductor base deposition.In step 303, form the hard mask of patterning by some steps, and form fin.In step 304, at described insulating barrier, fin and described hard another insulating barrier of mask deposition.In step 305, remove unnecessary insulating barrier, the part of described hard mask and described fin is come out.In step 306, remove hard mask.

The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.

Claims

1. the manufacture method of a multiple gate field effect transistor comprises:

Semiconductor base is provided, and described semiconductor base comprises that the bottom contains Si semiconductor layer, insulating barrier and top and contains the Si semiconductor layer;

Form hard mask at described semiconductor base;

The described hard mask of patterning;

Form fin;

At described insulating barrier, described fin and described hard another insulating barrier of mask deposition;

Remove unnecessary described another insulating barrier, the part of described hard mask and described fin is come out.

2. method according to claim 1, wherein said semiconductor base is silicon-on-insulator.

3. method according to claim 1, wherein said hard mask is silicon nitride.

4. method according to claim 1, wherein the method for the described hard mask of patterning adopts at least a in double-pattern photoetching technique, electron beam lithography, nanometer embossing or the extreme ultraviolet lithography.

5. method according to claim 1, the method that wherein deposits another insulating barrier adopts mobile chemical vapor deposition method, spin coating process or high-density plasma technique.

6. method according to claim 1 wherein adopts the depression etching to remove unnecessary described another insulating barrier.

7. method according to claim 6 wherein also comprised the step of removing described another insulating barrier on described hard mask top by cmp before described recess etch step.

8. method according to claim 1, wherein remove described another insulating barrier after, another thickness of insulating layer that is retained that is positioned at described fin bottom is 1/10 ~ 1/3 of fin total height.

9. method according to claim 1, wherein remove described another insulating barrier after, also comprise the step of removing described hard mask.

10. multiple gate field effect transistor structure comprises:

11. structure according to claim 10, the semiconductor fin height that wherein is partially submerged into insulating barrier is 1/10 ~ 1/3 of semiconductor fin total height.