CN103019624A

CN103019624A - Phase change memory device

Info

Publication number: CN103019624A
Application number: CN2012105338104A
Authority: CN
Inventors: 汪东升; 高鹏; 王海霞
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2012-12-11
Filing date: 2012-12-11
Publication date: 2013-04-03
Anticipated expiration: 2032-12-11
Also published as: CN103019624B

Abstract

The invention provides a phase change memory device, which comprises a memory controller and a memory bank, wherein the memory bank consists of a plurality of nonvolatile phase change memory chips and a volatile DRAM (dynamic random access memory) chip, and the nonvolatile phase change memory chips and the volatile DRAM chip part are respectively connected with the memory controller through respective data buses. Through the adoption of mixed structures of the phase change memory chips and the DRAM chip, the frequently read and written data is placed into the volatile DRAM chip. The reading and writing speed of the DRAM chip is higher than that of the phase change memory chips, and in addition, the writing loss problem does not exist, so the number of average writing times of the phase change memory is reduced, the service life is prolonged, and meanwhile, the whole power consumption of the memory bank is also reduced.

Description

A kind of phase change memory device

Technical field

The present invention relates to the Computer Systems Organization technical field, particularly a kind of phase change memory device.

Background technology

The performance boost speed of calculator memory lags far behind the speed that processor performance promotes.With respect to processor, internal storage access postpones with 5 times speed increment in per ten years, and this system architecture unbalance formed and hindered " the storage wall " that processor performance promotes, thereby so that memory system becomes one of performance bottleneck of whole computer system.In order to address this problem, a lot of new memory techniques are suggested.Phase transition internal memory PCM is exactly one of them.Because the characteristics such as phase transition internal memory has the storage density height, and is non-volatile.Be hopeful to substitute existing DRAM internal memory.

But phase transition internal memory has the shortcoming of the wearing and tearing write, and it is limited namely to write indegree.Under the present technological level, the life-span of average every bit phase transition internal memory memory device is 10 ⁶～10 ⁹Between inferior.How to reduce the emphasis that wearing and tearing become present research that writes of phase transition internal memory.

The method of improving at present the phase transition internal memory wearing and tearing mainly is divided into 3 large classes.The first kind is to write caching method.The method is that the phase transition internal memory module has been added a buffer memory that is made of dram chip.Data buffer storage in the address that this buffer memory will frequently be accessed gets off, until there are new data that it is swapped out.The method can reduce to a certain extent a certain address is frequently write the excessive wear that causes.The Equations of The Second Kind method is to write equilibrium.The method will write the data-mapping of a certain address in other address by address replay firing table.Remap by this, eliminated to a certain extent the fashionable excessive wear that causes is frequently write in a certain address.The 3rd class methods are write-after-read.Namely when writing an address location, read first the numerical value of this unit and compare with value to be written, if identical, then do not write.The method writes to reduce wearing and tearing to the phase transition internal memory chip by eliminating redundancy.But according to experiment, the wearing and tearing of different phase transition internal memory chip chambers still there are differences.This will cause short-board effect, and namely some phase transition internal memory chip is by excessive wear.

Summary of the invention

(1) technical matters to be solved

The objective of the invention is to propose a kind of phase change memory device, this device can reduce and equilibrium writes wearing and tearing to phase transition internal memory, to eliminate the unbalanced wear problem shortcoming in the word of not considering at present.

(2) technical scheme

The invention provides a kind of phase change memory device, this memory device comprises Memory Controller Hub and memory bar, it is characterized in that, described memory bar is comprised of multi-disc phase transition internal memory chip and multi-disc dram chip; Described phase transition internal memory chip part is connected with dram chip and is passed through respectively separately that data bus is connected with Memory Controller Hub.

Preferably, described Memory Controller Hub is divided into two-layer up and down, and lower floor is used for controlling the independent read-write of every a slice DRAM or phase transition internal memory chip; The upper strata is used for the data that buffer memory need to be read and write, and solves the asynchronous arrival of data.

Preferably, it is characterized in that high position data part or low data part in the common stored memory of the phase transition internal memory chip address of described dram chip and equivalent amount, the interposition part in all the other phase transition internal memory chip-stored memory addresss.

Preferably, it is characterized in that described dram chip is corresponding high address under little Tail Model; Corresponding low order address under large Tail Model.

Preferably, the mixing memory bar of described Memory Controller Hub compatible with single passage or hyperchannel form.

A kind of data read-write method based on phase change memory device of the present invention, the method comprises:

S1, when writing internal memory, low level or high position data write dram chip, interposition partial data recording phase change memory chip;

S2, when reading internal storage data, high position data part or low data part in memory address read from dram chip, the interposition part reads from the phase transition internal memory chip.

Preferably, after also being included in certain all period interval behind the step S1 or before system closedown, data in the dram chip are write back to the step in the phase transition internal memory chip of the correspondence that does not have data writing in this cycle.

(3) beneficial effect

The present invention is by adopting the mixed structure of phase transition internal memory chip and dram chip, so that the data that more frequent quilt is read and write are placed in the dram chip.Because the read or write speed of dram chip is higher than phase transition internal memory chip, the read-write power consumption is little, and does not have the loss problem of writing, thus reduced phase transition internal memory on average write indegree, improved the life-span.Also reduced simultaneously the power consumption of memory bar.This framework can reduce and balanced phase transition internal memory be write wearing and tearing simultaneously, eliminates the shortcoming of the unbalanced wearing and tearing in the word of not considering in the present method.

Description of drawings

Fig. 1 is the structural representation of phase change memory device;

Fig. 2 is the data read-write method process flow diagram based on phase change memory device of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments the present invention is described in further details.

The invention provides a kind of phase change memory device, it installs as shown in Figure 1, and this device comprises Memory Controller Hub and memory bar, and wherein, memory bar is comprised of 8 non-volatile phase-change memory chips and 2 volatibility dram chips, is 64 bit bit wides; 8 phase transition internal memory chips partly are connected with Memory Controller Hub by 64 bit bit wide data buss; 2 dram chips are connected with Memory Controller Hub by 6 or 16 bit bit wide data buss; Carry out the transmitting-receiving of control signal.

This phase change memory device also can comprise buffer memory, and buffer memory is connected with Memory Controller Hub by the buffer memory bus.

The read or write speed of dram chip is higher than phase transition internal memory, and the read-write power consumption is little, and does not have the loss problem of writing.

Wherein, Memory Controller Hub is divided into two-layer up and down: lower floor is responsible for the independent read-write control of every a slice DRAM or phase transition internal memory chip; The data that buffer memory need to be read and write are responsible on the upper strata, and solve because the asynchronous arrival problem of the different data of bringing with the phase transition internal memory read-write sequence of DRAM.

Memory Controller Hub can the compatible with single passage or the mixing memory bar of hyperchannel form.

For the indegree of writing of better minimizing phase transition internal memory is arranged, high position data part or low data part in memory address are stored jointly by the phase transition internal memory chip of dram chip and equivalent amount, but can not read and not write simultaneously, the interposition part is by the phase transition internal memory chip-stored.

Wherein dram chip can corresponding arbitrary bit address, and preferred, dram chip is corresponding high address under little Tail Model; Corresponding low order address under large Tail Model.That has reduced like this phase transition internal memory on average writes indegree, has improved the life-span; Also reduced simultaneously the power consumption of memory bar;

The present invention also provides a kind of reading/writing method that reads and writes data based on the computing machine of phase change memory device of the present invention, flow chart of steps as shown in Figure 2, and the method is:

S1, when computing machine is write internal memory, wherein low level or high position data at first write dram chip, and recording phase change memory chip not only has interposition partial data recording phase change memory chip.

Reducing that writing of phase transition internal memory reduced in the indegree and balanced phase transition internal memory being write wearing and tearing, eliminate the shortcoming of unbalanced wearing and tearing in the word of not considering in the present method like this

S2, after certain all period interval or before system closedown, data in the dram chip are write back in the corresponding phase transition internal memory chip namely not to be had in the phase transition internal memory chip of data writing.

S3, when reading internal storage data, high position data part or low data part in memory address read from dram chip, the interposition part reads from the phase transition internal memory chip.

Wherein, in order to improve the security of phase transition internal memory, deliberately so that after the outage storage be not full content, can data in the volatibility dram chip not write back in the corresponding non-volatile phase-change memory chip.This computer data caching method, that has reduced phase transition internal memory on average writes loss, has prolonged the life-span of phase transition internal memory, has reduced power consumption.

The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and replacement, these improvement and replacement also should be considered as protection scope of the present invention.

Claims

1. phase change memory device, this device comprises Memory Controller Hub and memory bar, it is characterized in that, described memory bar is comprised of multi-disc phase transition internal memory chip and multi-disc dram chip; Described phase transition internal memory chip part is connected with dram chip and is passed through respectively separately that data bus is connected with Memory Controller Hub.

2. phase change memory device as claimed in claim 1 is characterized in that, described Memory Controller Hub is divided into two-layer up and down: lower floor is used for controlling the independent read-write of every a slice DRAM or phase transition internal memory chip; The upper strata is used for the data that buffer memory need to be read and write, and solves the asynchronous arrival of data.

3. phase change memory device as claimed in claim 1 is characterized in that the mixing memory bar of described Memory Controller Hub compatible with single passage or hyperchannel form.

4. phase change memory device as claimed in claim 1, it is characterized in that, the phase transition internal memory chip of described dram chip and equivalent amount is mapped as high position data part or the low data part in the memory address, the interposition part in all the other phase transition internal memory chip-stored memory addresss jointly.

5. phase change memory device as claimed in claim 1 is characterized in that described dram chip is corresponding high address under little Tail Model; Corresponding low order address under large Tail Model.

6. data read-write method based on described any phase change memory device of claim 1-5 is characterized in that the method comprises:

S2, when reading internal storage data, high position data in memory address part or low data part read from dram chip, the interposition part reads from the phase transition internal memory chip.

7. method as claimed in claim 6 is characterized in that, after also being included in certain all period interval behind the step S1 or before system closedown, data in the dram chip is write back to the step in the phase transition internal memory chip of the correspondence that does not have data writing in this cycle.