CN103019300B - A kind of clock control and the method and apparatus controlled that resets - Google Patents
A kind of clock control and the method and apparatus controlled that resets Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of clock control and the method and apparatus controlled that resets, wherein method comprises: confirm whether current block has the one in the control of clock signal or the control of reset signal at least, if have, then being numbered according to clock control and the corresponding relation controlled that resets, adding in label table by numbering the identification number obtained; According to identification number and clock control and the corresponding relation controlled that resets, select effective control bit or retain position design clock-control register and reset control register.Software complexity and size of code can be reduced, improve maintainable; Meanwhile, clock is improved and the efficiency controlling to perform that resets.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of clock control and the method and apparatus controlled that resets.
Background technology
The clock control of chip and reset control design case, after chip hardware realizes, carry out the opening of clock and reset by software, close exploitations such as (or effectively, invalid) and control.
The clock control of each module of chip performs according to clock mark (Identity, ID) order, and the reset of each module controls then to perform according to reset ID order.
For clock switch, the controlling functions that reset control etc. are such, during software simulating, usual way needs the ID number value of module as parameter, pass to the bottom function of working control register, ID value just correspond to control bit (BIT) position in certain register.So, need all module controlling functions to be numbered sequence.So, clock ID sorts to all clock control functions, the sequencing table obtained; All reset controlling functions sort by reset ID, the ID sequence list obtained.
Below the process using clock ID and reset ID to carry out control operation is described, it should be noted that the using method of clock ID and reset ID is identical, so do not distinguish it in this example, be all called ID; As shown in Figure 1, idiographic flow is as follows:
101: bottom control function receives an ID value; Also may receive the parameters such as switching manipulation instruction simultaneously;
102: bottom control function obtains register address corresponding to this ID value; The mode obtained can be: judge whether this ID value is more than or equal to the ID value of the BIT0 position of this register, and be less than the ID value of next register BIT0 position, if it is determine that the address of above-mentioned register is recorded, be denoted as address A.
103: bottom control function calculates the difference of the ID value of this ID value and register BIT0 position corresponding to this ID, then according to the BIT position in register corresponding to this ID value of this mathematic interpolation, BIT position B can be denoted as;
104: bottom control function performs corresponding controlling functions according to the BIT position (that is: address A and BIT position B) in the register address obtained and register.Controlling functions can have a lot, such as: switch control rule, reset control.
Inventor finds in the process realizing the embodiment of the present invention, and due in the system of a multimode, clock and reset are not one to one, and therefore clock ID is different with the order of reset ID.According to above method, the realization of clock control needs maintenance clock ID sequence list, when needing to carry out open and close operation to certain clock, the ID of this clock is passed to Clock-Control function.The realization controlled that resets then needs maintenance reset ID sequence list, when needs carry out open and close operation to certain reset, this reset ID is passed to reset control function.If realize clock and reset controlling simultaneously, then need maintenance two to overlap ID table on the one hand, on the other hand, in Clock-Control function and reset control function, the ID value that the acquisition of register address A and the acquisition of BIT position B are carried out is obtained independently; Thus, software complexity and size of code are all comparatively large, and maintainability is also poor; Meanwhile, result in the efficiency controlling to perform low, the long and difficult problem safeguarded of software development time.
Summary of the invention
Embodiments provide a kind of clock control and the method and apparatus controlled that resets, reduce software complexity and size of code, improve maintainable; Meanwhile, improve clock and the efficiency controlling to perform that resets.
Realize clock control and the method controlled that resets, comprising:
Confirm whether current block has the one in the control of clock signal or the control of reset signal at least, if having, being then numbered according to clock control and the corresponding relation controlled that resets, adding in label table by numbering the identification number obtained;
According to identification number and clock control and the corresponding relation controlled that resets, select effective control bit or retain position design reset control register and clock-control register.
Clock control and the device controlled that resets, comprising:
Signal confirmation unit, for confirming whether current block has the one in the control of clock signal or the control of reset signal at least;
For signal confirmation unit, label table maintenance unit, confirms that result is for having, be then numbered according to clock control and the corresponding relation controlled that resets, and adds in label table by numbering the identification number obtained;
Register design unit, for according to identification number and clock control and the corresponding relation controlled that resets, selects effective control bit or retains position design clock-control register and reset control register.
As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages: retain position by increasing in a register, ensures to use same ID value to may be used for clock and reset controlling, thus reduces software complexity and size of code, improves maintainable; Meanwhile, clock is improved and the efficiency controlling to perform that resets.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is prior art clock and reset control flow schematic diagram;
Fig. 2 is embodiment of the present invention clock and reset control flow schematic diagram;
Fig. 3 is embodiment of the present invention apparatus structure schematic diagram;
Fig. 4 is embodiment of the present invention apparatus structure schematic diagram;
Fig. 5 is embodiment of the present invention register schematic diagram.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Clock control and the method controlled that resets, as shown in Figure 2, comprising:
201: confirm whether current block has the one in the control of clock signal or the control of reset signal at least;
202: if having, being then numbered according to clock control and the corresponding relation controlled that resets, adding in label table by numbering the identification number obtained;
Be understandable that, if do not have control or the reset signal of clock signal, so this method flow process can perform.
Alternatively, in above-mentioned 202, be numbered according to clock control and the corresponding relation controlled that resets, add in label table by numbering the identification number obtained, comprise: if having a clock control and the control that resets, then by the mark ID value in label table that above-mentioned identification number controls as this clock and reset, the identification number in label table adopts increasing or decreasing numbering to obtain; If have a clock control but the control that do not reset, then by above-mentioned identification number as the ID value of clock control in label table, identification number in label table adopts increasing or decreasing numbering to obtain; If have one to reset control but do not have clock control, then above-mentioned identification number is controlled the ID value in label table as reset, the identification number in label table adopts increasing or decreasing numbering to obtain.
Alternatively, if current block has two or more clock signal and the reset signal with corresponding relation; Then the above-mentioned corresponding relation according to clock control and the control that resets is numbered, numbering is added in label table, comprise: the clock signal and reset signal that there is corresponding relation are divided into N number of group, carry out to each group the identification number that serial number obtains each group, and the identification number of each group of current block is joined in label table; Wherein, N be greater than 1 natural number.
203: according to identification number and clock control and the corresponding relation controlled that resets, select effective control bit or retain position design reset control register and clock-control register.
Alternatively, in above-mentioned 203, according to identification number and clock control and the corresponding relation controlled that resets, select effective control bit or retain position design reset control register and clock-control register, comprise: if having a clock signal and a reset signal to the control of current block, then corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to efficient clock control bit, corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to active homing control bit; If have a clock signal and there is no reset signal to the control of current block, then corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to efficient clock control bit, corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to and retains position; If there is no clock signal and have a reset signal to the control of current block, then corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to active homing control bit, corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to and retains position.
Alternatively, above-mentioned corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to efficient clock control bit, comprise: select an effective control BIT position, send to clock-control register, by clock-control register, corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to efficient clock control bit; The above-mentioned reservation position that is set to BIT position corresponding for clock-control register corresponding for identification number comprises: select one to retain BIT position, send to clock-control register, by clock-control register BIT position corresponding for clock-control register corresponding to above-mentioned identification number is set to and retains position.
Alternatively, above-mentioned corresponding for the reset control register corresponding with an identification number BIT position is set to active homing control bit, comprise: choose an effective control BIT position, send to reset control register, by reset control register, corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to active homing control bit; Corresponding for the reset control register corresponding with an identification number BIT position is set to reservation position to comprise: select one to retain BIT position, send to reset control register, by reset control register corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to and retains position.
Further, said method comprises: use the identification number in label table to carry out the control of clock and reset.Identification number in above-mentioned use label table carries out the control of clock and reset, comprise: receive a clock or the ID value controlled that resets, judge the size of the ID value of above-mentioned ID value and each clock or reset control register lowest order or most significant digit position, navigate to the address of register; And calculate the difference of the above-mentioned ID value clock corresponding with above-mentioned ID value or the lowest order of reseting register or the ID value of most significant digit position, and locate the BIT position of above-mentioned ID value in the clock or reseting register of above-mentioned ID value correspondence according to above-mentioned difference, then perform clock or the control that resets.It should be noted that, adopt method corresponding to Fig. 1 can reach the technique effect reached required for the embodiment of the present invention.This step just adopts the embody rule of the scheme of Fig. 1, and this application should not be construed as the step that must perform.
After using said method to complete all resume module, unified ID label table can be produced in step 202, for software development, in step 203 one or more clock-control register be defined, to one or more reset control register definition, chip development is can be used for use.
Above technical scheme, in software development and chip development process, an ID sequence number table can be shared, the address of clock and reset control register can be navigated to by ID sequence number, the BIT position in register is navigated to by the relative difference between ID, 0 or write 1 and just can realize open and close (or effective, invalid) control operation is write to corresponding BIT, greatly can simplify complexity and the size of code of software simulating.
Above embodiment, retains position by increasing in a register, ensures to use same ID value to may be used for clock and reset controlling, thus reduces software complexity and size of code, improves maintainable; Meanwhile, clock is improved and the efficiency controlling to perform that resets.
The embodiment of the present invention additionally provides a kind of clock control and the device controlled that resets, and as shown in Figure 3, comprising:
Signal confirmation unit 301, for confirming whether current block has the one in the control of clock signal or the control of reset signal at least;
For signal confirmation unit 301, label table maintenance unit 302, confirms that result is for having, be then numbered according to clock control and the corresponding relation controlled that resets, and adds in label table by numbering the identification number obtained;
Register design unit 303, for according to identification number and clock control and the corresponding relation controlled that resets, selects effective control bit or retains position design clock-control register and reset control register.
Alternatively, above-mentioned label table maintenance unit 302, if specifically for having a clock control and the control that resets, then by the mark ID value in label table that above-mentioned identification number controls as this clock and reset, the identification number in label table adopts increasing or decreasing to number and obtains; If have a clock control but the control that do not reset, then by above-mentioned identification number as the ID value of clock control in label table, identification number in label table adopts increasing or decreasing numbering to obtain; If have one to reset control but do not have clock control, then above-mentioned identification number is controlled the ID value in label table as reset, the identification number in label table adopts increasing or decreasing numbering to obtain.
Alternatively, if current block has two or more clock signal and the reset signal with corresponding relation;
Above-mentioned label table maintenance unit 302, specifically for the clock signal and reset signal that there is corresponding relation are divided into N number of group, carry out to each group the identification number that serial number obtains each group, and joins in label table by the identification number of each group of current block; Wherein, N be greater than 1 natural number.
Alternatively, above-mentioned register design unit 303, if specifically for having a clock signal and a reset signal to the control of current block, then corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to efficient clock control bit, corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to active homing control bit; If have a clock signal and there is no reset signal to the control of current block, then corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to efficient clock control bit, corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to and retains position; If there is no clock signal and have a reset signal to the control of current block, then corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to active homing control bit, corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to and retains position.
Alternatively, above-mentioned register design unit 303, for corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to efficient clock control bit, comprise: select an effective control BIT position, send to clock-control register, by clock-control register, corresponding for the clock-control register corresponding with above-mentioned identification number BIT position is set to efficient clock control bit;
Above-mentioned register design unit 303, comprise for BIT position corresponding for clock-control register corresponding for identification number being set to reservation position: select one to retain BIT position, send to clock-control register, by clock-control register BIT position corresponding for clock-control register corresponding to above-mentioned identification number is set to and retains position.
Alternatively, above-mentioned register design unit 303, for corresponding for the reset control register corresponding with an identification number BIT position is set to active homing control bit, comprise: choose an effective control BIT position, send to reset control register, by reset control register, corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to active homing control bit;
Above-mentioned register design unit 303, comprise for corresponding for the reset control register corresponding with an identification number BIT position being set to reservation position: select one to retain BIT position, send to reset control register, by reset control register corresponding for the reset control register corresponding with an above-mentioned identification number BIT position is set to and retains position.
Further, as shown in Figure 4, said apparatus also comprises:
Clock-reset control module 401, for the control using the identification number in label table to carry out clock and reset.
More specifically, clock-reset control module 401, specifically for receiving a clock or the ID value controlled that resets, judging the size of the ID value of above-mentioned ID value and each clock or reset control register lowest order or most significant digit position, navigating to the address of register; And calculate the difference of the above-mentioned ID value clock corresponding with above-mentioned ID value or the lowest order of reseting register or the ID value of most significant digit position, and locate the BIT position of above-mentioned ID value in the clock or reseting register of above-mentioned ID value correspondence according to above-mentioned difference, then perform clock or the control that resets.
Above embodiment, retains position by increasing in a register, ensures to use same ID value to may be used for clock and reset controlling, thus reduces software complexity and size of code, improves maintainable; Meanwhile, improve clock and the efficiency controlling to perform that resets, reduce software development time.
Below provide the example that uses the execution result of said method or device.As shown in Figure 5, show two clock-control registers, be respectively: clock-control register 1, clock-control register 2; With two reset control registers, be respectively: reset control register 1, reset control register 2; From left to right be followed successively by BIT31 ~ BIT0 and module K ~ module 1, and module W is to module N; Module W ~ module K+1; In the module of clock-control register 2 correspondence, wherein show the corresponding relation of this module and clock, such as: module N (clock 3), module N (clock 2), module N (clock 1), and retain position.In reset control register 1 or 2, there is display to retain position.According to the method for the embodiment of the present invention, the identification number table of generation, as shown in table 1:
Table 1
| Sequence number | Clock control explanation | Reset and control explanation |
| X | Module W | Module W |
| X-1 | Module W-1 | Module W-1 |
……
| J+5 | Module N (clock 3) | Retain |
| J+4 | Module N (clock 2) | Retain |
| J+3 | Module N (clock 1) | Module N |
| J+2 | Retain | Module K+1 |
| J+1 | Module K | Module K |
| J | Module K-1 | Module K-1 |
……
| 3 | Module 4 | Retain |
| 2 | Retain | Module 3 |
| 1 | Module 2 | Retain |
| 0 | Module 1 | Module 1 |
According to the method for the embodiment of the present invention according to the register design of Fig. 5, table 1 can be obtained.As can be seen from Table 1, unified numbering is carried out for clock and reset ID, do not had the position of corresponding relation to retain position occupy-place.
For module 1, clock control and the control that resets all exist, and have one-to-one relationship, in the identification number table of software application, take sequence number 0, and a BIT position is respectively taken in " clock-control register 1 " and " reset control register 1 " of chip design, be all the position of BIT0;
For module 2, only has clock control, do not reset control, then software application-" take sequence number 1 in identification number table; and take an effective control bit in " clock-control register 1 " of chip design; in " reset control register 1 ", take a BIT position, being labeled as and retaining position, is all the position of BIT1;
For module 3, only having resets controls, there is no clock control, then in the identification number table of software application, take sequence number 2, and an effective control bit is taken in " the reset control register 1 " of chip design, in " clock-control register 1 ", take a BIT position, being labeled as and retaining position, is all the position of BIT2;
For module N, there are 3 clock controls, 1 control that resets, then in the identification number table of software application, take sequence number J+3, J+4, J+5, and 3 effective control bits are taken in " clock-control register 2 " of chip design, for BIT1, BIT2, BIT3,3 BIT positions are taken in " reset control register 2 ", BIT1 is effective control bit, BIT2 and BIT3 is labeled as and retains position, so all occupies 3 BIT positions.
It should be noted that in above-mentioned subscriber equipment and base station embodiment, included unit is carry out dividing according to function logic, but is not limited to above-mentioned division, as long as can realize corresponding function; In addition, the concrete title of each functional unit, also just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
In addition, one of ordinary skill in the art will appreciate that all or part of step realized in above-mentioned each embodiment of the method is that the hardware that can carry out instruction relevant by program completes, corresponding program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.
These are only the present invention's preferably embodiment; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the embodiment of the present invention discloses, the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (11)
1. clock control and the method controlled that resets, is characterized in that, comprising:
Confirm whether current block has the one in the control of clock signal or the control of reset signal at least, if having, being then numbered according to clock control and the corresponding relation controlled that resets, adding in label table by numbering the identification number obtained;
According to identification number and clock control and the corresponding relation controlled that resets, select effective control bit or retain position design clock-control register and reset control register;
Wherein, the described corresponding relation according to clock control and the control that resets is numbered, and adding in label table, comprising numbering the identification number obtained:
If have a clock control and the control that resets, then by the mark ID value in label table that described identification number controls as this clock and reset, the identification number in label table adopts increasing or decreasing to number and obtains;
If have a clock control but the control that do not reset, then by described identification number as the ID value of clock control in label table, identification number in label table adopts increasing or decreasing numbering to obtain;
If have one to reset control but do not have clock control, then described identification number is controlled the ID value in label table as reset, the identification number in label table adopts increasing or decreasing numbering to obtain;
Wherein, described according to identification number and clock control and the corresponding relation controlled that resets, select effective control bit or retain position design clock-control register and reset control register, comprising:
If have a clock signal and a reset signal to the control of current block, then corresponding for the clock-control register corresponding with described identification number bit BIT position is set to efficient clock control bit, corresponding for the reset control register corresponding with a described identification number BIT position is set to active homing control bit;
If have a clock signal and there is no reset signal to the control of current block, then corresponding for the clock-control register corresponding with described identification number BIT position is set to efficient clock control bit, corresponding for the reset control register corresponding with a described identification number BIT position is set to and retains position;
If there is no clock signal and have a reset signal to the control of current block, then corresponding for the reset control register corresponding with a described identification number BIT position is set to active homing control bit, corresponding for the clock-control register corresponding with described identification number BIT position is set to and retains position.
2. method according to claim 1, is characterized in that, if current block has two or more clock control and resetting with corresponding relation to control; Then the described corresponding relation according to clock control and the control that resets is numbered, and numbering is added in label table, comprising:
The clock signal and reset signal that there is corresponding relation are divided into N number of group, carry out to each group the identification number that serial number obtains each group, and the identification number of each group of current block is joined in label table; Wherein, N be greater than 1 natural number.
3. method according to claim 1, is characterized in that, described corresponding for the clock-control register corresponding with described identification number bit BIT position is set to efficient clock control bit, comprising:
Select an effective control BIT position, send to clock-control register, by clock-control register, corresponding for the clock-control register corresponding with described identification number bit BIT position is set to efficient clock control bit;
The described reservation position that is set to BIT position corresponding for clock-control register corresponding for identification number comprises:
Select one to retain BIT position, send to clock-control register, by clock-control register BIT position corresponding for clock-control register corresponding to described identification number is set to and retains position.
4. method according to claim 1, is characterized in that, described corresponding for the reset control register corresponding with an identification number BIT position is set to active homing control bit, comprising:
Choose an effective control BIT position, send to reset control register, by reset control register, corresponding for the reset control register corresponding with a described identification number BIT position is set to active homing control bit;
Corresponding for the reset control register corresponding with an identification number BIT position is set to reservation position to comprise:
Select one to retain BIT position, send to reset control register, by reset control register corresponding for the reset control register corresponding with a described identification number BIT position is set to and retains position.
5. method according to Claims 1-4 any one, is characterized in that, also comprise: use the identification number in label table to carry out the control of clock and reset.
6. method according to claim 5, it is characterized in that, the identification number in described use label table carries out the control of clock and reset, comprising:
Receive a clock or the ID value controlled that resets, judge the size of the ID value of above-mentioned ID value and each clock or reset control register lowest order or most significant digit position, navigate to the address of register; And calculate the difference of the described ID value clock corresponding with described ID value or the lowest order of reset control register or the ID value of most significant digit position, and locate the BIT position of described ID value in the clock or reseting register of described ID value correspondence according to described difference, then perform clock or the control that resets.
7. clock control and the device controlled that resets, is characterized in that, comprising:
Signal confirmation unit, for confirming whether current block has the one in the control of clock signal or the control of reset signal at least;
For signal confirmation unit, label table maintenance unit, confirms that result is for having, be then numbered according to clock control and the corresponding relation controlled that resets, and adds in label table by numbering the identification number obtained;
Register design unit, for according to identification number and clock control and the corresponding relation controlled that resets, selects effective control bit or retains position design clock-control register and reset control register;
Wherein, described label table maintenance unit, if specifically for having a clock control and the control that resets, then by the mark ID value in label table that described identification number controls as this clock and reset, the identification number in label table adopts increasing or decreasing to number and obtains; If have a clock control but the control that do not reset, then by described identification number as the ID value of clock control in label table, identification number in label table adopts increasing or decreasing numbering to obtain; If have one to reset control but do not have clock control, then described identification number is controlled the ID value in label table as reset, the identification number in label table adopts increasing or decreasing numbering to obtain;
Wherein, described register design unit, if specifically for having a clock signal and a reset signal to the control of current block, then corresponding for the clock-control register corresponding with described identification number bit BIT position is set to efficient clock control bit, corresponding for the reset control register corresponding with a described identification number BIT position is set to active homing control bit; If have a clock signal and there is no reset signal to the control of current block, then corresponding for the clock-control register corresponding with described identification number BIT position is set to efficient clock control bit, corresponding for the reset control register corresponding with a described identification number BIT position is set to and retains position; If there is no clock signal and have a reset signal to the control of current block, then corresponding for the reset control register corresponding with a described identification number BIT position is set to active homing control bit, corresponding for the clock-control register corresponding with described identification number BIT position is set to and retains position.
8. device according to claim 7, is characterized in that, if current block has two or more clock signal and the reset signal with corresponding relation;
Described label table maintenance unit, specifically for the clock signal and reset signal that there is corresponding relation are divided into N number of group, carry out to each group the identification number that serial number obtains each group, and joins in label table by the identification number of each group of current block; Wherein, N be greater than 1 natural number.
9. device according to claim 7, it is characterized in that, described register design unit, for corresponding for the clock-control register corresponding with described identification number bit BIT position is set to efficient clock control bit, comprise: select an effective control BIT position, send to clock-control register, by clock-control register, corresponding for the clock-control register corresponding with described identification number bit BIT position is set to efficient clock control bit;
Described register design unit, comprise for BIT position corresponding for clock-control register corresponding for identification number being set to reservation position: select one to retain BIT position, send to clock-control register, by clock-control register BIT position corresponding for clock-control register corresponding to described identification number is set to and retains position.
10. device according to claim 7, is characterized in that,
Described register design unit, for corresponding for the reset control register corresponding with an identification number BIT position is set to active homing control bit, comprise: choose an effective control BIT position, send to reset control register, by reset control register, corresponding for the reset control register corresponding with a described identification number BIT position is set to active homing control bit;
Described register design unit, comprise for corresponding for the reset control register corresponding with an identification number BIT position being set to reservation position: select one to retain BIT position, send to reset control register, by reset control register corresponding for the reset control register corresponding with a described identification number BIT position is set to and retains position.
11. according to claim 7 to 10 any one device, it is characterized in that, also comprise:
Clock-reset control module, for the control using the identification number in label table to carry out clock and reset.
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| CN109857234B (en) * | 2018-12-28 | 2021-10-19 | 曙光信息产业(北京)有限公司 | Online resetting device of real-time clock of blade server |
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| CN103019300A (en) | 2013-04-03 |
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