CN102983169B - The double-gate semiconductor devices of high-breakdown-voltage - Google Patents
The double-gate semiconductor devices of high-breakdown-voltage Download PDFInfo
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- CN102983169B CN102983169B CN201210529769.3A CN201210529769A CN102983169B CN 102983169 B CN102983169 B CN 102983169B CN 201210529769 A CN201210529769 A CN 201210529769A CN 102983169 B CN102983169 B CN 102983169B
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Abstract
A kind of double-gate semiconductor devices provides following high-breakdown-voltage, and this puncture voltage allows the large skew to the useful output voltage of power application.This double-gate semiconductor devices can be considered as comprising the dual-gated device of mos gate pole and knot grid, wherein tie grid biased can be the function of the grid voltage of mos gate pole.The puncture voltage of double-gate semiconductor devices is the puncture voltage sum of mos gate pole and knot grid.Because independent knot grid has intrinsic high-breakdown-voltage, so the puncture voltage of double-gate semiconductor devices is greater than the puncture voltage of independent mos gate pole.Double-gate semiconductor devices compared with conventional crystalline tube device except also providing the RF ability of improvement except the operability of more high power levels.
Description
The application is the applying date is on February 13rd, 2008, enter the divisional application that National Phase in China day is on September 21st, 2010, application number is 200880128225.8, denomination of invention is the PCT application of " double-gate semiconductor devices of high-breakdown-voltage ".
Technical field
The present invention generally relates to semiconductor device.More specifically, the present invention relates to a kind of semiconductor device configured for power application.
Background technology
For radio frequency (RF) power application and complementary metal oxide semiconductors (CMOS) (CMOS) device that designs, to require traditionally between the puncture voltage that the RF performance test improved is higher compromise.The RF performance of cmos device such as can be improved by reducing grid physical dimension (such as by using short channel length).But less grid physical dimension reduces the puncture voltage of cmos device.Because the puncture voltage reduced limits the voltage swing that can obtain in the output of cmos device, so such cmos device is not too useful in power application in amplifier configuration.
For in a kind of scheme of break-down voltage problem, voltage swing is less in the hope of current drives is larger can to design cmos device.But more large driven current density may require that the width of the transistor in cmos device makes greatly, therefore brings undesirable capacity load to drive circuit.
Another program for break-down voltage problem uses Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor.Ldmos transistor has drift region between active region and drain electrode.Drift region adulterates for slight and stand the maximum voltage amplitude of oscillation.Because the doping content in drift region requires restriction by puncture voltage, the higher all-in resistance (being called on-state resistance) of more high-breakdown-voltage and the drain current flowing to source terminal from draining so LDMOS device is traded off.
Another program for break-down voltage problem uses has device that is thicker and the more substrate of high resistivity.These devices can provide more high voltage capability still also to introduce higher on-state losses.These devices comprise reduction surface field (RESURF) device, and wherein the depleted region of substrate diode and the depleted region of transverse diode interact to reduce surface field.In these devices, because the transverse direction of depleted region broadens, voltage breakdown increases.
Therefore need a kind ofly to provide the RF ability of improvement and the semiconductor device of more high-power high-breakdown-voltage compared with conventional semiconductor devices.
Summary of the invention
Embodiments of the invention comprise a kind of method of the double-gate semiconductor devices for controlling high-breakdown-voltage.The method comprises the double-gate semiconductor devices forming high-breakdown-voltage, and this device is included in the metal-oxide semiconductor (MOS) grid on substrate and the knot grid substantially in well area, and this well area substantially in the substrate.The method also comprises: substantially in well area, form drain electrode; Substantially source electrode is formed in the substrate; And control circuit is coupled to knot grid, this control circuit effective resistance be configured to by changing knot grid controls the electric current flowed between drain electrode and source electrode.
According to another embodiment of the present invention, a kind of method comprises the double-gate semiconductor devices being controlled high-breakdown-voltage by following operation: form the substrate with the first doping type; Substantially form source electrode in the substrate, this source electrode has the second doping type; Form first grid being arranged on the oxide skin(coating) on substrate; Formed substantially in the substrate and there is the well area of the second doping type; Substantially in well area, form second grid, this second grid has the first doping type; And substantially in well area, forming drain electrode, this drain electrode has the second doping type.The method also comprises: control circuit is coupled to second grid, this control circuit is configured to the double-gate semiconductor devices being controlled high-breakdown-voltage by the effective resistance changed between drain electrode in well area and source electrode, and wherein effective resistance controls the electric current that flows between drain electrode in well area and source electrode.
Embodiments of the invention comprise a kind of double-gate semiconductor devices of the high-breakdown-voltage for power application, and this device comprises: substrate, have the first doping type; Source electrode, is formed in substrate substantially, and this source electrode has the second doping type; First grid, is formed on the oxide skin(coating) that is arranged on substrate; Well area, has the second conduction type and is substantially formed in substrate; And drain electrode, be substantially formed in well area, this drain electrode has the second doping type.Embodiments of the invention also comprise: second grid, are substantially formed in well area, and this second grid has the first doping type, and the current response wherein flowed in the double-gate semiconductor devices of high-breakdown-voltage is in the voltage applied to second grid.
Accompanying drawing explanation
Element in accompanying drawing simplifies for asking and illustrate for purpose of brevity, and not drawn on scale.The size of some elements can expand to contribute to improving the understanding to various embodiments of the invention relative to other element to some extent.
Fig. 1 illustrates the example cross-section comprising mos gate pole, tie the double-gate semiconductor devices in grid N+ region adjacent with two.
Fig. 2 illustrates the example cross-section of the double-gate semiconductor devices comprising two N+ regions that mos gate pole, knot grid and use conducting shell are coupled.
Fig. 3 illustrates and comprises mos gate pole and tie grid and be arranged at the example cross-section of double-gate semiconductor devices in the single N+ region between mos gate pole and knot grid.
Fig. 4 illustrates the example cross-section of the double-gate semiconductor devices of the Fig. 3 be in the second pattern of operation.
Fig. 5 illustrates the exemplary circuit figure of the double-gate semiconductor devices of Fig. 1 to Fig. 2.
Fig. 6 illustrates the example cross-section of the double-gate semiconductor devices comprising mos gate pole and knot grid.
Embodiment
A kind of double-gate semiconductor devices provides following high-breakdown-voltage, and this puncture voltage allows the large skew to the useful output voltage of power application.This double-gate semiconductor devices can be considered as comprising the dual-gated device of metal-oxide semiconductor (MOS) (MOS) grid and knot grid, wherein tie grid biased can be the function of the grid voltage of mos gate pole.The puncture voltage of double-gate semiconductor devices is the puncture voltage sum of mos gate pole and knot grid.Because independent knot grid has intrinsic high-breakdown-voltage, so the puncture voltage of double-gate semiconductor devices is higher than the puncture voltage of independent mos gate pole.
Double-gate semiconductor devices compared with conventional complimentary metal oxide semiconductor (CMOS) device except also providing the RF ability of raising except the operability of more high power levels.This double-gate semiconductor devices can use semiconductor fabrication techniques known in the art to come substantially to make on substrate and/or in substrate, and can use the standard manufacture craft for CMOS and logical device, wherein little to the amendment of technological process.
Mos gate extremely can comprise following metal-oxide-semiconductor structure, and this structure revises the CHARGE DISTRIBUTION in semiconductor structure when voltage puts on mos gate pole, therefore control the transport properties of semiconductor structure.Work can be carried out as the grid of electric control or switch in mos gate pole therefore.This class grid can be found in mos field effect transistor (MOSFET) device.Knot grid comprise the raceway groove of semi-conducting material as lower area, this region has the doping characteristic contrary with the doping characteristic in all the other regions of raceway groove, thus the CHARGE DISTRIBUTION when applying voltage to knot grid in raceway groove is modified and controls the transport properties of raceway groove thus.Therefore knot grid can carry out work as the grid of electric control or switch.This class grid can be found in junction field effect transistor (JFET).The effective resistance of knot grid is by the resistance of the voltage-controlled raceway groove of knot grid.
Can be produced as follows double-gate semiconductor devices, this device comprises one or more injection zone between mos gate pole and knot grid.With comprise the embodiment of one or more injection zone between mos gate pole with knot grid compared with, between mos gate pole and knot grid, the more high spatial Density and distribution of double-gate semiconductor devices can be provided for without the embodiment of injection zone.Except being modified in the depleted region between mos gate pole raceway groove and drift region, the operating principle of these various embodiments is similar.
Fig. 1 illustrates the example cross-section comprising mos gate pole, tie the double-gate semiconductor devices of grid N+ region (that is, injection zone) adjacent with two.Double-gate semiconductor devices 100 can use semiconductor fabrication techniques known in the art to be formed by the region of doped silicon, polysilicon, metal and insulating barrier and/or layer.Double-gate semiconductor devices 100 comprises P-substrate 110, the N-trap 120 be formed in P-substrate 110, N+ source electrode 130, grid 140, oxide skin(coating) 150, N+ region 160, N+ region 162, P+ grid 170 and N+ drain electrode 180.As used herein, "+" symbol shows the strong doping (such as N+ shows that N-type is adulterated by force) of shown conduction type, and "-" symbol shows the weak doping (such as P-shows P type weak doping) of shown conduction type.
The signal of telecommunication is as V
g1with control voltage V
g2grid 140 and P+ grid 170 can be coupled to respectively.The signal of telecommunication also can use additional polysilicon layer (not shown) or metal level (not shown) to be coupled to N+ source electrode 130, N+ region 160, N+ region 162 and N+ drain electrode 180, and these layers use semiconductor fabrication techniques known in the art to be arranged at N+ source electrode 130, N+ region 160, N+ region 162 and N+ and drain on 180 respective surfaces.
Double-gate semiconductor devices 100 comprises the N-type MOS field-effect transistor (also referred to as N-channel MOS FET) formed by P-substrate 110, N+ source electrode 130 and N+ region 160, grid 140 and oxide skin(coating) 150.Double-gate semiconductor devices 100 also comprises the N channel junction field-effect transistors (also referred to as N-type JFET) formed by P-substrate 110, N-trap 120, N+ region 162, P+ grid 170 and N+ drain electrode 180.In this embodiment, N+ region 160 is adjacent with N+ region 162, and N+ region 162 is arranged in N-trap 120 substantially.
As selection, the element that can configure double-gate semiconductor devices 100 makes double-gate semiconductor devices 100 comprise P type mos gate pole, and this grid comprises P channel junction grid.In such embodiments, some doped silicon regions and/or layer can have different doping according to semiconductor fabrication techniques known in the art.
Can think that double-gate semiconductor devices 100 operates in two patterns.Shown in Fig. 1, first mode is by V
g1> threshold voltage V
thwith | V
g2-V
pI| ≈ 0 (i.e. V
g2-V
pIabsolute value be about 0) show.V
g1the voltage at grid 140, V
g2the voltage at P+ grid 170, V
ththe threshold voltage of grid 140, and V
pIthe voltage in N+ region 162.In a first mode, apply to be greater than V to grid 140
thvoltage V
g1make mos gate pole " conducting ".Control voltage V is applied to P+ grid 170
g2knot gate bias is made to be at control voltage V
g2with the voltage V in N+ region 162
pIbetween there is low potential difference.Therefore P+ grid 170 presents the low resistance R to current flowing
on.In a first mode, semiconductor device 100 to drain conduction current between 180 at N+ source electrode 130 and N+.In a second mode, semiconductor device 100 non-conducting electric current.
Get back to Fig. 1, in a second mode, apply negative control voltage V to P+ grid 170
g2, and (not shown) in the depleted region under P+ grid 170 extends in N-trap 120 raceway groove.As the control voltage V applied to P+ grid 170
g2make | V
g2-V
pI| be greater than pinch-off voltage V
offtime, raceway groove is fully-depleted under P+ grid 170, and no current drains between 180 in N+ region 162 and N+ and flows.Similarly, in a second mode, no current drains between 180 at N+ source electrode 130 and N+ and flows.
As the control voltage V applied to P+ grid 170
g2make | V
g2-V
pI| time ≈ 0 (corresponding to first mode), raceway groove is open, and the electric current of majority carrier can drain between 180 in N+ region 162 and N+ and flows.The behavior of P+ grid 170 (knot grid) therefore can be equivalent to following variable resistance, and this resistor exists | V
g2-V
pI| > V
offin time, has to drain at N+ source electrode 130 and N+ and to allow between 180 seldom or the high effective resistance R of no current flows
offand | V
g2-V
pI| there is during ≈ 0 the low effective resistance R allowing maximum current flowing
on.
Double-gate semiconductor devices 100 can comprise and has two grid device, wherein at the control voltage V of P+ grid 170 (knot grid)
g2can be the voltage V at grid 140 (mos gate pole)
g1function.The control circuit described with reference to Fig. 5 can be used, by mos gate pole and knot grid simultaneously all dynamic bias in " conducting " state or " cut-off " state.
High effective resistance R in the second pattern of operation
offpermission P+ grid 170 maintains high voltage and the voltage potential be limited between grid 140 and N+ region 160 is less than mos gate pole puncture voltage.Puncture voltage due to double-gate semiconductor devices 100 is the puncture voltage sum of mos gate pole and P+ grid 170, so the intrinsic high-breakdown-voltage of P+ grid 170 provides the high-breakdown-voltage of double-gate semiconductor devices 100.
Control voltage V
g2control circuit can be used regulate and can pinch-off voltage V be depended on
off.Control circuit can comprise and being configured to the RF signal coupling from grid 140 to the capacitor (not shown) of P+ grid 170.In order to be limited in the distance between grid 140 and P+ grid 170, the multiple parallel laminated metal layer between grid 140 with P+ grid 170 can be utilized to realize this capacitor.
Fig. 2 illustrates the example cross-section of the double-gate semiconductor devices comprising two N+ regions that mos gate pole, knot grid and use conducting shell are coupled.Double-gate semiconductor devices 200 can use semiconductor fabrication techniques known in the art to be formed by the region of doped silicon, polysilicon, metal and insulating barrier and/or layer.
Double-gate semiconductor devices 200 comprises P-substrate 110, the N-trap 120 be formed in P-substrate 110, N+ source electrode 130, grid 140, oxide skin(coating) 150, N+ region 260, N+ region 265, conducting shell 265, P+ grid 170 and N+ drain electrode 180.Conducting shell 265 can be polysilicon layer, metal level or another conducting shell known in the art.As shown in Figure 2, N+ region 260 and N+ region 262 are by the region disconnecting of P-substrate 110, and N+ region 262 is arranged in N-trap 120 substantially.
As discussed with reference to double-gate semiconductor devices 200 here, the signal of telecommunication is as V
g1with control voltage V
g2grid 140 and P+ grid 170 can be coupled to respectively.The signal of telecommunication also can use additional polysilicon layer (not shown) or metal level (not shown) to be coupled to N+ source electrode 130, N+ region 260, N+ region 262 and N+ drain electrode 180, and these layers use semiconductor fabrication techniques known in the art to be arranged at N+ source electrode 130, N+ region 260, N+ region 262 and N+ and drain on 180 respective surfaces.
Double-gate semiconductor devices 200 comprises the N-type MOSFET formed by P-substrate 110, N-trap 120, N+ source electrode 130 and N+ region 260, grid 140 and oxide skin(coating) 150.Double-gate semiconductor devices 200 also comprises the N raceway groove JFET formed by P-substrate 110, N-trap 120, N+ region 262, P+ grid 170 and N+ drain electrode 180.In this embodiment, conducting shell 265 is used to be coupled N+ region 260 and N+ region 262.
As selection, the element that can configure double-gate semiconductor devices 200 makes double-gate semiconductor devices 200 comprise to comprise the P type mos gate pole of P channel junction grid or comprise the N-type mos gate pole of P channel junction grid or comprise the P type mos gate pole of N channel junction grid.In such embodiments, some doped silicon regions and/or layer can have different doping according to semiconductor fabrication techniques known in the art.
Can think and operate like double-gate semiconductor devices 200 and two Pattern Class described with reference to Fig. 1 here.First mode is by V
g1> threshold voltage V
thwith | V
g2-V
pI| ≈ 0 shows, wherein V
pIthe voltage in N+ region 262.In a first mode, apply to be greater than V to grid 140
thvoltage V
g1make mos gate pole " conducting ".Control voltage V is applied to P+ grid 170
g2knot gate bias is made to be at control voltage V
g2with the voltage V in N+ region 262
pIbetween there is low potential difference.Therefore P+ grid 170 presents the low resistance R to current flowing
on.In a first mode, semiconductor device 200 to drain conduction current between 180 at N+ source electrode 130 and N+.In a second mode, semiconductor device 200 non-conducting electric current.
When applying control voltage V to P+ grid 170
g2make | V
g2-V
pI| time ≈ 0 (corresponding to first mode), raceway groove is open, and the electric current of majority carrier can drain between 180 in N+ region 262 and N+ and flows.The behavior of P+ grid 170 (knot grid) therefore can be equivalent to following variable resistance, and this resistor exists | V
g2-V
pI| > V
offin time, has to drain at N+ source electrode 130 and N+ and to allow between 180 seldom or the high effective resistance R of no current flows
offand | V
g2-V
pI| there is during ≈ 0 the low effective resistance R allowing maximum current flowing
on.
Double-gate semiconductor devices 200 can comprise and has two grid device, wherein at the control voltage V of P+ grid 170 (knot grid)
g2can be the voltage V at grid 140
g1function.The control circuit described with reference to Fig. 5 can be used, by mos gate pole and knot grid simultaneously all dynamic bias in " conducting " state or " cut-off " state.As described with reference to FIG. 1, control circuit can comprise and being configured to the RF signal coupling from grid 140 to the capacitor (not shown) of P+ grid 170.
In the second pattern of operation, high effective resistance R
offpermission P+ grid 170 maintains high voltage and the voltage potential be limited between grid 140 and N+ region 260 is less than mos gate pole puncture voltage.Puncture voltage due to double-gate semiconductor devices 200 is the puncture voltage sum of mos gate pole and P+ grid 170, so the intrinsic high-breakdown-voltage of P+ grid 170 provides the high-breakdown-voltage of double-gate semiconductor devices 200.
Fig. 3 illustrates and comprises mos gate pole and tie grid and be arranged at the example cross-section of double-gate semiconductor devices in the single N+ region between mos gate pole and knot grid.Double-gate semiconductor devices 300 can use semiconductor fabrication techniques known in the art to be formed by the region of doped silicon, polysilicon, metal and insulating barrier and/or layer.Double-gate semiconductor devices 300 comprises P-substrate 110, the N-trap 120 be formed in P-substrate 110, N+ source electrode 130, grid 140, oxide skin(coating) 150, N+ region 360, P+ grid 170 and N+ drain electrode 180.As shown in Figure 3, N+ region 360 is arranged in N-trap 120 substantially.
As described in referring to figs. 1 through Fig. 2, the signal of telecommunication is as V
g1with control voltage V
g2grid 140 and P+ grid 170 can be coupled to respectively.The signal of telecommunication also can use additional polysilicon layer (not shown) or metal level (not shown) to be coupled to N+ source electrode 130, N+ region 360 and N+ drain electrode 180, and these layers use semiconductor fabrication techniques known in the art to be arranged at N+ source electrode 130, N+ region 360 and N+ and drain on 180 respective surfaces.
Double-gate semiconductor devices 300 comprises the N-type mos gate pole formed by P-substrate 110, grid 140 and oxide skin(coating) 150.Double-gate semiconductor devices 300 also comprises the N raceway groove JFET formed by P-substrate 110, N-trap 120, N+ region 360, P+ grid 170 and N+ drain electrode 180.In this embodiment, N+ region 360 is the source electrode of N raceway groove JFET and adjoins N-type mos gate pole, and this N-type mos gate pole comprises grid 140 and oxide skin(coating) 150.
Can think and operate like double-gate semiconductor devices 300 and two Pattern Class as described referring to figs. 1 through Fig. 2 here.First mode is by V
g1> threshold voltage V
thwith | V
g2-V
pI| ≈ 0 shows, wherein V
pIthe voltage in N+ region 360.In a first mode, apply to be greater than V to grid 140
thvoltage V
g1make mos gate pole " conducting ".Control voltage V is applied to P+ grid 170
g2knot gate bias is made to be at control voltage V
g2with the voltage V in N+ region 360
pIbetween there is low potential difference.Therefore P+ grid 170 presents the low resistance R to current flowing
on.In a first mode, semiconductor device 300 to drain conduction current between 180 at N+ source electrode 130 and N+.In a second mode, semiconductor device 300 non-conducting electric current.
When applying control voltage V to P+ grid 170
g2make | V
g2-V
pI| time ≈ 0 (corresponding to first mode), raceway groove is open, and the electric current of majority carrier can drain between 180 in N+ region 360 and N+ and flows.Therefore can think that the behavior of P+ grid 170 (knot grid) is equivalent to following variable resistance, this resistor exists | V
g2-V
pI| > V
offin time, has to drain at N+ source electrode 130 and N+ and to allow between 180 seldom or the high effective resistance R of no current flows
offand | V
g2-V
pI| there is during ≈ 0 the low effective resistance R allowing maximum current flowing
on.
As described in referring to figs. 1 through Fig. 2, can think that double-gate semiconductor devices 300 has two grid device, wherein at the control voltage V of P+ grid 170 (knot grid)
g2can be the voltage V at grid 140
g1function.The control circuit described with reference to Fig. 5 can be used, by mos gate pole and knot grid simultaneously all dynamic bias in " conducting " state or " cut-off " state.As described with reference to FIG. 1, control circuit can comprise and being configured to the RF signal coupling from grid 140 to the capacitor (not shown) of P+ grid 170.
In the second pattern of operation, high effective resistance R
offpermission P+ grid 170 maintains high voltage and the voltage potential be limited between grid 140 and N+ region 360 is less than mos gate pole puncture voltage.Puncture voltage due to double-gate semiconductor devices 300 is the puncture voltage sum of mos gate pole and P+ grid 170, so the intrinsic high-breakdown-voltage of P+ grid 170 provides the high-breakdown-voltage of double-gate semiconductor devices 300.
Fig. 4 illustrates the example cross-section of double-gate semiconductor devices 300 in the second pattern of operation of Fig. 3.Here the description of the double-gate semiconductor devices 300 in the second pattern of operation is applicable to similarly to the second pattern of the operation of the double-gate semiconductor devices 100 and 200 described referring to figs. 1 through Fig. 2 respectively.
In the second pattern of operation, to the voltage V that grid 140 applies
g1lower than threshold voltage V
thmake mos gate pole " cut-off ".Control voltage V is applied to P+ grid 170
g2make by being used in V
g2with the voltage V in N+ region 360
pIbetween high potential difference will tie gate bias at pinch-off voltage V
offnear.Therefore P+ grid 170 presents high effective resistance R to the current flowing in drift region (ratio drift region 420 as shown in Figure 4)
off.High effective resistance R
offowing under P+ grid 170 and around the depleted region that extends, than depleted region 410 as shown in Figure 4.
High effective resistance R in the second pattern of operation
offp+ grid 170 is allowed to maintain high voltage and the voltage swing being limited in grid 140 is less than mos gate pole puncture voltage.Second pattern of operation protects grid 140 from the voltage being greater than puncture voltage effectively.Puncture voltage due to double-gate semiconductor devices 300 is the puncture voltage sum of mos gate pole and P+ grid 170, so the intrinsic high-breakdown-voltage of P+ grid 170 provides the high-breakdown-voltage of double-gate semiconductor devices 300.
Fig. 5 illustrates the exemplary circuit figure of the double-gate semiconductor devices of Fig. 1 to Fig. 2.Circuit 500 comprises N raceway groove JFET510, N-channel MOS FET520 and control circuit 530.Control circuit 530 provides control voltage V to the grid of N raceway groove JFET510
g2, this control voltage can be the voltage V of N-channel MOS FET520
g1function.Control circuit 530 works, in order to by both N-channel MOS FET520 and N raceway groove JFET510 simultaneously dynamic bias in " conducting " state or " cut-off " state.Control circuit 530 can be following capacitor, and this capacitor can by the grid of the RF signal coupling of the grid from N-channel MOS FET to N raceway groove JFET.
Control circuit 530 provides control voltage V
g2r is made with biased N raceway groove JFET510
offeffective resistance is at N-channel MOS FET " cut-off " (i.e. V
g1< V
th) time be maximum.Usually, control voltage V
g2n raceway groove JFET510 is biased in pinch-off voltage V
offnear.As N-channel MOS FET520 " conducting " (i.e. V
g1> V
th) time, control circuit 530 provides control voltage V
g2r is made with biased N raceway groove JFET510
oneffective resistance is minimum and current flowing is maximum.R
onto R
offthe allowing on a large scale in the variation greatly of the drain electrode of N raceway groove JFET510 and corresponding effective resistance change of the power capabilities to(for) the double-gate semiconductor devices described referring to figs. 1 through Fig. 2.Referring to figs. 1 through Fig. 2 describe double-gate semiconductor devices also can represent by the circuit diagram similar with circuit 500, wherein N channel junction grid 510 can by P channel junction grid (not shown) replacement and N-channel MOS grid 520 can be replaced by P channel MOS grid (not shown).
Fig. 6 illustrates the cross section of the double-gate semiconductor devices according to the present invention's alternate embodiment.Compared with the embodiment described referring to figs. 1 through Fig. 4, in this embodiment, double-gate semiconductor devices 600 can be made in more high spatial Density and distribution.As shown in Figure 6, double-gate semiconductor devices 600 does not comprise N+ region, the N+ region 160 such as described referring to figs. 1 through Fig. 4, N+ region 162, N+ region 260, N+ region 262 and N+ region 360.Therefore make double-gate semiconductor devices 600 to inject without the need to the N+ region between mos gate pole and knot grid of routine.The operating principle of double-gate semiconductor devices 600 is similar to the operating principle (comprising the description of the second pattern of the operation described with reference to Fig. 4) of the double-gate semiconductor devices 100,200 and 300 described referring to figs. 1 through Fig. 3.
Double-gate semiconductor devices 600 can use semiconductor fabrication techniques known in the art to be formed by the region of doped silicon, polysilicon, metal and insulating barrier and/or layer.Double-gate semiconductor devices 600 comprises P-substrate 110, the N-trap 120 be formed in P-substrate 110, N+ source electrode 130, grid 140, oxide skin(coating) 150, P+ grid 170 and N+ drain electrode 180.
The signal of telecommunication is as V
g1with control voltage V
g2grid 140 and P+ grid 170 can be coupled to respectively.The signal of telecommunication can use additional polysilicon layer (not shown) or metal level (not shown) to be coupled to N+ source electrode 130 and N+ drain electrode 180, and these layers use semiconductor fabrication techniques known in the art to be arranged at N+ source electrode 130 and N+ and drain on 180 respective surfaces.
Can think and operate like double-gate semiconductor devices 600 and two Pattern Class of the operation described referring to figs. 1 through Fig. 4.In a first mode, electric current drains between 180 at N+ source electrode 130 and N+ and conducts.In a second mode, electric current non-conducting.In a first mode, apply to be greater than threshold voltage V to grid 140
ththe voltage V of (not shown)
g1.Control voltage V is applied to P+ grid 170
g2, therefore present the low effective resistance R to current flowing
on.
In the second pattern of operation, to the voltage V that grid 140 applies
g1lower than threshold voltage V
th, and apply control voltage V to P+ grid 170
g2, therefore present the high effective resistance R to current flowing
off.High effective resistance R
offowing under P+ grid 170 and around the depleted region similar with the depleted region 410 described with reference to Fig. 4 that extend.
Embodiment discussed here is for illustrating the present invention.Owing to describing these embodiments with reference to schematic diagram, so those skilled in the art can know the method for description or the various amendment of concrete element or adaptation.Depend on instruction of the present invention and all such amendments making these instructions develop prior art, adaptation or change are all considered as in Spirit Essence of the present invention and scope.Therefore these descriptions and accompanying drawing should not be considered as having limited significance, because be appreciated that the present invention is never only limitted to illustrated embodiment.
Claims (11)
1. a semiconductor device, comprising:
Substrate;
Be formed in the source region in described substrate;
First grid, comprises
Dielectric layer, arrange over the substrate and formed in described substrate, above the channel region that adjoins described source region, and
Conductive gate layer, is arranged on described dielectric layer;
Well area, to be formed in described substrate and to comprise:
Drain region, is formed in described well area, and
Second grid, is formed in described well area, between described drain region and described first grid; And
Conductive path, between described channel region and described well area, it is outer and adjoin the second doped region of described channel region and arrange the conductive layer contacted with described second doped region over the substrate and with described first doped region that described conductive path comprises the first doped region in described well area, described well area.
2. semiconductor device according to claim 1, wherein said substrate comprises P doping, described source region and described drain region include N doping, described well area comprises N doping and described second grid comprises P doping.
3. semiconductor device according to claim 1, wherein said conductive layer comprises polysilicon.
4. semiconductor device according to claim 1, wherein said conductive layer comprises metal.
5. semiconductor device according to claim 1, comprises further and to be coupling between described first grid and described second grid and to be configured to the control circuit of second grid according to the biasing being applied to described first grid.
6. semiconductor device according to claim 5, wherein said control circuit comprises capacitor.
7., for providing a method for semiconductor device, comprising:
In substrate, well area is formed with the first alloy;
With the second alloy in described substrate, described well area forms source region outward; And in described substrate He in described well area, form drain region with the second alloy;
In described substrate, in described well area, first grid region is formed with the 3rd alloy;
Dielectric layer is formed over the substrate between described source region and described well area;
In described substrate, form the first doped region with described second alloy between described dielectric layer and described first grid region, described first doped region is also in described well area;
With described second alloy in described substrate, described well area is outer and form the second doped region between described dielectric layer and described first doped region;
Described dielectric layer is formed the first conductive layer; And
Form the second conductive layer over the substrate and contact described first doped region and described second doped region.
8. according to claim 7 for providing the method for semiconductor device, wherein said first alloy is identical with described second alloy.
9. according to claim 7 for providing the method for semiconductor device, comprise further: form the control circuit be coupling between described first conductive layer and described first grid region, and the bias voltage that described control circuit is configured to according to being applied to described first conductive layer comes biased described first grid region.
10. according to claim 9 for providing the method for semiconductor device, wherein form described control circuit and comprise formation capacitor.
11. is according to claim 10 for providing the method for semiconductor device, wherein forms described capacitor and comprise the multiple stacking metal level of formation.
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| CN200880128225.8A CN101978506B (en) | 2008-02-13 | 2008-02-13 | High breakdown voltage double-gate semiconductor device |
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| CN87208602U (en) * | 1987-05-25 | 1988-07-20 | 南京工学院 | Double-grid type high-voltage mos integrated circuit |
| CN1393053A (en) * | 2000-09-28 | 2003-01-22 | 皇家菲利浦电子有限公司 | Bootstrapped dual-gate class E amplifier circuit |
| TW200308075A (en) * | 2002-06-05 | 2003-12-16 | Intel Corp | Buffer, buffer operation and method of manufacture |
| CN1527400A (en) * | 2003-09-22 | 2004-09-08 | 东南大学 | Double-grid high-voltage N-type Mos transistor |
| CN1812131A (en) * | 2004-12-15 | 2006-08-02 | 因芬尼昂技术股份公司 | Double gate memory cell with improved tunnel oxide |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87208602U (en) * | 1987-05-25 | 1988-07-20 | 南京工学院 | Double-grid type high-voltage mos integrated circuit |
| CN1393053A (en) * | 2000-09-28 | 2003-01-22 | 皇家菲利浦电子有限公司 | Bootstrapped dual-gate class E amplifier circuit |
| TW200308075A (en) * | 2002-06-05 | 2003-12-16 | Intel Corp | Buffer, buffer operation and method of manufacture |
| CN1527400A (en) * | 2003-09-22 | 2004-09-08 | 东南大学 | Double-grid high-voltage N-type Mos transistor |
| CN1812131A (en) * | 2004-12-15 | 2006-08-02 | 因芬尼昂技术股份公司 | Double gate memory cell with improved tunnel oxide |
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