CN102981963B - A kind of implementation method of flash translation layer (FTL) of solid-state disk - Google Patents
A kind of implementation method of flash translation layer (FTL) of solid-state disk Download PDFInfo
- Publication number
- CN102981963B CN102981963B CN201210427484.9A CN201210427484A CN102981963B CN 102981963 B CN102981963 B CN 102981963B CN 201210427484 A CN201210427484 A CN 201210427484A CN 102981963 B CN102981963 B CN 102981963B
- Authority
- CN
- China
- Prior art keywords
- page number
- page
- mapping table
- logical
- buffer memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a kind of implementation method of flash translation layer (FTL) of solid-state disk, comprise: receive the read-write requests that file system sends, it is the page of K that this read-write requests corresponds to logical address, whether decision logic address K hits in buffer memory mapping table, if not, then judge in buffer memory mapping table, whether to admit the mapping relations number n once calling in buffer memory mapping table again, if can not admit, then find out the logical page number (LPN) Victim_Num finding out least-recently-used mapping relations in buffer memory mapping table, the all logical page number (LPN)s be stored in the mapping table with the mapping relations of Victim_Num in same one page are found out in buffer memory mapping table, and from mapping relations corresponding to these logical page number (LPN)s, find out n least-recently-used mapping relations, in global transformation catalogue, corresponding mapping relations are searched out according to Victim_Num.Read-write efficiency of the present invention is higher, and improves the performance of system, extends the life-span of solid-state disk.
Description
Technical field
The invention belongs to solid-state disk technical field of memory, more specifically, relate to a kind of implementation method of flash translation layer (FTL) of solid-state disk.
Background technology
In recent years, flash memory (Flash) the technology change that leads field of storage new., the many advantage such as speed fast, low in energy consumption, noiseless anti-vibration little by feat of its volume is replacing traditional mechanical hard disk gradually.
Completely different with conventional hard, as shown in Figure 1, flash chip of the prior art (FlashChip) 101 is made up of multiple pieces of (Block) 102, a block 102 is made up of multiple page (Page) 103, be generally 64, and in a page 103, be divided into two regions, be respectively data field 104 (DataArea) and OOB district (Out-ofBandarea) 105 composition.In a general page 103, data field is 512B, OOB is then 16B.Wherein the major function of OOB be record Hamming checking code, the logic page number and current page state, namely free time/invalidating (Free/Valid/Invalid).
Just based on this design feature of flash memory self, it also has its disadvantageous one side, is mainly manifested in four aspects: 1, will in units of page when read-write, can not in units of data; 2, write before to wipe in units of Block, namely can not cover and write (Over-write), when data need amendment, can not direct original place amendment as disk, and need will this data block wipe after re-write data again; 3, the erasing times of Block is limited, i.e. the restricted lifetime of flash memory.Therefore flash memory directly can not be used by traditional file systems as mechanical disk memory.
In order to make full use of technology and the product of the accumulation of traditional magnetic disk field, one or more flash chip combination is all packaged into the solid-state disk (SolidStateDrive of a look-alike disk by all big enterprises, be called for short SSD), for upper layer application provides the interface the same with traditional magnetic disk, and do not need amendment file system and application.Therefore, need a flash translation layer (FTL) (Flashtranslationlayer, be called for short FTL) solid-state disk is modeled to the block device of standard to shield its characteristic, make topmost paper system using in it just as at the common magnetic disk memory of use one.
As shown in Figure 2, the solid-state disk system of prior art comprises file system (in units of sector), FTL, flash drive and flash chip from top to bottom, wherein FTL comprises again three bulks, address maps converts the physical address of solid-state disk to by the logical address of topmost paper system in units of sector, this is topmost part in FTL, and garbage reclamation and abrasion equilibrium realize each flash memory and reclaim the flash block lost efficacy when abrasion equilibrium.
In existing FTL, although can shield to upper system the characteristic needing before it is write to wipe, still there is obvious weak point: 1, the buffer scheduling algorithm of the inside is not well in conjunction with the read write attribute of solid-state disk; Such as, now relatively more conventional page level maps FTL and is calling in lru algorithm conventional in the traditional file systems used in mapping relations to buffer memory, namely only call in mapping relations at every turn, but solid-state disk take page as read-write unit, call in mapping relations to need to read whole mapped page, recalling renewal mapping relations needs to write whole mapped page.Illustrate that this cache management mechanism is not suitable for solid-state disk; The spatial locality of data that what buffer scheduling 2, in existing FTL utilized is, and still immature to the utilization of sequential locality.May have multilayer buffer memory in actual storage system, and the buffer memory of solid-state disk is in the bottom.The I/O request of system arrives the buffer memory of solid-state disk after the filtration of upper strata buffer memory at different levels, does not almost have spatial locality.To be used in hit rate on solid-state disk unsatisfactory for the algorithm that recalls of therefore existing FTL.And solid-state disk buffer memory does not hit expense very large (map if need to upgrade, do not hit expense and comprise twice read operation and a write operation), the life-span of serious curtailments hard disk.
Summary of the invention
For the defect of prior art, the object of the present invention is to provide a kind of implementation method of flash translation layer (FTL) of solid-state disk, its read-write efficiency is higher, be more suitable for solid-state disk, and the update times effectively improving cache hit rate and minimizing flash memory with batch updating is dispatched forward by multilist, and then improve the performance of system, extend the life-span of solid-state disk.
For achieving the above object, the invention provides a kind of implementation method of flash translation layer (FTL) of solid-state disk, comprise the following steps:
(1) receive the read-write requests that file system sends, it is the page of K that this read-write requests corresponds to logical address, and wherein K is positive integer;
(2) whether decision logic address K hits in buffer memory mapping table, if yes then enter step (13), otherwise enters step (3);
(3) judge whether can admit the mapping relations number n once calling in buffer memory mapping table in buffer memory mapping table again, if can admit, then go to step (11), otherwise go to step (4);
(4) in buffer memory mapping table, find out the logical page number (LPN) Victim_Num of least-recently-used mapping relations;
(5) in buffer memory mapping table, find out all logical page number (LPN)s be stored in the mapping table with the mapping relations of Victim_Num in same one page, and find out n least-recently-used mapping relations from mapping relations corresponding to these logical page number (LPN)s;
(6) in global transformation catalogue, corresponding mapping relations are searched out according to Victim_Num, specifically, be E after dividing exactly 512 with Victim_Num, remainder is F, illustrate that logical page number (LPN) is the position that the mapping relations of Victim_Num are stored in that logical mappings page number is E, skew is F, be stored in the page that logical mappings page number is E the position that physical mappings page number is B by global transformation directory search;
(7) find physical mappings page number to be the page of B in the mapping table, and compare with the mapping relations in buffer memory mapping table, but judge whether that the physical page number of the identical correspondence of logical page number (LPN) is different, if had, then go to step (8); Otherwise go to step (10);
(8) an available page is found in the mapping table, its physical mappings page number is C, the physical mappings page number B mapping relations appeared in buffer memory mapping table are updated in this available page C, and the mapping relations do not appeared in buffer memory mapping table in physical mappings page number B are copied in this available page C, be the page setup of B by physical mappings page number be invalid, etc. to be recycled, and be that the page of C is set to effectively by available by physical mappings page number;
(9) in global transformation catalogue, physical mappings page number B corresponding for logical mappings page number E is changed to C;
(10) in buffer memory mapping table, remove n least-recently-used page-map relation;
(11) determine that logical address K is G after dividing exactly 512, remainder is H, and the physical mappings page number M finding logical mappings page number G corresponding in global transformation catalogue;
(12) find physical mappings page number to be the page of M in the mapping table, then find the mapping relations of its skew H, itself and the continuous n-1 bar mapping relations in same one page are below recalled, joins in buffer memory mapping table;
(13) in buffer memory mapping table, find logical page number (LPN) to be the record of K, obtain its physical page number J;
(14) find physical page number to be the page of J within the data block, and the address of this page is returned to file system.
The value of once calling in the mapping relations number n of buffer memory mapping table is 4-16.
By the above technical scheme that the present invention conceives, compared with prior art, the present invention has following beneficial effect:
1, improve cache hit rate: because in step (13), carried out multilist and dispatched forward, multiple continuous print mapping relations are called in a read operation, from dividing the sequential locality that make use of bottom buffer memory.
2, the read-write number of times of flash memory is reduced: because have employed the technology of batch updating in step (5) and (10), under the prerequisite not increasing read-write number of times, carry out batch updating.
3, the life-span of flash memory is extended: because have employed step (5) and (10), the read-write number of times of Flash is reduced, thus extends its serviceable life.
4, make use of sequential locality: because have employed step (13), the mapping relations of calling in CMT are the n bar record of continuous print in same one page.While calling in the mapping of current needs, probably to use after calling in mapping, not only make use of spatial locality (in the buffer memory of upper strata), also effectively make use of sequential locality, even if also greatly cache hit rate can be improved further after the filtration of upper strata I/O.
Accompanying drawing explanation
Fig. 1 is the structural representation of the flash chip of prior art.
Fig. 2 is the structural representation of the solid-state disk system of prior art.
Fig. 3 is the design structure diagram of the implementation method of the flash translation layer (FTL) of solid-state disk of the present invention.
Fig. 4 reads and writes schematic flow sheet in the inventive method.
Fig. 5 is the process flow diagram of the implementation method of the flash translation layer (FTL) of solid-state disk of the present invention.
Fig. 6 is the contrast that the flash memory conversion method of prior art and the inventive method read and write number of times.
Fig. 7 is the flash memory conversion method of prior art and the contrast of the inventive method erasing times.
Fig. 8 is the flash memory conversion method of prior art and the contrast of the inventive method cache hit rate.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Below first technical term of the present invention is explained and illustrated.
Buffer memory mapping table: CacheMappingTable, is after this called for short CMT, is used for mapping table in storage activities;
Mapping table: TranslationBlocks, stores the mapping relations of all logical page number (LPN)s to physical page number;
Data block: DataBlocks, is used for storing the True Data of user;
Global transformation catalogue: GlobalTranslationDirectory, the mapping relations being used for following the trail of logical address number deposit which page in the mapping table;
D
lPN: LogicalDataPageNumber, logical page number (LPN);
D
pPN: PhysicalDataPageNumber, physical page number;
M
vPN: VirtualTranslationPageNumber, logical mappings page number;
M
pPN:: PhysicalTranslationPageNumber, physical mappings page number;
Below in conjunction with the accompanying drawing in the invention process example, carry out clear, complete description to the technical scheme in example of the present invention, obviously, described embodiment is a part of example of the present invention, instead of whole embodiments.Based on embodiments of the invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 3, the flash chip that the implementation method of the flash translation layer (FTL) of solid-state disk of the present invention is applied to always is divided into four bulks, the mapping table that buffer memory mapping table (CachedMappingTable is called for short CMT) is used in storage activities; Global transformation catalogue (GlobalTranslationDirectory, be called for short GTD), the mapping relations being used for following the trail of logical address number exist in which page of mapping table; CMT and GTD deposits in sram; Data block (DataBlock) and mapping table (TranslationBlock), it is all arranged in flash memory, wherein data block accounts for the overwhelming majority, what data block stored is user data truly, and mapping table then stores the mapping relations of all logical addresses in data block to physical address.
The present invention fully takes into account the read write attribute of solid-state disk, while buffer memory mapping table completely needs to recall a part of mapping relations, by with other mapping relations update all be recorded in this in the mapping table in same page (be called for short batch updating technology), like this when not increasing read-write number of times, what decrease mapping table writes number of times, and then extends the solid-state disk life-span.
In addition, the combination with upper strata buffer memory has been taken into full account calling on strategy in the present invention.Owing to taking full advantage of spatial locality in the buffer memory of upper strata, consider the filtration of upper strata buffer memory, can greatly decline by LRU hit rate in solid-state disk, therefore the present invention utilizes sequential locality calling in strategy, namely once call in multiple continuous print mapping relations (to be called for short multilist to dispatch forward) in buffer memory mapping table, experiment draws, substantially increases cache hit rate like this.
In addition, when buffer memory mapping table completely needs to call in multiple mapping relations, must need to recall multiple mapping relations in the buffer.In CMT, now first find out the logical page number (LPN) Victim_Num of least-recently-used mapping relations, then find out in mapping table with all mapping relations that appear in CMT of Victim_Num at same one page, more therefrom find out n-1 (wherein n is the mapping relations number of once calling in CMT) individual least-recently-used mapping relations and recall.
As shown in Figures 4 and 5, the implementation method of the flash translation layer (FTL) of solid-state disk of the present invention comprises the following steps:
(1) receive the read-write requests that file system sends, this read-write requests corresponds to the page that logical address is K (K is positive integer), as shown in (1) in Fig. 4, in the shown example, and K=1280;
(2) whether decision logic address K hits in CMT, if yes then enter step (13), otherwise enters step (3);
(3) judge whether can admit n again in CMT, wherein n is the mapping relations number of once calling in CMT, if can admit, then goes to step (11), otherwise goes to step (4); The value of usual n is 4-16, in the shown example, and n=4;
(4) in CMT, find out the logical page number (LPN) Victim_Num of least-recently-used mapping relations, as shown in (4) in Fig. 4, in the shown example, get VictimNum=1;
(5) find out in CMT and to be stored in all logical page number (LPN)s in same one page in the mapping table with the mapping relations of Victim_Num (because logical page number (LPN) is order in the mapping table, such as logic number 0-511 is at same one page, 512-1024 is at same one page), and from mapping relations corresponding to these logical page number (LPN)s, find out n least-recently-used mapping relations, as shown in (5) in Fig. 4, n logical page number (LPN) is respectively 1,2,4,7;
(6) in GTD, corresponding mapping relations are searched out (in GTD according to Victim_Num, the relation record mapped is that order is deposited), specifically, be E after in figure, Victim_Num divides exactly 512, remainder is F, illustrate that logical page number (LPN) is the position that the mapping relations of Victim_Num are stored in that logical mappings page number is E, skew is F, finding logical mappings page number by GTD is that the page of E is stored in the position that physical mappings page number is B; For example, as shown in (7) in Fig. 4, B=21, be 0 after Victim_Num divides exactly 512, remainder is 1, illustrate that logical page number (LPN) is the position that the mapping relations of Victim_Num are stored in that logical mappings page number is 0, skew is 1, by GTD find logical mappings page number be 0 the page be stored in the position that physical mappings page number is 21;
(7) find physical mappings page number to be the page of B in the mapping table, and compare with the mapping relations in CMT, but judge whether that the physical page number of the identical correspondence of logical page number (LPN) is different, if had, then go to step (8); Otherwise go to step (10);
(8) an available page is found in the mapping table, its physical mappings page number is C, the physical mappings page number B mapping relations appeared in CMT are updated in this available page C, and the mapping relations do not appeared in CMT in physical mappings page number B are copied in this available page C, be the page setup of B by physical mappings page number be invalid, etc. to be recycled, and be that the page of C is set to effectively by available by physical mappings page number, as shown in (8) in Fig. 4, in the shown example, C=23 is got;
(9) in GTD, physical mappings page number B corresponding for logical mappings page number E is changed to C, for example, as shown in (9) in Fig. 4, in GTD, the physical mappings page number 21 of logical mappings page number 0 correspondence is changed to 23;
(10) in CMT, remove n least-recently-used page-map relation, in the shown example, to be logical page number (LPN) be 1,2,4,10 four records;
(11) determine that logical address K is G after dividing exactly 512, remainder is H, and the physical mappings page number M finding logical mappings page number G corresponding in GTD, as shown in (11) in Fig. 4, G=2, remainder H=256, M=15 after logical address 1280 divides exactly 512;
(12) find physical mappings page number to be the page of M in the mapping table, then find the mapping relations of its skew H, itself and the continuous n-1 bar mapping relations in same one page are below recalled, joins in CMT, as shown in (12) in Fig. 4;
(13) in CMT, find logical page number (LPN) to be the record of K, obtain its physical page number J, as shown in (13) in Fig. 4, J=660;
(14) find physical page number to be the page of J within the data block, and the address of this page is returned to file system.
Fig. 6 and Fig. 7 is existing flash memory conversion method and the readwrite performance of the inventive method and the contrast of erasing times respectively, as can be seen from the figure, method of the present invention effectively can reduce read-write number of times and erasing times, wherein, read number of times less 54.21%, write number of times less 15.74%, erasing times has been less 15.75%.
Fig. 8 is the contrast of the cache hit rate of existing flash memory conversion method and the inventive method, and as can be seen from the figure cache hit rate improves 20.1%.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. an implementation method for the flash translation layer (FTL) of solid-state disk, is characterized in that, comprises the following steps:
(1) receive the read-write requests that file system sends, it is the page of K that this read-write requests corresponds to logical address, and wherein K is positive integer;
(2) whether decision logic address K hits in buffer memory mapping table, if yes then enter step (13), otherwise enters step (3);
(3) judge whether can admit the mapping relations number n once calling in buffer memory mapping table in buffer memory mapping table again, if can admit, then go to step (11), otherwise go to step (4);
(4) in buffer memory mapping table, find out the logical page number (LPN) Victim_Num of least-recently-used mapping relations;
(5) in buffer memory mapping table, find out all logical page number (LPN)s be stored in the mapping table with the mapping relations of logical page number (LPN) Victim_Num in same one page, and find out n least-recently-used mapping relations from mapping relations corresponding to these logical page number (LPN)s;
(6) in global transformation catalogue, corresponding mapping relations are searched out according to logical page number (LPN) Victim_Num, specifically, be E after dividing exactly 512 with logical page number (LPN) Victim_Num, remainder is F, illustrate that logical page number (LPN) is the position that the mapping relations of logical page number (LPN) Victim_Num are stored in that logical mappings page number is E, skew is F, be stored in the page that logical mappings page number is E the position that physical mappings page number is B by global transformation directory search;
(7) find physical mappings page number to be the page of B in the mapping table, and compare with the mapping relations in buffer memory mapping table, but judge whether that the physical page number of the identical correspondence of logical page number (LPN) is different, if had, then go to step (8); Otherwise go to step (10);
(8) an available page is found in the mapping table, its physical mappings page number is C, the physical mappings page number B mapping relations appeared in buffer memory mapping table are updated in this available page C, and the mapping relations do not appeared in buffer memory mapping table in physical mappings page number B are copied in this available page C, be the page setup of B by physical mappings page number be invalid, etc. to be recycled, and be that the page of C is set to effectively by available by physical mappings page number;
(9) in global transformation catalogue, physical mappings page number B corresponding for logical mappings page number E is changed to C;
(10) in buffer memory mapping table, remove n least-recently-used page-map relation;
(11) determine that logical address K is G after dividing exactly 512, remainder is H, and the physical mappings page number M finding logical mappings page number G corresponding in global transformation catalogue;
(12) find physical mappings page number to be the page of M in the mapping table, then find the mapping relations of its skew H, itself and the continuous n-1 bar mapping relations in same one page are below recalled, joins in buffer memory mapping table;
(13) in buffer memory mapping table, find logical page number (LPN) to be the record of K, obtain its physical page number J;
(14) find physical page number to be the page of J within the data block, and the address of this page is returned to file system.
2. implementation method according to claim 1, is characterized in that, the value of once calling in the mapping relations number n of buffer memory mapping table is 4-16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210427484.9A CN102981963B (en) | 2012-10-30 | 2012-10-30 | A kind of implementation method of flash translation layer (FTL) of solid-state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210427484.9A CN102981963B (en) | 2012-10-30 | 2012-10-30 | A kind of implementation method of flash translation layer (FTL) of solid-state disk |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102981963A CN102981963A (en) | 2013-03-20 |
| CN102981963B true CN102981963B (en) | 2015-12-02 |
Family
ID=47856015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210427484.9A Active CN102981963B (en) | 2012-10-30 | 2012-10-30 | A kind of implementation method of flash translation layer (FTL) of solid-state disk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102981963B (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103136121B (en) * | 2013-03-25 | 2014-04-16 | 中国人民解放军国防科学技术大学 | Cache management method for solid-state disc |
| US20140304453A1 (en) * | 2013-04-08 | 2014-10-09 | The Hong Kong Polytechnic University | Effective Caching for Demand-based Flash Translation Layers in Large-Scale Flash Memory Storage Systems |
| CN103425600B (en) * | 2013-08-23 | 2016-01-20 | 中国人民解放军国防科学技术大学 | Address mapping method in a kind of solid-state disk flash translation layer (FTL) |
| CN104166634A (en) * | 2014-08-12 | 2014-11-26 | 华中科技大学 | Management method of mapping table caches in solid-state disk system |
| CN104268094B (en) * | 2014-09-23 | 2017-05-03 | 浪潮电子信息产业股份有限公司 | Optimized flash memory address mapping method |
| CN106155579A (en) * | 2015-04-27 | 2016-11-23 | 广明光电股份有限公司 | The method of solid state hard disc dynamic storing conversion layer data |
| CN106326134B (en) * | 2015-06-30 | 2019-10-01 | 华为技术有限公司 | The method and device of FTL address of cache |
| KR102580820B1 (en) * | 2016-03-10 | 2023-09-20 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
| US20170344575A1 (en) * | 2016-05-27 | 2017-11-30 | Netapp, Inc. | Methods for facilitating external cache in a cloud storage environment and devices thereof |
| US10289544B2 (en) * | 2016-07-19 | 2019-05-14 | Western Digital Technologies, Inc. | Mapping tables for storage devices |
| CN106502928B (en) * | 2016-09-29 | 2019-08-20 | 华为技术有限公司 | A kind of storage system power-off protection method, storage control and electronic equipment |
| CN106815152B (en) * | 2016-12-27 | 2019-05-31 | 华中科技大学 | A method of optimization page grade flash translation layer (FTL) |
| CN107368436B (en) * | 2017-06-29 | 2020-08-18 | 西安交通大学 | Flash memory cold and hot data separated storage method combined with address mapping table |
| CN109725825B (en) * | 2017-10-27 | 2022-03-11 | 伊姆西Ip控股有限责任公司 | Method, apparatus and computer program product for managing a cache |
| CN110007876A (en) * | 2019-04-15 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of solid state hard disk date storage method, device, equipment and medium |
| CN110059021A (en) * | 2019-04-18 | 2019-07-26 | 深圳市时创意电子有限公司 | A kind of algorithm for reducing write-in magnifying power and promoting random writing performance |
| CN110262982A (en) * | 2019-05-05 | 2019-09-20 | 杭州电子科技大学 | A kind of method of solid state hard disk address of cache |
| CN112882663B (en) * | 2021-03-25 | 2022-10-14 | 湖南国科微电子股份有限公司 | Random writing method, electronic equipment and storage medium |
| CN113220241A (en) * | 2021-05-27 | 2021-08-06 | 衢州学院 | Cross-layer design-based hybrid SSD performance and service life optimization method |
| CN116010298B (en) * | 2023-03-24 | 2023-09-22 | 温州市特种设备检测科学研究院(温州市特种设备应急处置中心) | NAND type flash memory address mapping method and device, electronic equipment and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102043721A (en) * | 2010-05-12 | 2011-05-04 | 中颖电子股份有限公司 | Memory management method for flash memory |
| CN102521156A (en) * | 2011-12-12 | 2012-06-27 | 云海创想信息技术（天津）有限公司 | Mapping relation access method and mapping relation access device |
-
2012
- 2012-10-30 CN CN201210427484.9A patent/CN102981963B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102043721A (en) * | 2010-05-12 | 2011-05-04 | 中颖电子股份有限公司 | Memory management method for flash memory |
| CN102521156A (en) * | 2011-12-12 | 2012-06-27 | 云海创想信息技术（天津）有限公司 | Mapping relation access method and mapping relation access device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102981963A (en) | 2013-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102981963B (en) | A kind of implementation method of flash translation layer (FTL) of solid-state disk | |
| CN104268094B (en) | Optimized flash memory address mapping method | |
| CN103425600B (en) | Address mapping method in a kind of solid-state disk flash translation layer (FTL) | |
| US10915475B2 (en) | Methods and apparatus for variable size logical page management based on hot and cold data | |
| CN106547703B (en) | A kind of FTL optimization method based on block group structure | |
| CN101169751B (en) | System with flash memory device and data recovery method thereof | |
| CN103136121B (en) | Cache management method for solid-state disc | |
| CN104166634A (en) | Management method of mapping table caches in solid-state disk system | |
| CN107391391B (en) | Method, system and the solid state hard disk of data copy are realized in the FTL of solid state hard disk | |
| CN102163175B (en) | Hybrid address mapping method based on locality analysis | |
| US10740251B2 (en) | Hybrid drive translation layer | |
| CN109582593B (en) | FTL address mapping reading and writing method based on calculation | |
| CN104102591A (en) | Computer subsystem and method for implementing flash translation layer in computer subsystem | |
| CN110413537B (en) | Flash translation layer facing hybrid solid state disk and conversion method | |
| CN102789427A (en) | Data storage device and operation method thereof | |
| CN101477492A (en) | Circulating rewriting flash memory equalization method used for solid state disk | |
| CN106815152A (en) | A kind of method for optimizing page level flash translation layer (FTL) | |
| CN109783398A (en) | One kind is based on related perception page-level FTL solid state hard disk performance optimization method | |
| KR20100115090A (en) | Buffer-aware garbage collection technique for nand flash memory-based storage systems | |
| CN106598493A (en) | Solid state disk address mapping table management method | |
| CN108845957A (en) | It is a kind of to replace and the adaptive buffer management method of write-back | |
| CN113253926A (en) | Memory internal index construction method for improving query and memory performance of novel memory | |
| CN115203079A (en) | Method for writing data into solid state disk | |
| CN102521144B (en) | Flash translation layer system | |
| Park et al. | A dynamic switching flash translation layer based on page-level mapping |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |