CN102957315A - Boost integrated circuit for tuner - Google Patents
Boost integrated circuit for tuner Download PDFInfo
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- CN102957315A CN102957315A CN2011102390997A CN201110239099A CN102957315A CN 102957315 A CN102957315 A CN 102957315A CN 2011102390997 A CN2011102390997 A CN 2011102390997A CN 201110239099 A CN201110239099 A CN 201110239099A CN 102957315 A CN102957315 A CN 102957315A
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Abstract
The invention relates to the field of electrical design and discloses a boost integrated circuit for a tuner. The boost integrated circuit comprises a clock oscillation circuit, a charge pump circuit and a voltage stabilizing circuit, wherein the clock oscillation circuit is electrically connected with the charge pump circuit and used for providing clock frequency signals for the charge pump circuit. An input end of a low-noise circuit is externally connected with externally input low-voltage signals, and an output end of the low-noise circuit. The charge pump circuit comprises N levels of charge pump subcircuits and output load circuits in cascade connection, wherein the N is a natural number. By the above technical scheme, low-voltage electric signals can be boosted to required high-voltage electric signals, and the boost integrated circuit for the tuner is high in adaptability and adjustability according to practical application.
Description
Technical field
The present invention relates to electrical design field, relate in particular to a kind of integrated circuit that boosts.
Background technology
The English Tuner that claims of tuner is a kind of device of finishing reception, gating, frequency conversion, demodulating process with analog form, is commonly called as to be tuner in television set, and tuner is widely used in television set, FM/AM broadcast receiver.Such as M/AM tuner or TV tuner, FM and AM are the signal modulation systems, and FM refers to frequency modulation, and AM refers to amplitude modulation.
Present one+33V of tuner need of work voltage, its method of realization that provides of this tuning operating voltage has following two kinds at present:
The one,, provide this tuning operating voltage signal of telecommunication by mainboard, and the mainboard of most all adopt low pressure (such as+5V) power supply, thus booster circuit that must setting general-purpose when realizing, by this booster circuit with the low tension signal (such as+5V) boost into the high pressure telecommunication signal (+33V).Therefore adopt the circuit of this solution to realize that cost is high, and because this implementation need to take motherboard resources, this implementation is eliminated at present substantially.
The 2nd,, in tuner, carry+the 33V power supply, and this also must be at the inner additional booster circuit of tuner.Mainly be to form an oscillation step-up circuit with more than ten device such as triode and inductance at present, this circuit structure is complicated, failure rate is high, and because the vibration that this booster circuit produces is to being caused interference by tuning signal, therefore should realize that settling mode was high to the precision of device, anti-interference parameter request, device cost is high.
Summary of the invention
The embodiment of the invention the first purpose is to provide a kind of integrated circuit that boosts, and it can be realized the low tension signal boosted and be required high-voltage signal, and it is strong to adapt to the property adjusted according to practical application.
A kind of integrated circuit that boosts that the embodiment of the invention provides comprises: clock oscillation circuit, charge pump circuit, voltage stabilizing circuit, wherein,
Described clock oscillation circuit is electrically connected with described charge pump circuit, is used to described charge pump circuit that clock frequency signal is provided,
The external outside input low-voltage signal of the input of described low noise circuit, output is electrically connected with described voltage stabilizing circuit; Wherein,
Described charge pump circuit comprises that by the charge pump electronic circuit of N level concatenated in order, output loading the electric circuit constitute, wherein N is natural number;
Each charge pump electronic circuit comprises respectively:
The first voltage stabilizing didoe (D1) that is electrically connected in series mutually, electrical quantity is identical, the second voltage stabilizing didoe (D2), the 3rd voltage stabilizing didoe (D3), the 4th voltage stabilizing didoe (D4),
The first parasitic capacitance (CS1), the second parasitic capacitance (CS2), trixenie electric capacity (CS3) between the negative pole end that is connected electrically in respectively described the second voltage stabilizing didoe (D2), the 3rd voltage stabilizing didoe (D3), the 4th voltage stabilizing didoe (D4) and the earth terminal, that electrical quantity is identical
Be connected electrically in the 3rd load capacitance (C3) of negative pole end and the described clock frequency signal first input end of described voltage stabilizing didoe D4,
Be connected electrically in second load capacitance (C2) of negative pole end and described clock frequency signal the second input of described voltage stabilizing didoe D3,
Be connected electrically in first load capacitance (C1) of negative pole end and the described clock frequency signal first input end of described voltage stabilizing didoe D2,
The electrical quantity of wherein said the first load capacitance (C1), the second load capacitance (C2), the 3rd load capacitance (C3) is identical;
Wherein the positive terminal of the 4th voltage stabilizing didoe (D4) in the 1st grade of charge pump electronic circuit can the external described outer low pressure signal of telecommunication, and the negative pole of first voltage stabilizing didoe (D1) of described N level charge pump electronic circuit is by the outside required high-voltage signal of output of described pressurizer.
Alternatively, described pressurizer is: mutual other earth capacitance (Cout) in parallel and the RC filter circuit of other earth resistance (R) composition,
First voltage stabilizing didoe (D1) of described N level charge pump electronic circuit is outwards exported required high-voltage signal by described pressurizer: specifically,
The negative electricity of first voltage stabilizing didoe (D1) of one end N level charge pump electronic circuit of described RC filter circuit connects, other end ground connection.
Alternatively, described the first voltage stabilizing didoe (D1), the second voltage stabilizing didoe (D2), the 3rd voltage stabilizing didoe (D3), the 4th voltage stabilizing didoe (D4) are metal-oxide-semiconductor diode.
Alternatively, the described integrated circuit that boosts is the complementary metal oxide semiconductors (CMOS) packaged chip.
Alternatively, the described integrated circuit complementary metal-oxide semiconductor (MOS) packaging technology granularity of boosting is 0.18 μ m.
Alternatively, the described integrated circuit that boosts is the SOT-23 encapsulation.
Alternatively, also comprise:
Input filter circuit, the positive terminal that is connected to the 4th voltage stabilizing didoe (D4) in the 1st grade of charge pump electronic circuit of described charge pump circuit is electrically connected with high-frequency filter capacitor (Co1), low frequency filtering electric capacity (Co2) also otherly.
Alternatively, also comprise following peripheral circuit:
The capacitance of described high-frequency filter capacitor (Co1) is 100PF,
The capacitance of described low frequency filtering electric capacity (Co2) is 4.7 μ F.
Alternatively, also comprise following peripheral circuit:
Output filter capacitor (Co3) is connected electrically between the negative electricity and ground of the first voltage stabilizing didoe (D1) of described N level charge pump electronic circuit;
Output load resistance (R1) is electrically connected in series in the negative pole end of first voltage stabilizing didoe (D1) of described N level charge pump electronic circuit, externally exports supply power voltage.
Therefore, use the technical scheme of the embodiment of the invention, the circuit structure that adopts in the integrated circuit that boosts that the present embodiment provides can be adjusted the capacitance C of the first parasitic capacitance CS1, CS2, CS3 and the progression of charge pump reaches actual needs according to the situation of reality (input low voltage voltage parameter, the output voltage parameters that need), therefore the adjustment flexibility according to actual needs of this circuit structure is stronger.
In addition, the integrated circuit that boosts of the present embodiment adopts CMOS encapsulation IC chip form, its small Stability Analysis of Structures, and anti-interference is better.
Description of drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, consists of the application's a part, does not consist of to improper restriction of the present invention, in the accompanying drawings:
The theory structure schematic block diagram of a kind of integrated circuit that boosts that Fig. 1 provides for the embodiment of the invention 1;
Fig. 2 is the realization circuit diagram of the charge pump circuit among Fig. 1 in the embodiment of the invention 1;
The electrical block diagram of a kind of integrated circuit that boosts with peripheral circuit of providing in the embodiment of the invention 1 is provided Fig. 3.
Embodiment
Describe the present invention in detail below in conjunction with accompanying drawing and specific embodiment, be used for explaining the present invention in this illustrative examples of the present invention and explanation, but not as a limitation of the invention.
Embodiment 1:
Shown in Fig. 1-3, a kind of integrated circuit 100 that boosts that the present embodiment provides mainly comprises following three parts: clock oscillation circuit 101, charge pump circuit 102, voltage stabilizing circuit 103.
Wherein this clock oscillation circuit 101 is electrically connected with charge pump circuit 102, clock oscillation circuit 101 is used to charge pump circuit 102 that clock frequency signal is provided, the external outside input low-voltage signal of the input of low noise circuit, output is electrically connected with voltage stabilizing circuit 103.
Wherein, charge pump circuit 102 comprises that by the charge pump electronic circuit of N level concatenated in order, output loading the electric circuit constitute, wherein N is natural number, such as 1,2,3 ... N.
Charge pump electronic circuits at different levels are comprised of the first voltage stabilizing didoe D1, the second voltage stabilizing didoe D2, the 3rd voltage stabilizing didoe D3, the 4th voltage stabilizing didoe D4, the first parasitic capacitance CS1, the second parasitic capacitance CS2, trixenie capacitor C S3, the first load capacitance C1, the second load capacitance C2, the 3rd load capacitance C3 respectively.
Wherein, the first voltage stabilizing didoe D1, the second voltage stabilizing didoe D2, the 3rd voltage stabilizing didoe D3, the 4th voltage stabilizing didoe D4 electrical quantity are identical, and the first parasitic capacitance CS1, the second parasitic capacitance CS2, trixenie capacitor C S3 electrical quantity are identical.
In charge pump electronic circuit at different levels, wherein circuit connecting relation is as follows:
The first voltage stabilizing didoe D1, the second voltage stabilizing didoe D2, the 3rd voltage stabilizing didoe D3, the 4th voltage stabilizing didoe D4 are electrically connected in series mutually.
The first parasitic capacitance CS1 is connected electrically between the negative electrode and earth terminal of the second voltage stabilizing didoe D2; Trixenie capacitor C S3 is connected electrically between the negative electrode and earth terminal of the 3rd voltage stabilizing didoe D3; The second parasitic capacitance CS2 is connected electrically between the negative electrode and earth terminal of the 4th voltage stabilizing didoe D4.
The 3rd load capacitance C3 point is connected between the negative electrode and described clock frequency signal first input end of voltage stabilizing didoe D4;
The second load capacitance C2 point is connected between the negative electrode and described clock frequency signal the second input of voltage stabilizing didoe D3;
The first load capacitance C1 point is connected between the negative electrode and described clock frequency signal first input end of voltage stabilizing didoe D2.
Whole charge pump circuit 102 is as follows with the annexation of outside input, output with voltage stabilizing circuit 103: wherein the positive terminal of the 4th voltage stabilizing didoe D4 in the 1st grade of charge pump electronic circuit can the external outer low pressure signal of telecommunication, and the negative pole of the first voltage stabilizing didoe D1 of described N level charge pump electronic circuit is by the outside required high-voltage signal of output of described pressurizer.
This pressurizer is: mutual other earth capacitance Cout in parallel and the RC filter circuit of other earth resistance Rc composition, the first voltage stabilizing didoe D1 of N level charge pump electronic circuit outwards exports required high-voltage signal by pressurizer: specifically, the negative electricity of the first voltage stabilizing didoe D1 of one end N level charge pump electronic circuit of RC filter circuit connects, other end ground connection.
Referring to shown in Figure 2, if the clock frequency that clock oscillation circuit 101 provides be fosc its can but be not limited to 2MHZ), Cs is that the capacitance of the first parasitic capacitance CS1, the second parasitic capacitance CS2, trixenie capacitor C S3 is Cs, the pressure drop of the first voltage stabilizing didoe D1, the second voltage stabilizing didoe D2, the 3rd voltage stabilizing didoe D3, the 4th voltage stabilizing didoe D4 be Vd(can but be not limited to 0.3V), load current be Iout(can but be not limited to 50 μ A), the capacitance of load capacitance C1, C2, C3 is C.
According to the circuit of Fig. 2 as seen, output voltage V out can determine according to following formula:
Vout=Vin+N*{（C∕(C+Cs)?*Vd-Vd-Iout∕[(C+Cs)*Fosc]}-Vd；
By above formula as seen, can change by changing N value and C value in the present embodiment the output valve of output voltage V out.
Such as, the integrated circuit 100 that boosts that the present embodiment is provided is applied to the tuner use, and when integrated circuit 100 that the present invention is boosted is applied to the tuner special use, namely this input voltage that boosts integrated circuit 100 is got low tension signal+5V commonly used, with this+the low tension signal of 5V boosts to+high-voltage signal of 33V, i.e. output+33V the signal of telecommunication, this moment just can be according to the first load capacitance C1, the capacitance C of C2, C3 in input voltage, the output voltage decision formula and the progression N value of charge pump.
Therefore, the circuit structure that adopts in the integrated circuit 100 that boosts that the present embodiment provides flexibly and can according to various actual needs by adjusting the first parasitic capacitance CS1, CS2, CS3 capacitance C and the progression of charge pump determine flexibly according to actual conditions, stronger in the flexibility of circuit design.
In the present embodiment, the integrated circuit 100 that boosts of the present embodiment can be packaged into the form of IC chip, can but be not limited to: the SOT-23 patch chip, as shown in Figure 3, this chip has three pins, wherein pin 301 is earth terminal, and pin 302 is input access terminal, and pin 303 is the Voltage-output terminal.
Preferred complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor is called for short CMOS) the semiconductor integrated circuit manufacture craft that adopts is made the integrated circuit of the present embodiment, obtains the CMOS integrated circuit (IC) chip.
The first voltage stabilizing didoe D1 in the present embodiment, the second voltage stabilizing didoe D2, the 3rd voltage stabilizing didoe D3, the 4th voltage stabilizing didoe D4 preferably adopt metal-oxide-semiconductor diode (building up the MOS diode), can need to not add in addition one deck mask in manufacture process with the CMOS process compatible of integrated IC chip like this and increase manufacturing cost.
Preferably adopt in the present embodiment the CMOS technique manufacturing of 0.18 μ m granularity to obtain the integrated circuit 100IC chip that boosts of the present embodiment.
Adopt the mode of integrated circuit (IC) chip can be so that the performance of whole circuit is more stable, and the volume of circuit be little.
Referring to shown in Figure 3, carry out in the actual application at the integrated circuit 100 that boosts with the present embodiment, can further overlap peripheral circuit at the integrated circuit 100 that boosts for the present embodiment according to reality: input filter circuit.This input filter circuit can be the cathode terminal that is connected electrically in the 4th voltage stabilizing didoe D4 in the 1st grade of charge pump electronic circuit of the integrated circuit 100 that boosts by being connected electrically in respectively input pin 302(actual) on high-frequency filter capacitor Co1, low frequency filtering capacitor C 2.Wherein the capacitance of high-frequency filter capacitor Co1 can but be not limited to select 100PF, the capacitance of low frequency filtering capacitor C o2 can but be not limited to select 4.7 μ F.Like this interference signal in the input low tension signal can be before the integrated circuit 100 that boosts of input the present embodiment in advance this removals high frequency and low-frequency interference signal so that the signal source stability of inputting is higher, be conducive to reduce the interference of output electrical signals.
Referring to shown in Figure 3, carry out in the actual application at the integrated circuit 100 that boosts with the present embodiment, can further overlap peripheral circuit at the integrated circuit 100 that boosts for the present embodiment according to reality: the output filtering load circuit specifically comprises output filter capacitor C3 and output load resistance R1.Wherein be connected electrically on the output pin 303 of the integrated circuit 100 that boosts of the present embodiment (actual is the negative electrode that is connected electrically in the first voltage stabilizing didoe D1 of the N level charge pump electronic circuit in the integrated circuit 100 that originally boosts), output load resistance R1 is electrically connected in series on the output pin 303 of the integrated circuit 100 that boosts of the present embodiment (actual is the negative electrode that is connected electrically in the first voltage stabilizing didoe D1 of the N level charge pump electronic circuit in the integrated circuit 100 that originally boosts) and externally exports supply power voltage the other ground of this output filter capacitor Co3.Like this, the higher pressure signal of telecommunication of externally exporting at the integrated circuit 100 that boosts of the present embodiment is being input to outside consuming parts (such as the tuner in the present embodiment) before, pass through in advance the filtering of other ground output filter capacitor Co3, export through the dividing potential drop of output load resistance R1+the utilization voltage VTu of 33V is to consuming parts, the resistance value of this output load resistance R1 can be selected according to actual needs, this output filter capacitor Co3 capacitance is 2.2nF in the present embodiment, and the resistance value of output load resistance R1 is 270K Ω.
The above technical scheme that the embodiment of the invention is provided is described in detail, used specific case herein principle and the execution mode of the embodiment of the invention are set forth, the explanation of above embodiment is only applicable to help to understand the principle of the embodiment of the invention; Simultaneously, for one of ordinary skill in the art, according to the embodiment of the invention, all will change on embodiment and range of application, in sum, this description should not be construed as limitation of the present invention.
Claims (9)
1. the integrated circuit that boosts is characterized in that, comprising: clock oscillation circuit, charge pump circuit, voltage stabilizing circuit, wherein,
Described clock oscillation circuit is electrically connected with described charge pump circuit, is used to described charge pump circuit that clock frequency signal is provided,
The external outside input low-voltage signal of the input of described low noise circuit, output is electrically connected with described voltage stabilizing circuit; Wherein,
Described charge pump circuit comprises that by the charge pump electronic circuit of N level concatenated in order, output loading the electric circuit constitute, wherein N is natural number;
Each charge pump electronic circuit comprises respectively:
The first voltage stabilizing didoe (D1) that is electrically connected in series mutually, electrical quantity is identical, the second voltage stabilizing didoe (D2), the 3rd voltage stabilizing didoe (D3), the 4th voltage stabilizing didoe (D4),
The first parasitic capacitance (CS1), the second parasitic capacitance (CS2), trixenie electric capacity (CS3) between the negative pole end that is connected electrically in respectively described the second voltage stabilizing didoe (D2), the 3rd voltage stabilizing didoe (D3), the 4th voltage stabilizing didoe (D4) and the earth terminal, that electrical quantity is identical
Be connected electrically in the 3rd load capacitance (C3) of negative pole end and the described clock frequency signal first input end of described voltage stabilizing didoe D4,
Be connected electrically in second load capacitance (C2) of negative pole end and described clock frequency signal the second input of described voltage stabilizing didoe D3,
Be connected electrically in first load capacitance (C1) of negative pole end and the described clock frequency signal first input end of described voltage stabilizing didoe D2,
The electrical quantity of wherein said the first load capacitance (C1), the second load capacitance (C2), the 3rd load capacitance (C3) is identical;
Wherein the positive terminal of the 4th voltage stabilizing didoe (D4) in the 1st grade of charge pump electronic circuit can the external described outer low pressure signal of telecommunication, and the negative pole of first voltage stabilizing didoe (D1) of described N level charge pump electronic circuit is by the outside required high-voltage signal of output of described pressurizer.
2. the integrated circuit that boosts according to claim 1 is characterized in that,
Described pressurizer is: mutual other earth capacitance (Cout) in parallel and the RC filter circuit of other earth resistance (R) composition,
First voltage stabilizing didoe (D1) of described N level charge pump electronic circuit is outwards exported required high-voltage signal by described pressurizer: specifically,
The negative electricity of first voltage stabilizing didoe (D1) of one end N level charge pump electronic circuit of described RC filter circuit connects, other end ground connection.
3. the integrated circuit that boosts according to claim 1 is characterized in that,
Described the first voltage stabilizing didoe (D1), the second voltage stabilizing didoe (D2), the 3rd voltage stabilizing didoe (D3), the 4th voltage stabilizing didoe (D4) are metal-oxide-semiconductor diode.
4. the integrated circuit that boosts according to claim 1 is characterized in that,
The described integrated circuit that boosts is the complementary metal oxide semiconductors (CMOS) packaged chip.
5. the integrated circuit that boosts according to claim 4 is characterized in that,
The described integrated circuit complementary metal-oxide semiconductor (MOS) packaging technology granularity of boosting is 0.18 μ m.
6. the integrated circuit that boosts according to claim 4 is characterized in that,
The described integrated circuit that boosts is the SOT-23 encapsulation.
7. according to claim 1 to 6 the arbitrary described integrated circuit that boosts, it is characterized in that, also comprise:
Input filter circuit, the positive terminal that is connected to the 4th voltage stabilizing didoe (D4) in the 1st grade of charge pump electronic circuit of described charge pump circuit is electrically connected with high-frequency filter capacitor (Co1), low frequency filtering electric capacity (Co2) also otherly.
8. the integrated circuit that boosts according to claim 7 is characterized in that, also comprises following peripheral circuit:
The capacitance of described high-frequency filter capacitor (Co1) is 100PF,
The capacitance of described low frequency filtering electric capacity (Co2) is 4.7 μ F.
9. the integrated circuit that boosts according to claim 1 is characterized in that, also comprises following peripheral circuit:
Output filter capacitor (Co3) is connected electrically between the negative electricity and ground of the first voltage stabilizing didoe (D1) of described N level charge pump electronic circuit;
Output load resistance (R1) is electrically connected in series in the negative pole end of first voltage stabilizing didoe (D1) of described N level charge pump electronic circuit, externally exports supply power voltage.
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| CN2011102390997A CN102957315A (en) | 2011-08-19 | 2011-08-19 | Boost integrated circuit for tuner |
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| CN2011102390997A CN102957315A (en) | 2011-08-19 | 2011-08-19 | Boost integrated circuit for tuner |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103490617A (en) * | 2013-08-29 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | Negative voltage charge pump circuit |
| WO2015100631A1 (en) * | 2013-12-31 | 2015-07-09 | 无锡华润矽科微电子有限公司 | Silicon microphone and special integrated circuit therein |
| CN106406418A (en) * | 2015-07-28 | 2017-02-15 | 株式会社电装 | Switching element driving circuit |
| CN110326205A (en) * | 2017-01-30 | 2019-10-11 | ams有限公司 | Electric pressure converter and the method converted for voltage |
| CN111490675A (en) * | 2019-01-29 | 2020-08-04 | 合肥格易集成电路有限公司 | Charge pump circuit, nonvolatile memory and method for controlling output voltage of charge pump |
| CN113824317A (en) * | 2021-10-28 | 2021-12-21 | 福州京东方光电科技有限公司 | Charge pump, power supply driving circuit and display |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101034536A (en) * | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | Charge pump circuit in TFT driving circuit |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101034536A (en) * | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | Charge pump circuit in TFT driving circuit |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103490617A (en) * | 2013-08-29 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | Negative voltage charge pump circuit |
| WO2015100631A1 (en) * | 2013-12-31 | 2015-07-09 | 无锡华润矽科微电子有限公司 | Silicon microphone and special integrated circuit therein |
| CN106406418A (en) * | 2015-07-28 | 2017-02-15 | 株式会社电装 | Switching element driving circuit |
| CN110326205A (en) * | 2017-01-30 | 2019-10-11 | ams有限公司 | Electric pressure converter and the method converted for voltage |
| US10972004B2 (en) | 2017-01-30 | 2021-04-06 | Ams Ag | Voltage converter and method for voltage conversion |
| CN111490675A (en) * | 2019-01-29 | 2020-08-04 | 合肥格易集成电路有限公司 | Charge pump circuit, nonvolatile memory and method for controlling output voltage of charge pump |
| CN113824317A (en) * | 2021-10-28 | 2021-12-21 | 福州京东方光电科技有限公司 | Charge pump, power supply driving circuit and display |
| CN113824317B (en) * | 2021-10-28 | 2022-11-11 | 福州京东方光电科技有限公司 | Charge pump, power supply driving circuit and display |
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Application publication date: 20130306 |