CN102956630A - Three-dimensional integrated semiconductor system and method for forming the same - Google Patents

Three-dimensional integrated semiconductor system and method for forming the same Download PDF

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Publication number
CN102956630A
CN102956630A CN2012102826708A CN201210282670A CN102956630A CN 102956630 A CN102956630 A CN 102956630A CN 2012102826708 A CN2012102826708 A CN 2012102826708A CN 201210282670 A CN201210282670 A CN 201210282670A CN 102956630 A CN102956630 A CN 102956630A
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China
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semiconductor
material layer
dimensional integrated
seoi substrate
electromagnetic radiation
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CN2012102826708A
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CN102956630B (en
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比什-因·阮
玛丽亚姆·萨达卡
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Sony Semiconductor Solutions Corp
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Soitec SA
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Priority claimed from US13/206,299 external-priority patent/US8842945B2/en
Priority claimed from FR1157423A external-priority patent/FR2979169B1/en
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Abstract

The invention relates to a three dimensionally integrated semiconductor system and a method for forming the same. Three dimensionally integrated semiconductor system includes a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. The method of forming such system includes forming the photoactive device on the SeOI substrate, and operatively coupling an waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. The semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.

Description

The method of three-dimensional integrated semiconductor system and this three-dimensional integrated semiconductor system of formation
Technical field
The disclosure relates to the bond semiconductor structure of utilizing three-dimensional (3D) integrated technology, and relates to the bond semiconductor structure that forms by this method.More particularly, the disclosure relates to the three-dimensional integrated semiconductor system of at least a portion of comprising at least one light-sensitive device and semiconductor-on-insulator (SeOI) substrate, and relates to the method that forms this three-dimensional integrated semiconductor system.
Background technology
The three-dimensional of two or more semiconductor structures (3D) is integrated can to produce many benefits to microelectronic applications.For example, the 3D of micromodule is integrated can to obtain improved electrical property and power consumption, reduces simultaneously the area of the device area of coverage (footprint).For example, referring to " The Handbook of 3D Integration, " Wiley-VCH(2008 of the people such as P.Garrou).The 3D of semiconductor structure is integrated can be by being attached to one or more additional semiconductor dies (namely with semiconductor element (die), tube core is to tube core (D2D)), semiconductor element is attached to one or more semiconductor wafer (namely, tube core is to wafer (D2W)) and semiconductor wafer is attached to one or more additional semiconductor wafer (namely, wafer is to wafer (W2W)), or their combination and occuring.
Although three-dimensional integration technology successfully has been applied to electronic integrated circuit, still there are the needs to the method for three-dimensional integrated photon integrated circuit (IC) system and this system of formation in this area.
Summary of the invention
Provide content of the present invention, to introduce the selection of design by reduced form.Below, in the detailed description of embodiment execution mode of the present disclosure, these designs are described in more detail.Content part of the present invention is not intended to identify key feature or the essential feature of purport required for protection, neither be intended to be used to limit the scope of purport required for protection.
In some embodiments, the disclosure comprises three-dimensional integrated semiconductor system.This system comprises: semiconductor-on-insulator (SeOI) substrate, and this SeOI substrate comprises semiconductor material layer, and electrical insulation material layer, the first type surface of this electrical insulation material layer and semiconductor material layer is adjacent to arrange.This system also comprises: at least one light-sensitive device, and this at least one light-sensitive device is formed on the semiconductor material layer of SeOI substrate; With at least one optical interconnection, this at least one optical interconnection comprises the part of the semiconductor material layer of SeOI substrate.This at least one optical interconnection operationally is coupled to this at least one light-sensitive device.This system also comprises: at least one current/voltage converter, this at least one current/voltage converter is formed on the semiconductor material layer of SeOI substrate.At least one electric pathway extends between at least one light-sensitive device and at least one current/voltage converter.At least one semiconductor device is bonded on the SeOI substrate, and at least one electric pathway is at least one current/voltage converter and be bonded between at least one semiconductor device on the SeOI substrate and extend.
In additional execution mode, the disclosure comprises the method for making this three-dimensional integrated semiconductor system.For example, the method for making three-dimensional integrated semiconductor system can may further comprise the steps: the semiconductor material layer at semiconductor-on-insulator (SeOI) substrate forms at least one light-sensitive device.Can form at least one waveguide, this at least one waveguide comprises the part of the semiconductor material layer of SeOI substrate.This at least one waveguide can operationally couple with at least one light-sensitive device.At least one current/voltage converter can be formed on the semiconductor material layer of SeOI substrate, and this at least one light-sensitive device can operationally couple each other with this at least one current/voltage converter.At least one semiconductor device can be bonded on the SeOI substrate, and this at least one current/voltage converter can operationally couple each other with this at least one semiconductor device that is bonded on the SeOI substrate.
Description of drawings
Although this specification is to particularly point out and the clearly claimed claims end that is counted as the content of embodiment of the present invention; but when read in conjunction with the accompanying drawings; according to the description to the concrete example of execution mode of the present disclosure, the advantage of execution mode of the present disclosure can more easily be determined.Wherein:
Fig. 1 is the simplification of semiconductor-on-insulator (SeOI) substrate and the cross-sectional side view of schematic illustration;
Fig. 2 is illustrated in light-sensitive device and the simplification of current/voltage converter and the cross-sectional side view of schematic illustration of making on the SeOI substrate of Fig. 1;
Fig. 3 is the simplification of waveguide and the stereogram of schematic illustration, and this waveguide comprises the part of semi-conducting material of the SeOI substrate of Fig. 2;
Fig. 4 is the simplification of the three-dimensional integrated semiconductor of illustration system and the cross-sectional side view of schematic illustration, and this three-dimensional integrated semiconductor system is included in a plurality of semiconductor device that engage on the structure of Fig. 2 and operationally couple with the structure of Fig. 2;
Fig. 5 to be illustration similar to the three-dimensional integrated semiconductor system of Fig. 4 simplification of another three-dimensional integrated semiconductor system and the cross-sectional side view of schematic illustration, but wherein, the part of SeOI substrate, light-sensitive device, and current/voltage converter is inverted with respect to the structure of Fig. 4;
Fig. 6 to be illustration similar to the three-dimensional integrated semiconductor system of Fig. 4 simplification of another three-dimensional integrated semiconductor system and the cross-sectional side view of schematic illustration, but also comprise the additional optical sensing device that is manufactured on the SeOI substrate and operationally couples with the first light-sensitive device;
Fig. 7 is the simplification of germanium on silicon emitter device and the cross-sectional side view of schematic illustration, and it can be adopted to additional optical sensing device shown in Figure 6;
Fig. 8 to be illustration similar to the three-dimensional integrated semiconductor system of Fig. 5 simplification of another three-dimensional integrated semiconductor system and the cross-sectional side view of schematic illustration, but the additional optical sensing device that also comprises on the structure that vertically is bonded on Fig. 5 and operationally couple with the first light-sensitive device;
Fig. 9 to be illustration similar to the three-dimensional integrated semiconductor system of Fig. 8 simplification of another three-dimensional integrated semiconductor system and the cross-sectional side view of schematic illustration, but also comprise as shown in Figure 6 the additional optical sensing device that is manufactured on the SeOI substrate and operationally couples with the first light-sensitive device; And
Figure 10 is the rough schematic view that comprises the three-dimensional integrated semiconductor system of electromagnetism transceiver.
Embodiment
The illustration that this paper presents not is the actual view that means any particular semiconductor structure, device, system or method, and is only used for describing the idealized expression of execution mode of the present disclosure.
Any title used herein should not be considered as limiting the scope of the embodiments of the present invention that limit such as following claims and legal equivalents thereof.The design of describing in any specific title can run through whole specification usually uses in other parts.
This paper has quoted many lists of references, and its whole disclosures are incorporated this paper by reference and all into, to be used for all purposes.And no matter which type of feature this paper has, and the list of references of quoting is not admitted to be the prior art relative with the present invention of the claimed theme of this paper.
As used herein, term " semiconductor structure " means and is included in any structure of using in the formation of semiconductor device.Semiconductor structure for example comprises tube core and wafer (for example, bearing substrate and device substrate), and comprises each other three-dimensional two or more integrated tube cores and/or composite construction or the assembly of wafer.Semiconductor structure also comprises the semiconductor structure (that is, semiconductor device) of making fully and is making the intermediate structure that forms during the semiconductor device.
As used herein, term " processing semiconductor structure " means and comprises any semiconductor structure that comprises one or more device architecture that forms at least in part.The processing semiconductor structure is the subset of semiconductor structure, and all the processing semiconductor structure all be semiconductor structure.
As used herein, term " bond semiconductor structure " means and comprises any structure that comprises two or more semiconductor structures that are attached at together.The bond semiconductor structure is the subset of semiconductor structure, and all bond semiconductor structures all are semiconductor structures.And, comprise one or more the bond semiconductor structure of processing semiconductor structure also be processing semiconductor structure.
As used herein, term " device architecture " means and comprises the following any part of processing semiconductor structure, this any part as, comprise or at least a portion of active or passive block of limiting semiconductor device to be formed on this semiconductor structure or to be formed in this semiconductor structure.For example, device architecture comprises the active and passive block of integrated circuit, such as transistor, transducer, capacitor, resistor, conducting wire, conductive through hole and conductive contact pad.
As used herein, term " semiconductor device " means and comprises any fully processing and exercisable semiconductor structure, as comprises that available operation set becomes semiconductor chip or the encapsulation of circuit.Semiconductor device for example comprises: E-signal processor (for instance, such as laser or other emitter device and electrooptic modulator driver), electronic memory device, and the semiconductor device that comprises light-sensitive device.
As used herein, term " three-dimensional integrated semiconductor system " means and comprises the semiconductor structure of any joint that has comprised two or more semiconductor device that operationally couple each other.
As used herein, term " electric interconnection " mean and comprise in the semiconductor structure, be used at least a portion by current path is provided with any conductive features of these at least two device architecture electric interconnections or the combination of feature between at least two device architectures of this semiconductor structure.
As used herein, term " connect wafer interconnect (through wafer interconnect) " or " TWI " mean and comprise at least a portion of passing the first semiconductor structure any conductive through hole that extend, that be used for providing between the first semiconductor structure and the second semiconductor structure across the interface between the first semiconductor structure and the second semiconductor structure structure and/or electric interconnection.Connect wafer interconnect and also call with other term in this area, such as " perforation silicon through hole ", " perforation substrate through-hole ", " perforation wafer via ", or the writing a Chinese character in simplified form of this term, such as " TSV " or " TWV ".TWI typically usually runs through this semiconductor structure extension along the direction (that is, along the direction that is parallel to " Z " axle) perpendicular to the common smooth first type surface of semiconductor structure.The perforation wafer interconnect is a type of electric interconnection.
As used herein, term " optical interconnection " mean and comprise in the semiconductor structure, being used for providing between at least two optic structure of this semiconductor structure can be by any features of the path of one or more wavelength conducting electromagnetic radiation.Although use term " optics ", but optical interconnection can be used for providing path for one or more wavelength of electromagnetic radiation, these wavelength can be within the visible region of this electromagnetic radiation spectrum or outside (for example, being within the visible region of electromagnetic radiation spectrum and in the infrared region one or two).Optical interconnection comprises: waveguide, optical through-hole (OV) and perforation wafer optical through-hole (TWOV).
As used herein, term " light-sensitive device " mean and comprise any such device architecture, this device architecture be configured in response to the curtage that is applied to this device architecture electromagnetic radiation-emitting and/or in response to electromagnetic radiation on this device architecture impact and generation current or voltage.Thus, light-sensitive device comprises the optical transmitting set such as light-emitting diode, laser etc., and photodetector, solar cell, and is configured to detect or other device architecture of receiving electromagnetic radiation.
As used herein, term " current/voltage converter " means and comprises that being configured to convert the electric current input to voltage signal exports, and perhaps converts the voltage input to any device of current signal output.For example, current/voltage converter can comprise in the electric integrated circuit, be configured to electric current input is converted to voltage signal output or converts the voltage input to current signal a plurality of device architectures output, that operationally couple each other, such as transistor, capacitor, and resistor.The current/voltage converter that is configured to electric current input is converted to voltage signal output is commonly called " transimpedance amplifier " in the art.
As used herein, term " metal layer " means and comprises processing semiconductor structure, this processing semiconductor structure comprise for along at least a portion conduction current of electric pathway with lower one or more: conducting wire, conductive through hole and conductive contact pad.
In some embodiments, the disclosure comprises three-dimensional integrated semiconductor system, this three-dimensional integrated semiconductor system comprise with the SeOI substrate at least one light-sensitive device of operationally coupling of at least one current/voltage converter.
Fig. 1 is the simplification cross-sectional side view of the SeOI substrate 100 that can adopt in execution mode of the present disclosure.As shown in Figure 1, SeOI substrate 100 comprises semiconductor material layer 102, and electrical insulating material (that is, the dielectric material) layer 104 that is adjacent to arrange with the first type surface 103 of semiconductor material layer 102.
In some embodiments, semiconductor material layer 102 can be the semi-conducting material of monocrystalline roughly at least.The unrestriced mode by example, semiconductor material layer 102 can comprise monocrystalline silicon, germanium, or IIIV family semi-conducting material, and can be doped or undope.In additional execution mode, semi-conducting material 102 can comprise polycrystalline or non-crystalline material.In some embodiments, semiconductor material layer 102 can comprise the epitaxial loayer of semi-conducting material.And in some embodiments, semi-conducting material 102 can comprise the lamination of a plurality of semiconductor material layers.Comprise in the execution mode of silicon at semiconductor material layer 102, SeOI substrate 100 can comprise that this area is called as " silicon-on-insulator " (SOI) substrate of substrate.
Semiconductor material layer 102 can be relatively thin.For example, in some embodiments, semiconductor material layer 102 can have about one micron (1 μ m) or less average total thickness, about 500 nanometers (500nm) or less average total thickness, or even about 10 nanometers (10nm) or less average total thickness.
Electrical insulating material 104 for example can comprise ceramic material, such as nitride (silicon nitride (for example, Si 3N 4)), or oxide (for example, silicon dioxide (SiO 2)) or such as aluminium oxide (Al 2O 3) metal oxide.In some embodiments, electrical insulating material 104 can comprise the lamination of these material layers.Comprise in the execution mode of oxide at electrical insulating material 104, electrical insulation material layer 104 can comprise that this area is called as the layer of " buried oxide layer (BOL) ".
In some embodiments, electrical insulation material layer 104 can have about 500 nanometers (500nm) or less average total thickness, about 200 nanometers (200nm) or less average total thickness, or even about 20 nanometers (10nm) or less average total thickness.
Optionally, semiconductor material layer 102 and electrical insulation material layer 104 can be arranged in the substrate 106 of bulk substrate material and by substrate 106 carryings.Electrical insulation material layer 104 can be arranged between semiconductor material layer 102 and the substrate 106.The unrestriced mode by example, substrate 106 can comprise: semi-conducting material, such as in above-mentioned those materials relevant with semi-conducting material 102 any; Perhaps insulating material is such as in above-mentioned those materials relevant with electrical insulating material 104 any.In some embodiments, substrate 106 can also comprise sandwich construction, and this sandwich construction comprises two or more different materials.
As a unrestricted example, SeOI substrate 100 shown in Figure 1 can utilize this area to be called as SMART-CUT TMThe technique of technique forms.This technique is for example described in detail in following patent: the U.S. Patent No. RE39 of Bruel, 484(2007 issued February 6), the people's such as Aspar U.S. Patent No. 6,303,468(2001 issued October 16), the people's such as Aspar U.S. Patent No. 6,335,258(2002 issued January 1), the people's such as Moriceau U.S. Patent No. 6,756,286(2004 issued June 29), the people's such as Aspar U.S. Patent No. 6,809,044(2004 issued October 26), and the people's such as Aspar U.S. Patent No. 6,946,365(2005 issued September 20), its disclosed content is all integrated with in this by reference.
Briefly, relatively thick semiconductor material layer can be engaged to the first type surface 105 of electrical insulation material layer 104.Relatively thick semiconductor material layer can have with to be arranged on electrical insulation material layer 104 on the identical composition of the composition of semiconductor material layer 102, semiconductor material layer 102 finally can be formed by the relatively thick layer first type surface 105 that is engaged to electrical insulation material layer 104, semiconductor material layer, and comprises the part that it is relatively thin.
After relatively thick semiconductor material layer is engaged to electrical insulation material layer 104, can make relatively thick semiconductor material layer attenuation, to form the relatively thin semiconductor material layer 102 of Fig. 1.The part of relatively thick semiconductor material layer can be removed from relatively thin semiconductor material layer 102, the back is at the surface of electrical insulating material 104 105 remaining relatively thin semiconductor material layers 102.
For semiconductor material layer 102 that will be relatively thin separates with the remainder of relatively thick semiconductor material layer, the Implantation plane that can be orientated along the major surfaces in parallel ground with semiconductor material layer, with different kinds of ions (for example, hydrogen ion, helium ion, or one or more of in the inert gas ion) be injected in the relatively thick semiconductor material layer.In some embodiments, this different kinds of ions can be injected in this semiconductor material layer before or after semiconductor material layer being engaged to electrical insulation material layer 104 and substrate 106.
Ion can be along injecting with the direction of semiconductor material layer approximate vertical.As known in the art, be to be used for the function of these Implantations to the energy of this semiconductor material layer Implantation at least in part to the degree of depth in the semiconductor material layer.In general, will inject with the relatively shallow degree of depth with the ion of more low-yield injection, and will inject with the relatively dark degree of depth with the ion that higher-energy is injected.
Ion can be injected in the semiconductor material layer with predetermined power, and this predetermined power is selected to the degree of depth ion in this semiconductor material layer with hope, and this degree of depth will be determined the thickness of semiconductor material layer 102.As known in the art, at least some ions can be injected with other degree of depth except the injection degree of depth of hope, and as the figure of the ion concentration of the function of the degree of depth from the surface of semiconductor material layer to this semiconductor material layer can show with the injection degree of depth of hope, have a peaked curve that is generally bell (symmetrical or asymmetric).
With after Implantation is in semiconductor material layer, these ions can limit the Implantation plane in this semiconductor material layer.This Implantation plane can comprise in this semiconductor material layer, with this semiconductor material layer in layer or the zone of the planar registration with maximum ion concentration (for example, centered by it).This Implantation plane can limit the weak area in this semiconductor material layer, and this semiconductor material layer can be rived or splits along this weak area in technique subsequently.For example, semiconductor material layer can be heated, so that this semiconductor material layer is rived along the Implantation plane or split.Optionally, can apply mechanical force to semiconductor material layer, so that or help this semiconductor material layer to rive along the Implantation plane.
In additional execution mode, with relatively thick semiconductor material layer (for example can pass through, have the layer greater than about 100 microns average thickness) be engaged to electrical insulation material layer 104 and substrate 106, and (for example utilize subsequently chemical technology, wet chemical etch or dry method chemical etching technique), mechanical technology (for example, polishing (grinding) or grinding (lapping) technique), perhaps by chemico-mechanical polishing (chemical-mechanical polishing:CMP) technique semiconductor material layer that this is relatively thick from itself and an on the contrary side attenuation of substrate 106, relatively thin semiconductor material layer 102 is arranged in electrical insulation material layer 104 and the substrate 106.
In another execution mode, relatively thin semiconductor material layer 102 can be formed on the spot 105 tops, surface (for example, on it) of electrical insulation material layer 104.For example, the SeOI substrate 100 of Fig. 1 can be by will be such as silicon, polysilicon, or the semiconductor material deposition of amorphous silicon forms to the thickness of wishing on the surface 105 of electrical insulation material layer 104.For example, can form relatively thin semiconductor material layer 102 with plasma enhanced chemical vapor deposition.
In some embodiments, can be after being transferred to relatively thin semiconductor material layer 102 on the electrical insulation material layer 104, the semiconductor material layer 102 that this is relatively thin thickens.For example, can be at the first type surface growth of the exposure of relatively thin semiconductor material layer 102 or the additional semi-conducting material (for example, Si, SiGe, Ge, III-V family semi-conducting material etc.) of deposition otherwise.The final thickness of semiconductor material layer 102 can depend on the lattice mismatch between semiconductor material layer 102 and the electrical insulation material layer 104, and will on the semiconductor material layer 102 or among the thickness requirement of the device made.
Three-dimensional integrated system can utilize SeOI substrate 100 to make, as following discussed in detail.
Fig. 2 is the simplification of processing semiconductor structure 110 and the cross-sectional side view of schematic illustration of illustration, this processing semiconductor structure comprise at least one light-sensitive device 112 and at least one current/voltage converter 114 of having made at the SeOI of Fig. 1 substrate 100.This light-sensitive device 112 can be formed on the semiconductor material layer 102 of SeOI substrate 100.This current/voltage converter 114 also can be formed on the different range or zone of semiconductor material layer 102 of SeOI substrate 100.
In some embodiments, light-sensitive device 112 can comprise photodetector, and this photodetector is configured to, in response to electromagnetic radiation on this photodetector impact and generate electric current.The electric current that generates by this photodetector can be transported to current/voltage converter 114.In additional execution mode, light-sensitive device 112 can comprise optical transmitting set, and this optical transmitting set is configured to, and generates ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and this signal of telecommunication input can be provided by current/voltage converter 114.For example, this optical transmitting set can comprise light-emitting diode (LED) or laser device, and this laser device is configured to launch at least roughly relevant electromagnetic radiation.
As a unrestricted example, light-sensitive device can comprise photodiode, and this photodiode comprises at least one PN junction that is set to as photodetector work.As shown in Figure 2, photodetector can comprise the first district 120, and this first district comprises the mix silicon (for example, be doped with in boron or the gallium one or more of) of (P+) by relatively light P.This silicon can comprise the part of the semiconductor material layer 102 of SeOI substrate 100.Can form in the first district 120 and comprise by mix one or more of silicon of (P++) of phase counterweight P and electrically contact district 122.Photodetector can comprise Second Region 124, and this Second Region 124 comprises and be arranged in the first district 120 and the block intrinsic germanium that contacts with the first district 120 direct physical, as shown in Figure 2.Comprise that mix (N++) the 3rd district 126 of (for example, be doped with in nitrogen, phosphorus, arsenic, antimony and the bismuth one or more of) of phase counterweight N is arranged on the second area 124 and with second area 124 direct physical and contacts.
Photodetector shown in Figure 2 can utilize the known conventional photoetching technique of field of manufacturing semiconductor devices to make.For example, can apply mask to the first type surface of the exposure of semiconductor material layer 102, then can carry out composition to mask, to form therein the hole corresponding with the position of wishing formation the first district 120.Then, can pass through this mask, utilize P type dopant that the expose portion of semiconductor material layer 102 is carried out light dope.This mask can be removed, and can deposit the second mask and the second mask is carried out composition, so that the second mask comprises the hole of wishing to electrically contact by its formation district 122.Then, by the second mask, utilize additional P type dopant that the expose portion in the first district 120 is further mixed, to form electrical contacts.Then, the second mask can be removed, and can and electrically contact in the first district 120 of semiconductor material layer 102, photodetector and distinguish dielectric layer 128 on 122.Dielectric layer 128 for example can comprise oxide skin(coating) and/or nitride layer.After dielectric layer 128, can apply mask to the first type surface of the exposure of dielectric layer 128, then can carry out composition to mask, to form therein the hole corresponding with the position in the Second Region 124 of wishing the formation photodetector and the 3rd district 126.Dielectric layer 128 can carry out etching by the mask layer of institute's composition, to form recess in this dielectric layer 128.Optionally, the light P doped silicon of can growing on the spot in the first district 120 is formed in the recess in the dielectric layer 128 the first district 120 is extended to by etching technics.Then, intrinsic germanium can be deposited in the remainder of the recess in the dielectric layer 128, it defines Second Region 124.For forming the 3rd district 126, then, the part of intrinsic germanium can be doped with the N-type dopant.
In above-mentioned structure, light-sensitive device 112 can comprise photodetector, when the electromagnetic radiation of a specific wavelength or a plurality of wavelength is impacted on the regional of light-sensitive device 112, this photodetector is at the generation current between the 122 and the 3rd district 126, district that electrically contacts of light-sensitive device 112, this specific wavelength or a plurality of wavelength are the functions of the special component of regional, as known in the art.
Above-mentioned structure and manufacturing process for light-sensitive device 112 provide as a unrestricted example.The light-sensitive device of various other types is known in the art with the manufacturing process that is used to form these light-sensitive devices, and can adopt in execution mode of the present disclosure.As another example, in additional execution mode, light-sensitive device 112 can comprise the germanium on silicon emitter apparatus, as following described with reference to Fig. 7.
Can be before making light-sensitive device 112, after forming light-sensitive device 112 or with the manufacturing of light-sensitive device 112, combine at least in part, at the zones of different manufacturing current/voltage converter 114 of semiconductor material layer 102.Many current/voltage converters 114 dissimilar and structure are known in the art, and can adopt in execution mode of the present disclosure.These current/voltage converters 114 generally include a plurality of transistors, capacitor and the resistor that operationally couples each other, be configured to convert the electric current input to voltage signal output to provide, perhaps the voltage input is converted to the circuit (for example, integrated circuit) of current signal output.In some embodiments, as light-sensitive device 112 wherein comprise be configured in response to electromagnetic radiation on light-sensitive device 112 impact and the execution mode of the photodetector of generation current, current/voltage converter 114 can comprise transimpedance amplifier, and the electric current input that this transimpedance amplifier is configured to be provided by light-sensitive device 112 converts voltage signal output to.
Technique for the manufacture of each assembly (comprising transistor, capacitor and resistor) of current/voltage converter 114 is that field of semiconductor manufacture is known.And one or more in each assembly of current/voltage converter 114 (such as the channel region of field-effect transistor) can comprise the part of semiconductor material layer 102.
In additional execution mode, current/voltage converter 114 can be formed in another substrate layer, and this another substrate layer can be stacking and be bonded on the semiconductor material layer 102.The conductive features section and the electric interconnection between this current/voltage converter 114 that are formed on the semiconductor material layer 102 or in the semiconductor material layer 102 can limit by vertically extending conductive through hole and horizontally extending conductive trace (for example, the conducting wire of redistribution layer (RDL)).
Processing semiconductor structure 100 can also comprise at least one optical interconnection, and such as waveguide 116, this optical interconnection comprises the part of the semiconductor material layer 102 of SeOI substrate 100.Waveguide 116 can operationally be coupled to light-sensitive device 112, and be provided in the execution mode that light-sensitive device 112 comprises photodetector electromagnetic radiation is delivered to light-sensitive device 112, perhaps comprise in the execution mode of optical transmitting set being carried by the electromagnetic radiation of light-sensitive device 112 emissions with away from this light-sensitive device 112 at light-sensitive device 112.
Waveguide 116 can comprise the part of the isolation of semiconductor material layer 102.Fig. 3 is the simplification stereogram of a part of the structure 110 of Fig. 2, and this part comprises the cross section of waveguide 116.Waveguide 116 can form by following technique: remove semiconductor material layer 102, with this semiconductor material layer 102 be used for limit and comprise the part that the parts transversely of waveguide 116 is adjacent, and use and compare the removed part that another material with different refractivity is replaced this semiconductor material layer 102 with semiconductor material layer 102.For example, can use mask and etching technics, with the part of removal semiconductor material layer 102, and formation and waveguide 116 horizontal adjacent recesses.Then, can be with oxide 130 or other dielectric deposition in these recesses, with the restriction of lateral isolation semiconductor material layer 102 and comprise the part of waveguide 116.
As known in the art, the cross-sectional dimension of waveguide 116 (for example, the width of waveguide 116 and height) will be determined at least in part and can and carry wavelength or the radiation wavelength that does not have remarkable loss by these waveguide 116 guiding with the composition of waveguide 116 and material around.Thus, the material of the wavelength considering to carry by this waveguide 116 or radiation wavelength and encirclement waveguide 116 (such as oxide 130, electrical insulation material layer 104, and dielectric layer 128) is selected the particular dimensions of waveguide 116.
Although the stereogram according to Fig. 2, waveguide 116 is illustrated as the cross side that extends to light-sensitive device 112 in Fig. 2, but in additional execution mode, waveguide 116 can extend in the plane of Fig. 2 or extend this plane, and can extend to and contact the center that electrically contacts the light-sensitive device 112 between the district 122.This structure can improve the efficient of electromagnetic radiation impact on the material of light-sensitive material or light-sensitive device 112 of being carried by waveguide 116.
Referring again to Fig. 2, comprise in the execution mode of photodetector at light-sensitive device 112, electromagnetic radiation can enter waveguide 116 from structure 110 outsides simply.For example, electromagnetic radiation can be impacted at light-sensitive device 112 and/or be configured to carry in the waveguide 116 of electromagnetic radiation to light-sensitive device 112.Light-sensitive device can in response to electromagnetic radiation thereon impact and generation current.In other embodiments, electromagnetic radiation can enter waveguide 116 from another device that couples optically with waveguide 116, then is delivered to light-sensitive device 112 by waveguide 116.
With reference to Fig. 4, three-dimensional integrated semiconductor system 140 can be formed in the following manner by the semiconductor structure 110 of Fig. 2: electrically and operationally at least one light-sensitive device 112 and at least one current/voltage converter 114 are coupled in together, one or more semiconductor device 142A, 142B are bonded on the SeOI substrate 100, and electrically and operationally one or more semiconductor device 142A, the 142B of at least one current/voltage converter 114 on being bonded on SeOI substrate 100 are coupled in.
For example, one or more metal layer 144 can be formed on dielectric layer 128, light-sensitive device 112 and the current/voltage converter 114.These metal layers 144 comprise a plurality of conductive features section 146.This a plurality of conductive features section 146 can comprise one or more in vertically extending conductive through hole, horizontally extending conductive trace and the conductive contact pad.In these conductive features sections 146 at least some can electrically contact with the character pair section (as electrically contacting the 122 and the 3rd district 126, district) of light-sensitive device 112.In these conductive features sections 146 at least some can electrically contact with the character pair section of current/voltage converter 114 (such as resistor, capacitor, with transistorized source area, drain region, and grid structure).These conductive features sections 146 can be formed and comprised metal by metal.Above-mentioned one or more metal layer 144 can be by successively technique (layer-by-layer process) formation, wherein, by metal level and the dielectric materials layer that this mode that forms conductive features section 146 deposits and composition replaces, this conductive features section 146 can be embedded in the dielectric material 148 and by this dielectric material 148 and surround.Conductive features section 146 can be used to form and be provided between this at least one light-sensitive device 112 and this at least one current/voltage converter 114 at least one electric pathway that extends, and be used to form and be provided at this at least one current/voltage converter 114 and will be bonded on SeOI substrate 100(formed light-sensitive device 112 and current/voltage converter 114 on it) on semiconductor device 142A, 142B between at least one electric pathway that extends.In some embodiments, conductive features section 146 can be used to be provided at one or more electric pathways that extend between among semiconductor device 142A, the 142B two or more, so that this semiconductor device 142A, 142B can be coupled to each other electrically and operationally.In this embodiment, two or more among semiconductor device 142A, the 142B can not be directly to couple with current/voltage converter 114 electrically and operationally.In some embodiments, one or more metal layer 144 can comprise that this area is called as the layer of redistribution layer (RDL).
Among one or more semiconductor device 142A, the 142B each can comprise one or more in E-signal processor device, electronic memory device, the additional optical sensing device etc.In some embodiments, be bonded among semiconductor device 142A, the 142B on the SeOI substrate 100 one or more and can comprise E-signal processor.For example, the first semiconductor device 142A can comprise E-signal processor.In this embodiment, the second semiconductor device 142B also can comprise E-signal processor, and perhaps the second semiconductor device 142B can comprise dissimilar semiconductor device, such as electronic memory device or additional optical sensing device.
Among a plurality of semiconductor device 142A, the 142B each can be for example by with on the conductive features section structure such as bond pad on semiconductor device 142A, the 142B and be coupled to electrically one or more metal layer 144 such as bond pad corresponding conductive features section 146, and be bonded on the SeOI substrate 100.The conductive features section of semiconductor device 142A, 142B can for example utilize conductive projection as known in the art or conducting sphere to be engaged to the conductive features section 146 of one or more metal layer 144.In additional execution mode, the conductive features section of semiconductor device 142A, 142B can utilize direct joint technology to be engaged to the conductive features section 146 of one or more metal layer 144.
Being engaged to the joining technique of using in second half conductor structure, a semiconductor structure can classify differently, a kind of whether intermediate layer of material being arranged between two semiconductor structures so that they are bonded together, and being joint interface, the second whether allow electronics (that is, electric current) to pass this interface.So-called " directly joint method " be between two semiconductor structures, set up direct solid to the Solid-state Chemistry bonding so that they are bonded together, and the method that needn't between two semiconductor structures, utilize the inter-engagement material that they are bonded together.Develop direct metal to metal bonding method, be used for the metal material of the surface of the first semiconductor structure is engaged to the metal material of the surface of the second semiconductor structure." hot press " method is direct joint method, wherein, with the high temperature of (and usually between about 300 degrees centigrade (300 ℃) and about 400 degrees centigrade (400 ℃)) between 200 degrees centigrade (200 ℃) and about 500 degrees centigrade (500 ℃), between composition surface, exert pressure.Additional direct joint method can be carried out with 200 degrees centigrade (200 ℃) or lower temperature.This direct joint technology of carrying out with 200 degrees centigrade (200 ℃) or lower temperature is referred to herein as " ultralow temperature (ultra-low temperature) " directly joint method.The direct joint method of ultralow temperature can pass through careful surface impurity and the surface compound (for example, native oxide) removed, and carries out by the close contact area that increases between two surfaces by atomic scale.Close contact area between two surfaces is usually through near the value of atomic scale, by exert pressure to produce plastic deformation between composition surface with the reduction surface roughness by the polishing composition surface, perhaps by the polishing composition surface and exert pressure to obtain this plastic deformation both realize.
After by direct physical contact two surfaces being set, engaging ripple (bonding wave) can be beginning and propagates along the interface between these two adjoining surfaces between two adjoining surfaces at the interface.Along with wave surface spreads across the joint interface between two adjoining surfaces, between these two adjoining surfaces, set up direct chemical bonding by wave surface.The direct joint method of some ultralow temperature can be carried out in situation about need to not exert pressure at the joint interface place between the composition surface, although in the direct joint method of other ultralow temperature, can exert pressure at the joint interface place between composition surface, in order to realize suitable bond strength at this joint interface place.The direct joint method of the ultralow temperature of exerting pressure between composition surface is commonly called " surperficial assist in engagement " or " SAB " method in the art.Thus, as used herein, term " surperficial assist in engagement " and " SAB " mean and comprise by making the first material against the second material, and exert pressure any direct joint technology of the first material Direct Bonding to the second material with 200 degrees centigrade (200 ℃) or the lower joint interface place of temperature between composition surface.
Continuation is with reference to Fig. 4, the conductive features section of semiconductor device 142A, 142B can utilize metal to be engaged to (such as hot press technique or the direct joint technology of ultralow temperature, the direct joint technology of this ultralow temperature can comprise or can not comprise surperficial assist in engagement (SAB) technique) the conductive features section 146 of one or more metal layer 144 to the direct joint technology of metal.
In the three-dimensional integrated semiconductor system 140 of Fig. 4, at least one light-sensitive device 112 and being bonded on the public side of one or more semiconductor device 142A on the SeOI substrate 100, electrical insulation material layer 104 that 142B is arranged on this SeOI substrate 100.In addition, at least one current/voltage converter 114 is arranged on the same public side of electrical insulation material layer 104 of SeOI substrate 100, and this public side is a side that is provided with semiconductor material layer 102, and is a side opposite with substrate 106.Yet, in additional execution mode, at least one light-sensitive device 112 and being bonded on the two opposite sides of one or more semiconductor device 142A on the SeOI substrate 100, electrical insulation material layer 104 that 142B can be arranged on this SeOI substrate 100.
For example, Fig. 5 illustration the additional execution mode of similar to the three-dimensional integrated semiconductor system 140 of Fig. 4 three-dimensional integrated semiconductor system 150 roughly, this three-dimensional integrated semiconductor system 150 comprises: light-sensitive device 112, current/voltage converter 114 and waveguide 116.Three-dimensional integrated semiconductor system 150 also utilizes the SeOI substrate 100 of Fig. 1 to form, and comprises semiconductor material layer 102 and electrical insulation material layer 104.Yet in the execution mode of Fig. 5, the substrate 106 of SeOI substrate 100 has been removed during manufacture.From the stereogram of Figure 4 and 5, semiconductor material layer 102, electrical insulation material layer 104, light-sensitive device 112, and current/voltage converter 114 is inverted with respect to the three-dimensional integrated semiconductor system of Fig. 4.
As shown in Figure 5, at least one light-sensitive device 112 and being bonded on the opposite both sides of one or more semiconductor device 142A on the SeOI substrate 100, electrical insulation material layer 104 that 142B can be arranged on this SeOI substrate 100, and at least one light-sensitive device 112 and at least one current/voltage converter 114 are arranged on the public side of electrical insulation material layer of SeOI substrate 100 (Fig. 1).
As shown in Figure 5, three-dimensional integrated semiconductor system 150 comprises and aforementioned metal layer 144 similar one or more metal layer 144', and comprises the 146' of conductive features section that is embedded in the dielectric material 148' and is surrounded by dielectric material 148'.One or more metal layer 144' is arranged on semiconductor material layer 102, light-sensitive device 112 and the current/voltage converter 114 on the public side that is in electrical insulation material layer 104.Yet, in the execution mode of Fig. 5, connect electric pathway that wafer interconnect 152 is used for running through three-dimensional integrated semiconductor system 150 from its side on semiconductor material layer 102 (namely, from three-dimensional integrated semiconductor system 150 source or surface arranged) be passed to its side on electrical insulation material layer 104 dorsal part of three-dimensional integrated semiconductor system 150 (that is, to).
One or more additional metal layer 154 can be formed on the side opposite with one or more metal layer 144' of integrated semiconductor on the electrical insulation material layer 104, three-dimensional system 150.One or more additional metal layer 154 can roughly be similar to aforementioned metal layer 144,144', and can comprise a plurality of conductive features section 156, such as the horizontal-extending conductive trace, vertically extend conductive through hole and conductive welding disk, these conductive features sections can be embedded in the dielectric material 158 and by dielectric material and surround.In some embodiments, one or more metal layer 154 can comprise redistribution layer (RDL).
A plurality of semiconductor device 142A, 142B, 142C can be engaged to conductive features section 156 and/or the dielectric material 158 of (that is, on electrical insulation material layer 104 and the semiconductor material layer 102) one or more metal layer 154 (Fig. 1) on the remainder of SeOI substrate 100.Among a plurality of semiconductor device 142A, 142B, the 142C each can comprise one or more in the previous dissimilar semiconductor device of mentioning with reference to Fig. 4.
The 146' of conductive features section of one or more metal layer 144' can be used to form or additionally be provided at least one electric pathway that extends between at least one light-sensitive device 112 and at least one current/voltage converter 114.In addition, the 146' of conductive features section of one or more metal layer 144', the conductive features section 156 that connects wafer interconnect 152 and/or one or more metal layer 154 can be used to form or additionally be provided at least one current/voltage converter 114 and be bonded on electrical insulation material layer 104 and semiconductor material layer 102(Fig. 1 of SeOI substrate 100) on a plurality of semiconductor device 142A, one or more semiconductor device among 142B, the 142C between at least one electric pathway that extends.
For forming the three-dimensional integrated semiconductor system 150 of Fig. 5, one or more metal layer 144' can be formed on light-sensitive device 112, current/voltage converter 114 and the dielectric layer 128 of processing semiconductor structure 110 of Fig. 2.Then, bearing substrate (for example, bearing wafer) can be bonded on one or more metal layer 144' temporarily, and then, substrate 106 can be removed from structure 110 at least in part.Then, one or more metal layer 154 can be formed on the electrical insulation material layer 104, and perforation wafer interconnect 152 can run through one or more metal layer 154, electrical insulation material layer 104, semiconductor material layer 102 and one or more metal layer 144' formation.Then, a plurality of semiconductor device 142A, 142B, 142C can be engaged to conductive features section 156 and/or the dielectric material 158 of one or more metal layer 154.
In additional execution mode, the present invention includes so three-dimensional integrated semiconductor system, that is, it comprises two or more light-sensitive devices that operationally couple each other.For example, this three-dimensional integrated semiconductor system can comprise: be configured to electromagnetic radiation-emitting at least one optical transmitting set, be configured to receive at least one photodetector by the electromagnetic radiation of optical transmitting set emission, and couple optical transmitting set and photodetector and be configured to optical mode and carry at least one optical interconnection by the electromagnetic radiation of optical transmitting set emission to photodetector.
Fig. 6 illustration the example of such execution mode of three-dimensional integrated semiconductor system 160.The three-dimensional integrated semiconductor system 160 of Fig. 6 roughly is similar to the three-dimensional integrated semiconductor system 140 of Fig. 4, and comprises and being formed on the SeOI substrate 100 and by light-sensitive device 112, the current/voltage converter 114 of SeOI substrate 100 carryings, and waveguide 116.Three-dimensional integrated semiconductor system 160 also comprises one or more metal layer 144, and is bonded on a plurality of semiconductor device 142A, 142B on one or more metal layer 144 and the SeOI substrate 100.Three-dimensional integrated semiconductor system 160 also comprises operationally the additional optical sensing device 162 that couples with the first light-sensitive device 112.For example, additional optical sensing device 162 can comprise optical transmitting set, and this optical transmitting set is configured to electromagnetic radiation-emitting.Optionally, three-dimensional integrated semiconductor system 160 can be included among Fig. 6 illustration schematically and can be used for optionally modulating modulator 164 by the electromagnetic radiation of additional optical sensing device 162 emissions.Waveguide 166 can be from additional optical sensing device 162 to modulator 166 be extended, and waveguide 116 can be extended from modulator 166 to the first light-sensitive device 112, and this first light-sensitive device 112 can comprise the photodetector that is configured to receive modulated electromagnetic radiation.Waveguide 166 can comprise the waveguide of describing with reference to the waveguide 116 of Fig. 3 as previous.Many not isostructures of the photonic modulation device that can make in the SeOI type of substrate are known in the art, and can adopt in execution mode of the present disclosure.
Additional optical sensing device 162 for example can comprise light-emitting diode (LED) or laser device.By the mode of unrestricted example, additional optical sensing device 162 can comprise germanium on silicon (germanium-on-silicon) emitter apparatus 168, as shown in Figure 7.This germanium on silicon emitter apparatus 168 is such as carried out more detailed description in Publication about Document: the people such as X.Sun, the people such as Optics Lett.34 (8) the 1198th page (on April 15th, 2009) and X.Sun, the 1345th page of Optics Lett.34 (9) (on May 1st, 2009), each piece of writing in these documents is all quoted by this its full content is incorporated into this.
With reference to Fig. 7, germanium on silicon emitter apparatus 168 can comprise block P doped silicon 170 and the block N doped germanium 172 that is arranged on this P doped silicon 170.P doped silicon 170 can comprise the part of the semiconductor material layer 102 that has been doped with one or more of P type dopants (for example, be doped with in boron and the gallium one or more of).Block germanium 172 can be doped with one or more N-type dopants (for example, being doped with one or more of in nitrogen, phosphorus, arsenic, antimony and the bismuth), and is mixed on the spot during this block germanium 172 of growth.
Block N doped germanium 172 can be under the state of elongation strain.For example, block germanium 172 can be under the state of from about 0.20% to about 0.25% elongation strain.This elongation strain can by under high temperature (elevated temperature) with chemical vapor deposition (CVD) technique epitaxial growth relaxation attitude block germanium 172 on P doped silicon 170, and cool off subsequently this block germanium 172 and in this block germanium 172, provide.This block germanium 172 can be grown by the high temperature (for example, about 650 ℃) between about 600 ℃ and about 700 ℃, and can be during growth technique complete relaxation.This elongation strain can after deposition, be brought out in this block germanium 172 when this block germanium 172 is cooled to room temperature.Optionally, thermal anneal process after the growth can be used for the value of the elongation strain in the finishing block germanium 172, it will affect the band gap of block germanium 172.
Dielectric material 174 can be deposited on block germanium 172 and the block P doped silicon 170.Dielectric material 174 can comprise as before at dielectric material 128 described herein.The tactile section 176 of N doped polycrystalline silicon can be arranged on the block N doped germanium 172 and with block N doped germanium 172 direct physical and contact.As shown in Figure 7, electrical contacts 178 can pass dielectric material 174 and extend to respectively N doped polycrystalline silicon contact site 176 and block P doped silicon 170, and this electrical contacts 178 can comprise 146(Fig. 6 of conductive features section of one or more metal layer 144).
In this structure, by between electrical contacts 178, applying voltage, and thus, apply voltage across the PN junction between block P doped silicon 170 and the block N doped germanium 172, can make germanium on silicon reflector electromagnetic radiation-emitting, the electromagnetic radiation of launching can have for example wavelength between about 1560 nanometers and about 1620 nanometers.
In additional execution mode, three-dimensional integrated semiconductor system can comprise the additional optical sensing device, this additional optical sensing device is bonded on the SeOI substrate 100, and operationally couples with the first light-sensitive device 112 on the semiconductor material layer 102 that is formed on SeOI substrate 100.
For example, Fig. 8 illustration to similar three-dimensional integrated semiconductor system 180 roughly of the three-dimensional integrated semiconductor system 150 of Fig. 5, this three-dimensional integrated semiconductor system 180 comprises light-sensitive device 112, current/voltage converter 114 and the waveguide 116 that is arranged on semiconductor material layer 102 and the electrical insulation material layer 104.This three-dimensional integrated semiconductor system 180 also comprises one or more metal layer 144', and this metal layer 144' comprises the 146' of conductive features section that is embedded in the dielectric material 148' and is surrounded by dielectric material 148'.Connect electric pathway that wafer interconnect 152 is used for running through three-dimensional integrated semiconductor system 180 from its side on semiconductor material layer 102 (namely, from three-dimensional integrated semiconductor system 180 source or surface arranged) be passed to its side on electrical insulation material layer 104 dorsal part of three-dimensional integrated semiconductor system 180 (that is, to).One or more additional metal layer 154 can be formed on the electrical insulation material layer 104', and one or more additional metal layer 154 can comprise a plurality of conductive features section 156 that is embedded in the dielectric material 158 and is surrounded by dielectric material 158, as front with reference to as described in Fig. 5.A plurality of semiconductor device 142A, 142B, 142C can be engaged to conductive features section 156 and/or the dielectric material 158 of one or more metal layer 154 of (Fig. 1) on the remainder of SeOI substrate 100.
In the execution mode of Fig. 8, additional semiconductor device 142D is bonded on the remainder (Fig. 1) upper (that is, being bonded on electrical insulation material layer 104 and the semiconductor material layer 102) of SeOI substrate 100.Should comprise light-sensitive device by additional semiconductor device 142D.For example, this additional semiconductor device 142D can comprise light-emitting diode (LED) or laser device.By the mode of unrestricted example, additional optical sensing device 162 can comprise germanium on silicon emitter apparatus 168, as front described with reference to Fig. 7.
Light-sensitive device 142D can with the semiconductor material layer 102 that is formed on SeOI substrate 100 on the first light-sensitive device 112 operationally (that is, with optical mode) couple.For example, additional semiconductor device 142D can comprise optical transmitting set, and this optical transmitting set is configured to electromagnetic radiation-emitting.Optionally, this three-dimensional integrated semiconductor system 180 can comprise the same modulator (not shown) of modulator 164 of describing with reference to Fig. 6 as previous, and it can be used for optionally modulating the electromagnetic radiation of being launched by additional semiconductor device 142D.The first light-sensitive device 112 can comprise photodetector, and this photodetector is configured to receive the electromagnetic radiation by the additional semiconductor device 142D emission that comprises optical transmitting set.
This three-dimensional integrated semiconductor system 180 also comprises a plurality of optical interconnections, and these optical interconnections are provided in the light-sensitive device of additional semiconductor device 142D and are formed between at least one light-sensitive device 112 on the semiconductor material layer 102 of SeOI substrate carries electromagnetic radiation.These a plurality of optical interconnections for example can comprise waveguide 116, and this waveguide 116 comprises the part of the semiconductor material layer 102 of SeOI substrate 100, as front with reference to as described in Fig. 2 and 3.A plurality of optical interconnections can comprise that at least one connects wafer optical interconnection 182, this connects wafer optical interconnection 182 along the direction vertical with semiconductor material layer 102 and electrical insulation material layer 104, vertically extends through the three-dimensional integrated semiconductor 180(of system according to the stereogram of Fig. 8).An end of perforation wafer optical interconnection 182 can extend to waveguide 116 and operationally couple with waveguide 116, and the opposite end of this perforation wafer optical interconnection 182 can extend to another waveguide 184 and operationally couple with another waveguide 184, this another waveguide 184 extends to the light-sensitive device of additional semiconductor device 142D from this perforation wafer optical interconnection 182, as shown in Figure 8.
Additional waveguide 184 can comprise the part of additional semiconductor material layer 186.Should can comprise previous any material of describing with semiconductor material layer 102 by additional semiconductor material layer 186 relevantly.Should additional semiconductor material layer 186 can form discretely and be transferred on the dielectric material 188 that is deposited on processing semiconductor device 142A, 142B, the 142C, as shown in Figure 8.In additional execution mode, this additional semiconductor material layer 186 can form (for example, deposition) on the spot on dielectric material 188.
Optionally, adding semiconductor device 142 can be surrounded by additional dielectric material 190 at least in part.And, comprise that the additional waveguide 192 of the part of additional semiconductor material layer 186 can extend to another perforation wafer optical interconnection 194 from additional semiconductor device 142D.This connects wafer interconnect 194 can be used in three-dimensional integrated semiconductor system 180 vertically three-dimensional integrated another additional semiconductor device, and operationally (for example, with optical mode) couples the light-sensitive device of the three-dimensional integrated semiconductor system of the light-sensitive device of this additional semiconductor device and Fig. 8.
Fig. 9 illustration to similar three-dimensional integrated semiconductor system 195 roughly of the three-dimensional integrated semiconductor system 180 of Fig. 8, this three-dimensional integrated semiconductor system 195 comprises light-sensitive device 112, current/voltage converter 114 and the waveguide 116 that is arranged on semiconductor material layer 102 and the electrical insulation material layer 104.Three-dimensional integrated semiconductor system 195 also comprises operationally the additional optical sensing device 162 that couples with the first light-sensitive device 112, and optional modulator 164, as front with reference to as described in Fig. 6.For example, additional optical sensing device 162 can comprise optical transmitting set, and this optical transmitting set is configured to electromagnetic radiation-emitting.Waveguide 166 can be from additional optical sensing device 162 to modulator 166 be extended, and waveguide 116 can be extended from modulator 166 to the first light-sensitive device 112, and this first light-sensitive device 112 can comprise the photodetector that is configured to receive modulated electromagnetic radiation.
This three-dimensional integrated semiconductor system 195 can also comprise a plurality of optical interconnections, these optical interconnections are provided in additional optical sensing device 162 and are formed between at least one light-sensitive device 112 on the semiconductor material layer 102 of SeOI substrate 100 carries electromagnetic radiation, and carries electromagnetic radiation between any other optical module of additional optical sensing device 162 and three-dimensional integrated semiconductor system 195.A plurality of optical interconnections for example can comprise waveguide 116, and this waveguide 116 comprises the part of the semiconductor material layer 102 of SeOI substrate 100, as front with reference to as described in Fig. 2 and 3.These a plurality of optical interconnections can comprise that at least one connects wafer optical interconnection 182, this connects wafer optical interconnection 182 along the direction vertical with semiconductor material layer 102 and electrical insulation material layer 104, vertically extends through the three-dimensional integrated semiconductor 195(of system according to the stereogram of Fig. 9).An end of perforation wafer optical interconnection 182 can extend to waveguide 116 and operationally couple with waveguide 116, and the opposite end of this perforation wafer optical interconnection 182 can operationally couple another waveguide optical device (not shown).
Although in these particular instantiations not among the illustrative figure schematically, but the various assemblies of photonic integrated circuits all are known in the art, for example, comprising: toroidal cavity resonator, Mach-Zender(MZ) interferometer, array waveguide grating (AWG) multiplexer and demodulation multiplexer, and delay line.This class component also can be included in the previous described three-dimensional integrated semiconductor of this paper system, and can be formed on the SeOI substrate 100.And this class component can utilize such as the previous described optical interconnection of this paper and couple with optical mode each other.
The previous described three-dimensional integrated semiconductor of this paper system can be set to many dissimilar optics or in the electro-optical system any.As unrestricted example, these three-dimensional integrated semiconductor systems can be set to and comprise electromagnetic radiation transmitter and/or electromagnetic radiation receiver, the electromagnetic radiation transmitter is configured to the output ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and the electromagnetic radiation receiver is configured to the output electrical signals in response to the ELECTROMAGNETIC RADIATION SIGNATURE input.Thus, in some embodiments, these three-dimensional integrated semiconductor systems can comprise the electromagnetic radiation transceiver, and this electromagnetic radiation transceiver is configured in response to signal of telecommunication input and output ELECTROMAGNETIC RADIATION SIGNATURE, and in response to the ELECTROMAGNETIC RADIATION SIGNATURE input output electrical signals.
Figure 10 is the schematic diagram that comprises the three-dimensional integrated semiconductor system 200 of electromagnetism transceiver.This transceiver comprises electromagnetic radiation transmitter 202 and electromagnetic radiation receiver 208, this electromagnetic radiation transmitter 202 is configured to the output ELECTROMAGNETIC RADIATION SIGNATURE 204 in response to signal of telecommunication input 206, and this electromagnetic radiation receiver 208 is configured to the output electrical signals 210 in response to ELECTROMAGNETIC RADIATION SIGNATURE input 212.Thus, this three-dimensional integrated semiconductor system 200 comprises: electric component, and optics and/or photoelectric subassembly, and as aforesaid three-dimensional integrated semiconductor system.The optics of three-dimensional integrated semiconductor system 200 and/or photoelectric subassembly are included in those in the frame 214 among Figure 10.Those assemblies that are in outside the frame 214 of three-dimensional integrated semiconductor system 200 are electric components.
As shown in figure 10, electromagnetic radiation transmitter 202 comprises: emitter of electromagnetic radiation 216(for example, laser), be used for monitoring by the monitoring photodetector 218 of the electromagnetic radiation of reflector 216 emissions, and be used for control reflector 216 operation drive assembly 220(for example, laser driver).Reflector 216, monitoring photodetector 218 and drive assembly 220 can have closed-loop configuration, wherein, waveguide 222 is used for carrying the electromagnetic radiation of being launched by reflector 216 to monitoring photodetector 218, at least one electric pathway 224 extends between monitoring photodetector 218 and drive assembly 220 and electric coupling monitoring photodetector 218 and drive assembly 220, to allow drive assembly 220 to receive input electrical signal (being generated by the monitoring photodetector 218) feature of the electromagnetic radiation of being launched by reflector 216, and at least one electric pathway 226 extends between drive assembly 220 and reflector 216 and electric coupling drive assembly 220 and reflector 216, to allow the operation of drive assembly 220 control reflectors 216.
Another waveguide 228 extends to electrooptic modulator 230 from reflector 216.This electrooptic modulator can be for the electromagnetic radiation of optionally modulating in response to signal of telecommunication input 206 by reflector 216 emissions.Another drive assembly 232 can be used for the operation of control electrooptic modulator 230 in response to signal of telecommunication input 206.Drive assembly 232 can comprise and can input 206 radio circuits that generate radio frequency (RF) signal according to the signal of telecommunication, and this radiofrequency signal will be by at least one electric pathway 234 to electrooptic modulator 230 inputs.
Modulated electromagnetic radiation 230 can be carried by waveguide 236, and with away from electrooptic modulator 230, this waveguide 236 couples by waveguide fiber coupler 238 and fibre-optic catheter alternatively.
Electromagnetic radiation receiver 208 comprises for the photodetector 242 that receives and detect ELECTROMAGNETIC RADIATION SIGNATURE input 212.This ELECTROMAGNETIC RADIATION SIGNATURE input 212 can be delivered to photodetector 242 by another fibre-optic catheter 244 and waveguide 246, and this another fibre-optic catheter 244 and waveguide 246 can be coupled in together by waveguide fiber coupler 248.This photodetector 242 can be configured in response to ELECTROMAGNETIC RADIATION SIGNATURE input 212 thereon impact and generate electric current.The electric current that is generated by photodetector 242 can be delivered to current/voltage converter 250 by electric pathway 252.Current/voltage converter 250 can comprise transimpedance amplifier, and this transimpedance amplifier is configured in response to being generated by photodetector 242 and inputting and the output of formation voltage signal from the electric current that this photodetector 242 receives by electric pathway 252.This signal of telecommunication output 210 can comprise the voltage signal that is generated by current/voltage converter 250.
In the previously described three-dimensional integrated semiconductor system 140,150,160,180 any can be configured to comprise the illustrative three-dimensional integrated semiconductor system 200 schematically such as Figure 10.
Below, additional unrestricted routine execution mode of the present invention is described.
Execution mode 1: a kind of three-dimensional integrated semiconductor system, this three-dimensional integrated semiconductor system comprises: semiconductor-on-insulator (SeOI) substrate, this semiconductor-on insulator-substrate comprises semiconductor material layer, and electrical insulation material layer, the first type surface of this electrical insulation material layer and described semiconductor material layer is adjacent to arrange; At least one light-sensitive device, this at least one light-sensitive device are formed on the described semiconductor material layer of SeOI substrate; With at least one optical interconnection, this at least one optical interconnection comprises the part of the described semiconductor material layer of SeOI substrate, and this at least one optical interconnection operationally is coupled to described at least one light-sensitive device; At least one current/voltage converter, this at least one current/voltage converter is formed on the semiconductor material layer of SeOI substrate; At least one electric pathway that between described at least one light-sensitive device and described at least one current/voltage converter, extends; At least one semiconductor device, this at least one semiconductor device is bonded on the SeOI substrate; And at described at least one current/voltage converter and be bonded at least one electric pathway that extends between described at least one semiconductor device on the SeOI substrate.
Execution mode 2: according to the described three-dimensional integrated semiconductor of execution mode 1 system, wherein, described at least one light-sensitive device and being bonded on the public side of described electrical insulation material layer that described at least one semiconductor device on the SeOI substrate is arranged on the SeOI substrate.
Execution mode 3: according to the described three-dimensional integrated semiconductor of execution mode 2 system, wherein, described at least one current/voltage converter is arranged on the described public side of described electrical insulation material layer of SeOI substrate.
Execution mode 4: according to the described three-dimensional integrated semiconductor of execution mode 1 system, wherein, described at least one light-sensitive device and being bonded on the opposite both sides of described electrical insulation material layer that described at least one semiconductor device on the SeOI substrate is arranged on the SeOI substrate.
Execution mode 5: according to the described three-dimensional integrated semiconductor of execution mode 4 system, wherein, described at least one light-sensitive device and described at least one current/voltage converter are arranged on the public side of described electrical insulation material layer of described SeOI substrate.
Execution mode 6: according to the described three-dimensional integrated semiconductor of in the execution mode 1 to 5 any system, wherein, described at least one light-sensitive device comprises photodetector, this photodetector be configured in response to electromagnetic radiation on described photodetector impact and generate electric current.
Execution mode 7: according to the described three-dimensional integrated semiconductor of execution mode 6 system, wherein, described at least one optical interconnection is configured to electromagnetic radiation is delivered to described photodetector.
Execution mode 8: according to the described three-dimensional integrated semiconductor of execution mode 6 system, wherein, described at least one current/voltage converter comprises transimpedance amplifier.
Execution mode 9: according to the described three-dimensional integrated semiconductor of in the execution mode 1 to 8 any system, wherein, described at least one light-sensitive device comprises optical transmitting set, and this optical transmitting set is configured to generate ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.
Execution mode 10: according to the described three-dimensional integrated semiconductor of execution mode 9 system, wherein, described at least one optical interconnection is configured to carry the electromagnetic radiation by described optical transmitting set emission.
Execution mode 11: according to the described three-dimensional integrated semiconductor of execution mode 9 or execution mode 10 system, wherein, described optical transmitting set comprises the germanium on silicon reflector.
Execution mode 12: according to the described three-dimensional integrated semiconductor of in the execution mode 1 to 11 any system, wherein, described at least one semiconductor device that is bonded on the described SeOI substrate comprises E-signal processor.
Execution mode 13: according to the described three-dimensional integrated semiconductor of execution mode 12 system, wherein, described at least one semiconductor device that is bonded on the described SeOI substrate comprises a plurality of semiconductor device that are bonded on the described SeOI substrate.
Execution mode 14: according to the described three-dimensional integrated semiconductor of execution mode 13 system, wherein, at least one semiconductor device that is bonded in the described a plurality of semiconductor device on the described SeOI substrate comprises electronic memory device.
Execution mode 15: according to the described three-dimensional integrated semiconductor of in the execution mode 1 to 11 any system, wherein, described at least one semiconductor device that is bonded on the described SeOI substrate comprises a plurality of semiconductor device that are bonded on the described SeOI substrate.
Execution mode 16: according to the described three-dimensional integrated semiconductor of execution mode 15 system, wherein, at least one semiconductor device that is bonded in the described a plurality of semiconductor device on the described SeOI substrate comprises the additional optical sensing device.
Execution mode 17: according to the described three-dimensional integrated semiconductor of execution mode 16 system, wherein, described additional optical sensing device operationally with the described semiconductor material layer that is formed on described SeOI substrate on described at least one light-sensitive device couple.
Execution mode 18: according to the described three-dimensional integrated semiconductor of execution mode 17 system, described three-dimensional integrated semiconductor system also comprises: a plurality of optical interconnections, described a plurality of optical interconnection is provided in described additional optical sensing device and is formed between described at least one light-sensitive device on the described semiconductor material layer of described SeOI substrate carries electromagnetic radiation, described a plurality of optical interconnection comprises at least one waveguide, and described at least one waveguide comprises the described part of the described semiconductor material layer of described SeOI substrate.
Execution mode 19: according to the described three-dimensional integrated semiconductor of execution mode 18 system, wherein, described a plurality of optical interconnections comprise that at least one connects wafer optical interconnection.
Execution mode 20: according to the described three-dimensional integrated semiconductor of in the execution mode 17 to 19 any system, wherein, described additional optical sensing device comprises optical transmitting set, this optical transmitting set is configured to electromagnetic radiation-emitting, and described at least one light-sensitive device that is formed on the described semiconductor material layer of described SeOI substrate comprises photodetector, and this photodetector is configured to detect the emission by the electromagnetic radiation of described optical transmitting set emission.
Execution mode 21: according to the described three-dimensional integrated semiconductor of execution mode 20 system, wherein, described optical transmitting set comprises laser device.
Execution mode 22: according to the described three-dimensional integrated semiconductor of execution mode 20 system, wherein, described optical transmitting set comprises the germanium on silicon emitter apparatus.
Execution mode 23: according to the described three-dimensional integrated semiconductor of in the execution mode 1 to 22 any system, wherein, described three-dimensional integrated semiconductor system comprises the electromagnetic radiation transmitter, and this electromagnetic radiation transmitter is configured to the output ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.
Execution mode 24: according to the described three-dimensional integrated semiconductor of in the execution mode 1 to 22 any system, wherein, described three-dimensional integrated semiconductor system comprises the electromagnetic radiation receiver, and this electromagnetic radiation receiver is configured to the output electrical signals in response to the ELECTROMAGNETIC RADIATION SIGNATURE input.
Execution mode 25: according to the described three-dimensional integrated semiconductor of execution mode 23 or execution mode 24 system, wherein, described three-dimensional integrated semiconductor system comprises the electromagnetic radiation transceiver, this electromagnetic radiation transceiver is configured to the output ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and inputs and output electrical signals in response to ELECTROMAGNETIC RADIATION SIGNATURE.
Execution mode 26: a kind of method of making three-dimensional integrated semiconductor system, the method may further comprise the steps: the semiconductor material layer at semiconductor-on-insulator (SeOI) substrate forms at least one light-sensitive device; Formation comprises at least one waveguide of a part of the described semiconductor material layer of described SeOI substrate, and operationally couples described at least one waveguide and described at least one light-sensitive device; Described semiconductor material layer at described SeOI substrate forms at least one current/voltage converter; Described at least one light-sensitive device of electric coupling and described at least one current/voltage converter; Engage at least one semiconductor device at described SeOI substrate; And described at least one current/voltage converter of electric coupling and described at least one semiconductor device that is bonded on the described SeOI substrate.
Execution mode 27: according to execution mode 26 described methods, described method is further comprising the steps of: the first side at the electrical insulation material layer of described SeOI substrate forms described at least one light-sensitive device, and engages described at least one semiconductor device in described first side of the described electrical insulation material layer of described SeOI substrate.
Execution mode 28: according to execution mode 27 described methods, during described method is further comprising the steps of at least one: described the first side at the described electrical insulation material layer of SeOI substrate forms described at least one current/voltage converter, and engages described at least one current/voltage converter in described first side of the described electrical insulation material layer of SeOI substrate.
Execution mode 29: according to execution mode 26 described methods, wherein, the step that forms described at least one light-sensitive device comprises the step that forms photodetector, this photodetector be configured in response to electromagnetic radiation on described photodetector impact and generate electric current.
Execution mode 30: according to any the described method in the execution mode 26 to 29, wherein, the step that forms described at least one current/voltage converter comprises the step that forms transimpedance amplifier.
Execution mode 31: according to any the described method in the execution mode 26 to 30, wherein, the step that forms described at least one light-sensitive device comprises the step that forms optical transmitting set, and this optical transmitting set is configured to generate ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.
Execution mode 32: according to execution mode 31 described methods, wherein, the step that forms described optical transmitting set comprises the step that forms laser device, and this laser device is configured in response to the described signal of telecommunication input electromagnetic radiation that at least emission roughly is concerned with.
Execution mode 33: according to execution mode 31 or execution mode 32 described methods, wherein, the step that forms described optical transmitting set comprises the step that forms the germanium on silicon reflector.
Execution mode 34: according to any the described method in the execution mode 26 to 33, wherein, the step that engages at least one semiconductor device at described SeOI substrate is included in the step that described SeOI substrate engages E-signal processor.
Execution mode 35: according to any the described method in the execution mode 26 to 34, wherein, the step that engages at least one semiconductor device at described SeOI substrate also is included in the step that described SeOI substrate engages electronic memory device.
Execution mode 36: according to any the described method in the execution mode 26 to 35, wherein, the step that engages at least one semiconductor device at described SeOI substrate is included in the step that described SeOI substrate engages a plurality of semiconductor device.
Execution mode 37: according to execution mode 36 described methods, the step that engages a plurality of semiconductor device at described SeOI substrate is included in the step that described SeOI substrate arranges the additional optical sensing device.
Execution mode 38: according to execution mode 37 described methods, described method is further comprising the steps of: operationally couple described additional optical sensing device and described at least one light-sensitive device that is formed on the described semiconductor material layer of described SeOI substrate.
Execution mode 39: according to execution mode 37 or execution mode 38 described methods, described method is further comprising the steps of: select described additional optical sensing device to comprise the optical transmitting set that is configured to electromagnetic radiation-emitting, and select to be formed on described at least one light-sensitive device on the described semiconductor material layer of described SeOI substrate, to comprise the photodetector that is configured to detect by the emission of the electromagnetic radiation of described optical transmitting set emission.
Execution mode 40: according to execution mode 39 described methods, described method is further comprising the steps of: select described optical transmitting set, to comprise the germanium on silicon emitter apparatus.
Execution mode 41: according to any the described method in the execution mode 26 to 40, described method is further comprising the steps of: described three-dimensional integrated semiconductor system is set, to comprise at least one in electromagnetic radiation transmitter and the electromagnetic radiation receiver, this electromagnetic radiation transmitter is configured to the output ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and this electromagnetic radiation receiver is configured to the output electrical signals in response to the ELECTROMAGNETIC RADIATION SIGNATURE input.
Above-mentioned illustrative embodiments of the present disclosure does not limit scope of the present invention, because these execution modes only are the examples of embodiments of the present invention, scope of the present invention limits according to the scope of appended claims and legal equivalents thereof.Any execution mode that is equal to all is in the scope of the present invention.In fact, except this paper shown and describe, according to specification, various modifications of the present disclosure (the as described useful combination of the alternative of element) will become obvious for a person skilled in the art.In other words, one or more feature of an illustrative embodiments described herein can be combined with one or more feature of another embodiment execution mode described herein, so that additional execution mode of the present disclosure to be provided.This modification and execution mode also are intended to fall in the scope of appended claims.

Claims (41)

1. three-dimensional integrated semiconductor system, this three-dimensional integrated semiconductor system comprises:
Semiconductor-on-insulator SeOI substrate, this SeOI substrate comprises:
Semiconductor material layer; With
Electrical insulation material layer, the first type surface of this electrical insulation material layer and described semiconductor material layer are adjacent to arrange;
At least one light-sensitive device, this at least one light-sensitive device are formed on the described semiconductor material layer of described SeOI substrate; And
At least one optical interconnection, this at least one optical interconnection comprises the part of the described semiconductor material layer of described SeOI substrate, described at least one optical interconnection operationally is coupled to described at least one light-sensitive device;
At least one current/voltage converter, this at least one current/voltage converter are formed on the described semiconductor material layer of described SeOI substrate;
At least one electric pathway that between described at least one light-sensitive device and described at least one current/voltage converter, extends;
At least one semiconductor device, this at least one semiconductor device are bonded on the described SeOI substrate; And
At described at least one current/voltage converter and be bonded at least one electric pathway that extends between described at least one semiconductor device on the described SeOI substrate.
2. three-dimensional integrated semiconductor according to claim 1 system, wherein, described at least one light-sensitive device and being bonded on the public side of described electrical insulation material layer that described at least one semiconductor device on the described SeOI substrate is arranged on described SeOI substrate.
3. three-dimensional integrated semiconductor according to claim 2 system, wherein, described at least one current/voltage converter is arranged on the described public side of described electrical insulation material layer of described SeOI substrate.
4. three-dimensional integrated semiconductor according to claim 1 system, wherein, described at least one light-sensitive device and being bonded on the opposite both sides of described electrical insulation material layer that described at least one semiconductor device on the described SeOI substrate is arranged on described SeOI substrate.
5. three-dimensional integrated semiconductor according to claim 4 system, wherein, described at least one light-sensitive device and described at least one current/voltage converter are arranged on the public side of described electrical insulation material layer of described SeOI substrate.
6. three-dimensional integrated semiconductor according to claim 1 system, wherein, described at least one light-sensitive device comprises photodetector, this photodetector be configured in response to electromagnetic radiation on described photodetector impact and generate electric current.
7. three-dimensional integrated semiconductor according to claim 6 system, wherein, described at least one optical interconnection is configured to electromagnetic radiation is delivered to described photodetector.
8. three-dimensional integrated semiconductor according to claim 6 system, wherein, described at least one current/voltage converter comprises transimpedance amplifier.
9. three-dimensional integrated semiconductor according to claim 1 system, wherein, described at least one light-sensitive device comprises optical transmitting set, this optical transmitting set is configured to generate ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.
10. three-dimensional integrated semiconductor according to claim 9 system, wherein, described at least one optical interconnection is configured to carry the electromagnetic radiation by described optical transmitting set emission.
11. three-dimensional integrated semiconductor according to claim 9 system, wherein, described optical transmitting set comprises the germanium on silicon reflector.
12. three-dimensional integrated semiconductor according to claim 1 system, wherein, described at least one semiconductor device that is bonded on the described SeOI substrate comprises E-signal processor.
13. three-dimensional integrated semiconductor according to claim 12 system, wherein, described at least one semiconductor device that is bonded on the described SeOI substrate comprises a plurality of semiconductor device that are bonded on the described SeOI substrate.
14. three-dimensional integrated semiconductor according to claim 13 system, wherein, at least one semiconductor device that is bonded in the described a plurality of semiconductor device on the described SeOI substrate comprises electronic memory device.
15. three-dimensional integrated semiconductor according to claim 1 system, wherein, described at least one semiconductor device that is bonded on the described SeOI substrate comprises a plurality of semiconductor device that are bonded on the described SeOI substrate.
16. three-dimensional integrated semiconductor according to claim 15 system, wherein, at least one semiconductor device that is bonded in the described a plurality of semiconductor device on the described SeOI substrate comprises the additional optical sensing device.
17. three-dimensional integrated semiconductor according to claim 16 system, wherein, described additional optical sensing device operationally couples with described at least one light-sensitive device on the described semiconductor material layer that is formed on described SeOI substrate.
18. three-dimensional integrated semiconductor according to claim 17 system, described three-dimensional integrated semiconductor system also comprises: a plurality of optical interconnections, described a plurality of optical interconnection is provided in described additional optical sensing device and is formed between described at least one light-sensitive device on the described semiconductor material layer of described SeOI substrate carries electromagnetic radiation, described a plurality of optical interconnection comprises at least one waveguide, and described at least one waveguide comprises the described part of the described semiconductor material layer of described SeOI substrate.
19. three-dimensional integrated semiconductor according to claim 18 system, wherein, described a plurality of optical interconnections comprise that at least one connects wafer optical interconnection.
20. three-dimensional integrated semiconductor according to claim 17 system, wherein, described additional optical sensing device comprises the optical transmitting set that is configured to electromagnetic radiation-emitting, and described at least one light-sensitive device that is formed on the described semiconductor material layer of described SeOI substrate comprises photodetector, and this photodetector is configured to detect the emission by the electromagnetic radiation of described optical transmitting set emission.
21. three-dimensional integrated semiconductor according to claim 20 system, wherein, described optical transmitting set comprises laser device.
22. three-dimensional integrated semiconductor according to claim 20 system, wherein, described optical transmitting set comprises the germanium on silicon emitter apparatus.
23. three-dimensional integrated semiconductor according to claim 1 system, wherein, described three-dimensional integrated semiconductor system comprises the electromagnetic radiation transmitter, and this electromagnetic radiation transmitter is configured to the output ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.
24. three-dimensional integrated semiconductor according to claim 1 system, wherein, described three-dimensional integrated semiconductor system comprises the electromagnetic radiation receiver, and this electromagnetic radiation receiver is configured to the output electrical signals in response to the ELECTROMAGNETIC RADIATION SIGNATURE input.
25. three-dimensional integrated semiconductor according to claim 1 system, wherein, described three-dimensional integrated semiconductor system comprises the electromagnetic radiation transceiver, this electromagnetic radiation transceiver is configured to the output ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and inputs and output electrical signals in response to ELECTROMAGNETIC RADIATION SIGNATURE.
26. a method of making three-dimensional integrated semiconductor system, the method may further comprise the steps:
Semiconductor material layer at semiconductor-on-insulator SeOI substrate forms at least one light-sensitive device;
Formation comprises at least one waveguide of a part of the described semiconductor material layer of described SeOI substrate, and operationally couples described at least one waveguide and described at least one light-sensitive device;
Described semiconductor material layer at described SeOI substrate forms at least one current/voltage converter;
Described at least one light-sensitive device of electric coupling and described at least one current/voltage converter;
Engage at least one semiconductor device at described SeOI substrate; And
Described at least one current/voltage converter of electric coupling and described at least one semiconductor device that is bonded on the described SeOI substrate.
27. method according to claim 26, described method is further comprising the steps of: the first side at the electrical insulation material layer of described SeOI substrate forms described at least one light-sensitive device, and engages described at least one semiconductor device in described first side of the described electrical insulation material layer of described SeOI substrate.
28. method according to claim 27, at least one step during described method is further comprising the steps of: described the first side at the described electrical insulation material layer of described SeOI substrate forms described at least one current/voltage converter, and engages described at least one current/voltage converter in described first side of the described electrical insulation material layer of described SeOI substrate.
29. method according to claim 26, wherein, the step that forms described at least one light-sensitive device comprises the step that forms photodetector, this photodetector be configured in response to electromagnetic radiation on described photodetector impact and generate electric current.
30. method according to claim 29, wherein, the step that forms described at least one current/voltage converter comprises the step that forms transimpedance amplifier.
31. method according to claim 26, wherein, the step that forms described at least one light-sensitive device comprises the step that forms optical transmitting set, and this optical transmitting set is configured to generate ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.
32. method according to claim 31, wherein, the step that forms described optical transmitting set comprises the step that forms laser device, and this laser device is configured to the electromagnetic radiation that emission at least roughly is concerned with in response to described signal of telecommunication input.
33. method according to claim 31, wherein, the step that forms described optical transmitting set comprises the step that forms the germanium on silicon reflector.
34. method according to claim 26, wherein, the step that engages at least one semiconductor device at described SeOI substrate is included in the step that described SeOI substrate engages E-signal processor.
35. method according to claim 34, wherein, the step that engages at least one semiconductor device at described SeOI substrate also is included in the step that described SeOI substrate engages electronic memory device.
36. method according to claim 26, wherein, the step that engages at least one semiconductor device at described SeOI substrate is included in the step that described SeOI substrate engages a plurality of semiconductor device.
37. method according to claim 36, the step that engages described a plurality of semiconductor device at described SeOI substrate is included in the step that described SeOI substrate arranges the additional optical sensing device.
38. described method according to claim 37, described method is further comprising the steps of: operationally couple described at least one light-sensitive device on described additional optical sensing device and the described semiconductor material layer that is formed on the SeOI substrate.
39. described method according to claim 38, described method is further comprising the steps of: select described additional optical sensing device to comprise the optical transmitting set that is configured to electromagnetic radiation-emitting, and select to be formed on described at least one light-sensitive device on the described semiconductor material layer of described SeOI substrate, to comprise photodetector, this photodetector is configured to detect the emission by the electromagnetic radiation of described optical transmitting set emission.
40. described method according to claim 39, described method is further comprising the steps of: select described optical transmitting set, to comprise the germanium on silicon emitter apparatus.
41. method according to claim 26, described method is further comprising the steps of: described three-dimensional integrated semiconductor system is set, to comprise at least one in electromagnetic radiation transmitter and the electromagnetic radiation receiver, this electromagnetic radiation transmitter is configured to the output ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and this electromagnetic radiation receiver is configured to the output electrical signals in response to the ELECTROMAGNETIC RADIATION SIGNATURE input.
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FR1157423A FR2979169B1 (en) 2011-08-19 2011-08-19 INTEGRATED SEMICONDUCTOR SYSTEMS IN THREE DIMENSIONS COMPRISING PHOTO-ACTIVE DEVICES

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104752341A (en) * 2013-12-31 2015-07-01 上海丽恒光微电子科技有限公司 Infrared avalanche diode array device, forming method and laser three-dimensional imaging device
CN112987174A (en) * 2019-12-13 2021-06-18 台湾积体电路制造股份有限公司 Semiconductor device and method and system for generating layout diagram thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020036330A1 (en) * 2000-09-28 2002-03-28 Nec Corporation Semiconductor device with SOI structure and method of manufacturing the same
US20070020871A1 (en) * 2005-07-06 2007-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional IC device and alignment methods of IC device substrates
CN101128761A (en) * 2005-02-04 2008-02-20 斯欧普迪克尔股份有限公司 Vertical stacking of multiple integrated circuits including SOI-based optical components
CN101395480A (en) * 2006-01-27 2009-03-25 斯欧普迪克尔股份有限公司 Lidar system utilizing soi-based opto-electronic compounds

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020036330A1 (en) * 2000-09-28 2002-03-28 Nec Corporation Semiconductor device with SOI structure and method of manufacturing the same
CN101128761A (en) * 2005-02-04 2008-02-20 斯欧普迪克尔股份有限公司 Vertical stacking of multiple integrated circuits including SOI-based optical components
US20070020871A1 (en) * 2005-07-06 2007-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional IC device and alignment methods of IC device substrates
CN101395480A (en) * 2006-01-27 2009-03-25 斯欧普迪克尔股份有限公司 Lidar system utilizing soi-based opto-electronic compounds

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104752341A (en) * 2013-12-31 2015-07-01 上海丽恒光微电子科技有限公司 Infrared avalanche diode array device, forming method and laser three-dimensional imaging device
CN104752341B (en) * 2013-12-31 2018-01-30 上海丽恒光微电子科技有限公司 Infrared avalanche photodiode arrays device and forming method, laser three-dimensional imaging device
CN112987174A (en) * 2019-12-13 2021-06-18 台湾积体电路制造股份有限公司 Semiconductor device and method and system for generating layout diagram thereof
CN112987174B (en) * 2019-12-13 2023-05-05 台湾积体电路制造股份有限公司 Semiconductor device and method and system for generating layout thereof

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