CN102955760A - Base-2 parallel FFT (fast Fourier transformation) processor based on DIF (decimation in frequency) and processing method thereof - Google Patents

Abstract

The invention discloses a base-2 parallel FFT (fast Fourier transformation) processor based on DIF (decimation in frequency) and a processing method thereof. The processor comprises a parallel FFT input arithmetic unit, a twiddle factor module and an FFT processor. The parallel FFT input arithmetic unit comprises 2M parallel adder--subtractors and delay units for achieving time synchronization, wherein M is a nonnegative integer. The FFT processor comprises 2M parallel FFTIP (fast Fourier transform intellectual property) cores. The 2M parallel adder-subtractors are in one-to-one correspondence connection with the 2M parallel FFTIP cores. An output sequence of each adder-subtractor multiplies a corresponding twiddle factor in the twiddle factor module and is input to one FFTIP core in one-to-one correspondence connection with the adder-subtractor. The delay units are disposed at input ends or/and output ends of the adder-subtractors in the FFT input arithmetic unit. The base-2 parallel FFT processor based on DIF splits long sequences into short sequences, FFT of the short sequences is achieved by the FFTIP cores, and accordingly processing speed and system throughput are increased linearly.

Description

Base-2 parallel FFT processor and disposal route thereof based on DIF

Technical field

The invention belongs to the Signal and Information Processing technical field, relate to a kind of fft processor, relate in particular to a kind of base based on DIF-2 parallel FFT processor and disposal route thereof.

Background technology

FFT has a very wide range of applications in digital processing field, but long sequence FFT operand is very large, realizes relatively difficulty.Along with the development of high speed device, about how realizing fast that the research of long sequence FFT this respect is a lot, various implementation methods also occur in succession.For example consist of parallel organization with the long sequence FFT of quick realization with a plurality of special chips, but this method is based on special chip, dirigibility is not enough.In recent years FPGA device development is rapid, and its reconstruction property able to programme is so that it has obtained more and more widely application in a lot of fields.The Virtex-II of Xilinx company Series FPGA is inner integrated a large amount of special multiplier (Block Multiplier), a large amount of block RAM (Block RAM) and abundant logic gate resource, this is so that it is fit to realize the design of a large amount of multipliers of this needs of FFT, a large amount of block RAM and register very much.Fft algorithm has two kinds in theory, be decimation in time method DIT (Decimation-In-Time) and decimation in frequency method (Decimation-In-Freqency), two kinds of algorithms do not have difference in essence, the order that is plural plus-minus method and twiddle factor multiplication is had any different, and the operand of two kinds of methods is the same.But on implementation, both butterfly computation structures are different.For processing speed and the throughput of system (Throughput) that improves long sequence FFT, analysis of the present invention has also designed a kind of parallel FFT that FPGA realizes that is suitable for based on the DIF method.

Summary of the invention

Technical matters to be solved by this invention is: a kind of base based on DIF-2 parallel FFT processor is provided, and this parallel FFT processor can linearly improve processing speed;

In addition, the present invention also provides the disposal route of a kind of base based on DIF-2 parallel FFT processors, and the method also can linearly improve processing speed.

For solving the problems of the technologies described above, the present invention adopts following technical scheme.

A kind of base based on DIF-2 parallel FFT processor comprises parallel FFT input arithmetical unit, twiddle factor module and fft processor; Described parallel FFT input arithmetical unit comprises 2 ^MThe adder-subtractor that the road is parallel and in order to realize the delay unit of timing synchronization, wherein M is nonnegative integer; Described fft processor comprises 2 ^MThe FFT IP kernel that the road is parallel; 2 ^MThe adder-subtractor and 2 that the road is parallel ^MCorrespondence is continuous one by one for the parallel FFT IP kernel in road; The output sequence of each road adder-subtractor and corresponding twiddle factor in the twiddle factor module rear road FFT IP kernel that link to each other corresponding to self that all input to that multiply each other; Described delay unit is arranged on the input end of the adder-subtractor in the parallel FFT input arithmetical unit or/and output terminal.

As a preferred embodiment of the present invention, the list entries of described base based on DIF-2 parallel FFT processor is long to be K2 ^M, wherein K is positive integer, the length of the handled sequence of described FFT IP kernel is K.

As another kind of preferred version of the present invention, store the twiddle factor look-up table in the described twiddle factor module.

The disposal route of a kind of base based on DIF-2 parallel FFT processors may further comprise the steps:

Step 1 is K2 with length ^MThe sequence x (n) of point is equally divided into 2 ^MThe group sequence, i.e. x (n), x (n+K), x (n+2K) ..., (n+ (2 for x ^M-1) K), wherein K is positive integer, and M is nonnegative integer;

Step 2 is with described 2 ^MThe group sequence is input in the parallel FFT input arithmetical unit synchronously, and described parallel FFT input arithmetical unit comprises 2 ^MThe adder-subtractor that the road is parallel;

Step 3, will by parallel FFT input that arithmetical unit calculates 2 ^MGroup plus-minus result multiply by the twiddle factor of the correspondence of storing in the twiddle factor module, obtains 2 ^MThe group result of product;

Step 4 is with described 2 ^MIt is that the FFT IP kernel of K carries out FFT and processes that the group result of product is input to respectively length, obtains the FFT result that length is K; 2 ^MThe FFT result on road joins end to end, and namely obtains the FFT result of list entries.

As a preferred embodiment of the present invention, the list entries of described base based on DIF-2 parallel FFT processor is long to be K2 ^M, wherein K is positive integer, the length of the handled sequence of described FFT IP kernel is K.

As another kind of preferred version of the present invention, store the twiddle factor look-up table in the described twiddle factor module.

As another preferred version of the present invention, the input end of the adder-subtractor in the described parallel FFT input arithmetical unit is or/and output terminal is provided with to realize the delay unit of timing synchronization.

Beneficial effect of the present invention is: the base based on DIF of the present invention-2 parallel FFT processor will be grown sequence and split into short sequence, and by the FFT of the short sequence of a plurality of fft processor Parallel Implementation, thereby linearity has improved processing speed and throughput of system.

Description of drawings

Fig. 1 is the structural representation of the base based on DIF of the present invention-2 parallel FFT processors;

Fig. 2 is the structural representation of embodiment two described base based on DIF-2 parallel FFT processors;

Fig. 3 is the N=16 point FFT operational flowchart of the decimation in frequency method (DIF) of a standard.

The primary clustering symbol description:

1, parallel FFT input arithmetical unit; 2, twiddle factor module;

3, fft processor; 11, adder-subtractor;

12, delay unit; 31, FFT IP kernel.

Embodiment

Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.

Embodiment one

The present embodiment provides a kind of base based on DIF-2 parallel FFT processor, as shown in Figure 1, comprises parallel FFT input arithmetical unit 1, twiddle factor module 2 and fft processor 3; Described parallel FFT input arithmetical unit 1 comprises 2 ^MAdder-subtractor 11 and delay unit 12 that the road is parallel, wherein M is nonnegative integer; Described FFT IP kernel 3 comprises 2 ^MThe FFT IP kernel 31 that the road is parallel; 2 ^MThe adder- subtractor 11 and 2 that the road is parallel ^MCorrespondence is continuous one by one for the parallel FFT IP kernel 31 in road; The output sequence of each road adder-subtractor 11 and corresponding twiddle factor in the twiddle factor module 2 rear road FFT IP kernel 31 that link to each other corresponding to self that all input to that multiply each other.

The list entries of described base based on DIF-2 parallel FFT processor is long to be K2 ^M, wherein K is positive integer, the length that described FFTIP examines 31 handled sequences is K.Store the twiddle factor look-up table in the described twiddle factor module 2.The input end of the adder-subtractor 11 in the described parallel FFT input arithmetical unit 1 is or/and output terminal is provided with to realize the delay unit 12 of timing synchronization.

The disposal route of described base based on DIF-2 parallel FFT processors is:

Step 1 is K2 with length ^MThe sequence x (n) of point is equally divided into 2 ^MThe group sequence, i.e. x (n), x (n+K), x (n+2K) ..., (n+ (2 for x ^M-1) K), wherein K is positive integer, and M is nonnegative integer;

Step 2 is with described 2 ^MThe group sequence is input in the parallel FFT input arithmetical unit synchronously, and described parallel FFT input arithmetical unit comprises 2 ^MThe adder-subtractor that the road is parallel;

Step 3, will by parallel FFT input that arithmetical unit calculates 2 ^MGroup plus-minus result multiply by the twiddle factor of the correspondence of storing in the twiddle factor module, obtains 2 ^MThe group result of product;

Step 4 is with described 2 ^MIt is that the FFT IP kernel of K carries out FFT and processes that the group result of product is input to respectively length, obtains the FFT result that length is K, 2 ^MThe FFT result on road joins end to end, and namely obtains the FFT result of list entries.Wherein fft processor comprises 2 ^MThe FFT IP kernel that the road is parallel, every road FFT IP kernel is processed one group of result of product.

Embodiment two

The present embodiment provides a kind of base based on DIF-2 parallel FFT processor, and as shown in Figure 2, the difference of itself and embodiment one is: parallel FFT input arithmetical unit comprises 4 tunnel parallel adder-subtractors, and fft processor comprises 4 tunnel parallel FFT IP kernels; Be N based on the list entries of the base-2 parallel FFT processor of DIF is long.

Fig. 3 has shown the N=16 point FFT operational flowchart of the decimation in frequency method (DIF) of a standard, wherein the data flow after the two-stage of front is divided into four separate units (as shown in phantom in Figure 3) significantly on level, each unit is realized the FFT that N/4 is ordered independently, thereby consists of one four tunnel parallel structure.Therefore, the FFT that can come parallel computation N to order with the FFT unit that four N/4 are ordered, the i.e. FFT of so-called parallel organization.Then design the computing circuit of an ad hoc structure and process initial two-stage.

The below is described in detail the design process of the described base based on DIF of the present embodiment-2 parallel FFT processors:

Designing a key that is suitable for the parallel DIF mode fft processor of FPGA realization is the computing circuit of the above-mentioned ad hoc structure of design, and the FFT Unit Design of standard will here not set forth, and the present invention adopts special-purpose FFT IP kernel to realize that the FFT of short sequence (length is N/4) processes.

Be the sequence x (n) of N for length, establishing its corresponding FFT result is N point sequence X (w), has so

$X\left(w\right)=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}x\left(n\right)W_N^{\mathrm{wn}}---\left(1\right)$

Wherein, W _N=e ^{-j2 π/N}Be so-called twiddle factor (twiddle-factor).

For the ease of understanding, by Cooley-Tukey algorithm output sequence X (k) is split into two groups of odd evens by k, namely

$X\left(k\right)=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}x\left(n\right)W_N^{\mathrm{kn}}=\underset{n=0}{\overset{N/2-1}{\mathrm{\Σ}}}x\left(n\right)W_N^{\mathrm{kn}}+\underset{n=N/2}{\overset{N-1}{\mathrm{\Σ}}}x\left(n\right)W_N^{\mathrm{kn}}$

$=\underset{n=0}{\overset{N/2-1}{\mathrm{\Σ}}}x\left(n\right)W_N^{\mathrm{kn}}+\underset{n=0}{\overset{N/2-1}{\mathrm{\Σ}}}x(n+N/2)W_N^{k(n+N/2)}$

$=\underset{n=0}{\overset{N/2-1}{\mathrm{\Σ}}}x\left(n\right)W_N^{\mathrm{kn}}+\underset{n=0}{\overset{N/2-1}{\mathrm{\Σ}}}{(-1)}^{k}x(n+N/2)W_N^{\mathrm{kn}}---\left(2\right)$

In the formula (2), $W_N^{\mathrm{kN}/2}=e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HDA0000085460370000011.png,HDA0000085460370000021.png"\; state="\{\{state\}\}">j</figure-callout>}\frac{2\mathrm{\&pi;}}{N}\frac{N}{2}k}=e^{-\mathrm{jk\&pi;}}={(-1)}^k,$ So have

$X\left(k\right)=\underset{n=0}{\overset{N/2-1}{\mathrm{\&Sigma;}}}[x\left(n\right)+{(-1)}^{k}x(n+N/2)]W_N^{\mathrm{kn}},k=\mathrm{0,1},.....N-1---\left(3\right)$

Equally, can be subdivided into 4 groups to k, namely

$X\left(k\right)=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x\left(n\right)W_N^{\mathrm{kn}}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+N/4)W_N^{k(n+N/4)}$

$\left(4\right)$

$+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+2N/4)W_N^{k(n+2N/4)}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+3N/4)W_N^{k(n+3N/4)}$

So we represent k with r, namely divide k=4r, 4r+1,4r+2, four kinds of situations of 4r+3, formula (4) can be decomposed into following several formula so:

$X\left(4r\right)=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x\left(n\right)W_N^{4\mathrm{rn}}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+N/4)W_N^{\left(4r\right)(n+N/4)}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+2N/4)W_N^{\left(4r\right)(n+2N/4)}$

$+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+3N/4)W_N^{\left(4r\right)(n+3N/4)}---\left(5\right)$

$=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}[x\left(n\right)+x(n+N/4)+x(n+2N/4)+x(n+3N/4)]W_N^0{W}_{N/4}^{\mathrm{rn}}$

$=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}{x}_{11}\left(n\right)W_N^0{W}_{N/4}^{\mathrm{rn}}$

Wherein, x ₁₁(n)=x (n)+x (n+N/4)+x (n+2N/4)+x (n+3N/4).

$X(4r+1)=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x\left(n\right)W_N^{(4r+1)n}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+N/4)W_N^{(4r+1)(n+N/4)}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+2N/4)W_N^{(4r+1)(n+2N/4)}$

$+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+3N/4)W_N^{(4r+1)(n+3N/4)}---\left(6\right)$

$=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}[x\left(n\right)-j*x(n+N/4)-x(n+2N/4)+j*x(n+3N/4)]W_N^n{W}_{N/4}^{\mathrm{rn}}$

$=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}{x}_{12}\left(n\right)W_N^n{W}_{N/4}^{\mathrm{rn}}$

Wherein, x ₁₂(n)=x (n)-j*x (n+N/4)-x (n+2N/4)+j*x (n+3N/4).

$X(4r+2)=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x\left(n\right)W_N^{(4r+2)n}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+N/4)W_N^{(4r+2)(n+N/4)}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+2N/4)W_N^{(4r+2)(n+2N/4)}$

$+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+3N/4)W_N^{(4r+2)(n+3N/4)}---\left(7\right)$

$=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}[x\left(n\right)-x(n+N/4)+x(n+2N/4)-x(n+3N/4)]{\mathrm{<figure-callout\; id="2n"\; label="W\; N"\; filenames="HDA0000085460370000021.png"\; state="\{\{state\}\}">W</figure-callout>}}_N^{}{W}_{N/4}^{\mathrm{rn}}$

$=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}{x}_{21}\left(n\right){\mathrm{<figure-callout\; id="2n"\; label="W\; N"\; filenames="HDA0000085460370000021.png"\; state="\{\{state\}\}">W</figure-callout>}}_N^{}{W}_{N/4}^{\mathrm{rn}}$

Wherein, x ₂₁(n)=x (n)-x (n+N/4)+x (n+2N/4)-x (n+3N/4).

$X(4r+3)=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x\left(n\right)W_N^{(4r+3)n}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+N/4)W_N^{(4r+3)(n+N/4)}+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+2N/4)W_N^{(4r+3)(n+2N/4)}$

$+\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}x(n+3N/4)W_N^{(4r+3)(n+3N/4)}---\left(8\right)$

$=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}[x\left(n\right)+j*x(n+N/4)+x(n+2N/4)-j*x(n+3N/4)]{\mathrm{<figure-callout\; id="3n"\; label="W\; N"\; filenames="HDA0000085460370000021.png"\; state="\{\{state\}\}">W</figure-callout>}}_N^{}{W}_{N/4}^{\mathrm{rn}}$

$=\underset{n=0}{\overset{N/4-1}{\mathrm{\&Sigma;}}}{x}_{22}\left(n\right){\mathrm{<figure-callout\; id="3n"\; label="W\; N"\; filenames="HDA0000085460370000021.png"\; state="\{\{state\}\}">W</figure-callout>}}_N^{}{W}_{N/4}^{\mathrm{rn}}$

Wherein, x ₁₂(n)=x (n)+j*x (n+N/4)+x (n+2N/4)-j*x (n+3N/4).

From above-mentioned formula (5～8) as can be known, length is that the FFT of the sequence of N can realize by the FFT IP kernel that a special operating structure and 4 length are N/4, thereby reaches the purpose that parallel processing improves arithmetic speed.Above-mentioned implementation method adopts FPGA to realize, needs 4 tunnel special concurrent operation construction modules of design and uses the FFT IP kernel.Parallel FFT is realized principle as shown in Figure 2.

Mainly inputting special arithmetical unit (U0), twiddle factor table (U9) and fft processor by parallel FFT based on the base-2 parallel FFT processor of DIF forms.Wherein,

U0: parallel FFT is inputted special arithmetical unit, and it has realized the calculating of formula (5～8), mainly by adder-subtractor, and multiplier, delay unit forms;

U1～U4: adder-subtractor, it has realized the signed magnitude arithmetic(al) of formula (5～8);

D2, D4: delay unit, realize on the sequential synchronously;

U5～U8: length is the FFT IP kernel of N/4;

U9: the twiddle factor table, namely in the formula (5～8)

Look-up table.

Length is that the value X (w) of the FFT of the N sequence x (n) of ordering can be the sequence x that N/4 is ordered by length like this ₁₁(n), x ₁₂(n), x ₂₁(n) and x ₂₂(n) through type (5～8) calculates, and concrete calculation procedure is as follows:

Step 1 is length that the sequence that N is ordered is divided into x (n), x (n+N/4), x (n+2N/4), four groups of x (n+3N/4);

Step 2 is input to U0 shown in Figure 2 (parallel FFT is inputted special arithmetical unit) synchronously to above-mentioned four groups of sequences;

It is that the FFT IP kernel module of N/4 is carried out FFT and processed and just obtain the FFT result that length is the sequence of N that step 3,4 groups of results that calculate by U0 are input to respectively length.

The present invention can also continue by the method for embodiment two N point sequence five equilibrium is gone down to increase parallel way, and the way that certainly increases also can increase the consumption of hardware resource in the time of more, and the computing circuit of ad hoc structure also becomes more complicated.

But the present invention derives the FFT formula of Parallel Implementation in detail from the discrete Fourier transformation formula, designed the fft processor of the parallel organization that is suitable for the FPGA realization, sort processor splits into several shorter sequences to long sequence, then the parallel FFT that is with sending into several processing unit for parallel that realize short sequence FFT, 4 tunnel FFT result is joined end to end, namely obtain the FFT result of list entries.

Embodiment three

The present embodiment is by in the situation that single channel, two-way and four tunnel parallel, from the function contrast of fft processor at the resource that consumes (Resources), the aspects such as clock frequency (Maximum Speed), stand-by period (Latency), conversion time (TransformTime) and throughput of system (Throughput) that can reach, further prove parallel FFT processor that the present invention proposes and the beneficial effect of disposal route thereof.

Base based on DIF of the present invention-2 parallel FFT processor is obtaining checking with Virtex-II sequence FPGA XC2V3000 brassboard DASQ_USB_V1.Length is that 2048 real sequence splits into four tunnel input FPGA, and what four parallel FFT unit adopted is the free FFT IP kernel that Xilinx FPGA developing instrument ISE10.1 carries, and it can realize the flowing water input and output.The FFT the result that list entries length is N=2048 is as shown in table 1, and the inputoutput data in the table is expressed as fixed-point number, and word length is 16.

Table 1: the performance that realizes the fixed point FFT of N=2048 sequence at XC2V3000-6

Here handling capacity is expressed as: handling capacity (Throughput)=clock frequency * parallel way.

Table 1 has enumerated respectively in the situation that single channel, two-way and four tunnel parallel, the resource that fft processor consumes (Resources), the clock frequency (Maximum Speed) that can reach, stand-by period (Latency), conversion time (Transform Time) and throughput of system (Throughput).As seen from Table 1,2 tunnel used Slices resources when parallel increase less than 1 times than single channel, but processing speed and handling capacity can improve 1 times; And 4 tunnel used Slices resources when parallel increase about 3 times than single channel, but conversion time only has 1/4th of single channel, and throughput of system then reaches 4 times of single channel.If this has illustrated that resource enough just can constantly increase parallel way to obtain faster processing speed and larger handling capacity.

Experimental result shows, parallel FFT processor of the present invention can linearly improve processing speed and throughput of system.Because resource is limit, the present invention has only verified that two-way walks abreast and four tunnel parallel situations, if when in fact the processing speed requirement is higher, can also increase parallel way, system is expanded.

Description of the invention and application are illustrative, are not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment and change is possible, and the various parts of the replacement of embodiment and equivalence are known for those those of ordinary skill in the art.Those skilled in the art are noted that in the situation that do not break away from spirit of the present invention or essential characteristic, and the present invention can be with other forms, structure, layout, ratio, and realize with other elements, material and parts.

Claims (7)

1. the base based on DIF-2 a parallel FFT processor is characterized in that: comprise parallel FFT input arithmetical unit, twiddle factor module and fft processor; Described parallel FFT input arithmetical unit comprises 2 ^MThe adder-subtractor that the road is parallel and in order to realize the delay unit of timing synchronization, wherein M is nonnegative integer; Described fft processor comprises 2 ^MThe FFT IP kernel that the road is parallel; 2 ^MThe adder-subtractor and 2 that the road is parallel ^MCorrespondence is continuous one by one for the parallel FFT IP kernel in road; The output sequence of each road adder-subtractor and corresponding twiddle factor in the twiddle factor module rear road FFT IP kernel that link to each other corresponding to self that all input to that multiply each other; Described delay unit is arranged on the input end of the adder-subtractor in the parallel FFT input arithmetical unit or/and output terminal.

2. the base based on DIF according to claim 1-2 parallel FFT processor is characterized in that: the long K2 of being of the list entries of described base based on DIF-2 parallel FFT processor ^M, wherein K is positive integer, the length of the handled sequence of described FFT IP kernel is K.

3. the base based on DIF according to claim 1-2 parallel FFT processor is characterized in that: store the twiddle factor look-up table in the described twiddle factor module.

4. the disposal route of the base based on DIF claimed in claim 1-2 parallel FFT processors is characterized in that, may further comprise the steps:

Step 1 is K2 with length ^MThe sequence x (n) of point is equally divided into 2 ^MThe group sequence, i.e. x (n), x (n+K), x (n+2K) ..., (n+ (2 for x ^M-1) K), wherein K is positive integer, and M is nonnegative integer;

Step 2 is with described 2 ^MThe group sequence is input in the parallel FFT input arithmetical unit synchronously, and described parallel FFT input arithmetical unit comprises 2 ^MThe adder-subtractor that the road is parallel;

Step 3, will by parallel FFT input that arithmetical unit calculates 2 ^MGroup plus-minus result multiply by the twiddle factor of the correspondence of storing in the twiddle factor module, obtains 2 ^MThe group result of product;

Step 4 is with described 2 ^MIt is that the FFT IP kernel of K carries out FFT and processes that the group result of product is input to respectively length, obtains the FFT result that length is K; 2 ^MThe FFT result on road joins end to end, and namely obtains the FFT result of list entries.

5. the disposal route of the base based on DIF according to claim 4-2 parallel FFT processors is characterized in that: the long K2 of being of the list entries of described base based on DIF-2 parallel FFT processor ^M, wherein K is positive integer, the length of the handled sequence of described FFT IP kernel is K.

6. the disposal route of the base based on DIF according to claim 4-2 parallel FFT processors is characterized in that: store the twiddle factor look-up table in the described twiddle factor module.

7. the disposal route of the base based on DIF according to claim 4-2 parallel FFT processors is characterized in that: the input end of the adder-subtractor in the described parallel FFT input arithmetical unit is or/and output terminal is provided with to realize the delay unit of timing synchronization.

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