CN102944803B - Leakage power estimation - Google Patents

Abstract

The invention provides a method and equipment for leakage power estimation. In an embodiment, one or more detected temperature values (108) and one or more voltage values (110) are used for determining leakage powder of one part of an integrated circuit (IC). Other embodiments are also described.

Description

Leakage power is estimated

The divisional application that the application is the applying date is on June 30th, 2006, application number is 200680054765.7, denomination of invention is the Chinese invention patent application of " leakage power estimation ".

Background technology

The present invention generally relates to electronic applications, and more particularly, the leakage power that embodiments of the invention relate in integrated circuit (IC) device is estimated.

Technical field

No matter being dynamic power consumption or leakage power, is all one of principal concern in IC design.Particularly, subthreshold leaks (or leakage power) may increase along with each design phase in succession.For example, when reducing supply voltage (such as, in order to reduce dynamic power consumption), threshold voltage also can be lowered (such as, object is to maintain low gate delay or high frequency).But reducing threshold voltage may affect leakage power in a non-linear manner.

In certain embodiments, can suppose that leakage power operationally equals constant.But leakage power also may operationally change, such as, change with the change of temperature, supply voltage or threshold voltage.So do not know leakage power, power management techniques just may be not too accurate.

Accompanying drawing explanation

Describe in detail and carry out with reference to accompanying drawing.In the drawings, the figure number that in reference number, this reference number of numeral of high order end occurs for the first time.In different drawings, adopt identical reference number representation class like or identical entry.

Fig. 1, Fig. 5 and Fig. 6 represent the block scheme of the computing system according to each embodiment of the present invention.

Fig. 2 A and Fig. 2 B represents the block scheme of each several part of the leakage power estimating system according to each embodiment.

Fig. 3 represents the block scheme of the processor core according to embodiment.

Fig. 4 represents the process flow diagram of the method according to embodiment.

Embodiment

In the following description, many specific detail are given so that the various embodiment of thorough understanding.But each embodiment of the present invention can not adopt these specific detail to implement.In other circumstances, also do not illustrate in detail well-known method, process, parts and circuit, the object done like this is in order to outstanding specific embodiment of the present invention.The various aspects of all embodiments of the present invention can adopt different means to realize, such as, adopt integrated semiconductor circuit (" hardware "), form the combination of the computer-readable instruction (" software ") of one or more program or hardware and software.With regard to this instructions, mention " logic " and just refer to hardware, software or their combination.

Some embodiments discussed herein can provide effective technology to estimate leakage power (static state such as produced by one or more parts of IC device or subthreshold leakage power).In an embodiment, this leakage power may be caused by one or more changes, such as, change in temperature and/or voltage (as threshold value and/or supply voltage).And embodiments more discussed in this article can be applied to various computing system, such as, with reference to the computing system that Fig. 1, Fig. 5 and Fig. 6 discuss.More particularly, Fig. 1 is the block scheme of the computing system 100 according to embodiment.System 100 can comprise one or more territory 102 – 1 to 102 – M(and its entirety is commonly referred to as in " territory 102 " herein).Each territory in – 1 to the 102-M of territory 102 can comprise various parts, but for clarity sake, only depicts exemplary components to territory 102 – 1 and territory 102 – 2.And each territory 102 can correspond to a part (such as with reference to the parts that Fig. 5 and Fig. 6 discusses, or more generally saying, one or more transistors of IC device) for computing system.In an embodiment, each territory in territory 102 can comprise the different circuit (or logic) by clock signal timing, and this clock signal can be different from the clock signal used in other territories.In one embodiment, the one or more signals in these clock signals can be mesochronous, or according to (such as there is the relation self repeating in time or self do not repeat in time) that other modes are correlated with.

As shown in Figure 1, data communication can be carried out by one or more impact dampers 104 and other territories in each territory.In one embodiment, impact damper 104 can be first-in first-out (FIFO) impact damper.Each territory can comprise the logic of the leakage power for estimating one or more parts in corresponding field (such as respectively with reference to logical one 06 – 1 and 106 – 2 shown by territory 102 – 1 and 102 – 2, be commonly referred to as herein " logical one 06 "), one or more temperature sensor (such as respectively with reference to sensor 108 – 1 and 108 – 2 shown by territory 102 – 1 and 102 – 2), controlled frequency and/or voltage level and/or the logic (such as respectively with reference to logical one 10 – 1 and 110 – 2 shown by territory 102 – 1 and 102 – 2) of current threshold voltage and/or voltage value is provided, and the logic of one or more parts power consumptions in management corresponding field is (such as respectively with reference to logical one 12 – 1 and 112 – 2 shown by territory 102 – 1 and 102 – 2, be commonly referred to as herein " logical one 12 ").In an embodiment, the threshold voltage of transistor can by applying electric current to regulate to transistor body (substrate).

In various embodiments, Power management logic 112 can regulate the power consumption of one or more parts of corresponding field.For example, logical one 12 can utilize some information to regulate supply voltage and/or the threshold voltage of one or more parts of corresponding field, and these information can be leakage power estimated values (value such as provided by respective logic 106), dynamic power is estimated and/or some other information (instruction, cache misses etc. that such as each circulation is born).And logical one 12 can regulate the frequency of clock signal (the interior at least partially clock signal used of such as corresponding field).In an embodiment, logical one 12 can turn off one or more parts: some part (such as different streamlines etc.) of such as one or more processor core or these processor cores and/or data cache (such as, can various levels of cache be comprised, as the first order (L1), the second level (L2) or other levels) or some part (such as different cache clusters) of data cache.

Fig. 2 A and Fig. 2 B represents the block scheme according to the leakage power estimating system 200 of each embodiment and the ingredient of system 250.In one embodiment, the logical one 06 of system 200 and system 250 and reference Fig. 1 discussion is same or similar.In an embodiment, the storage unit discussed with reference to Fig. 2 A and Fig. 2 B can be same or similar with the memory member discussed with reference to Fig. 5 and/or Fig. 6.

As shown in Figure 2 A and 2 B, system 200 and system 250 can comprise temperature calibration factor storage unit 202(such as, are used for storing multiple temperature calibration factor values).Storage unit 202 can accept from one or more parts (such as with reference to those parts that Fig. 1, Fig. 5 and Fig. 6 discuss) corresponding sensor 108 temperature value that detects.System 200 can also comprise voltage calibration factor storage unit 204(such as, is used for storing multiple voltage factor value) and with reference to leaking storage unit 206(such as, be used for stored reference or benchmark leakage power value).The benchmark leakage value stored in storage unit 206 can be determined when designing (such as being determined by emulation or circuit measuring), or is determined when testing.For example, to the design with higher variability, benchmark leakage value (this is because to each chip and/or functional block, this reference value can carry out separately calculating to adapt to the estimation to each circuit details) can be determined when testing.

In an embodiment, system 200 can also comprise the logic 210 that rounds off, and is used for rounding up (such as making detected value round off becomes the immediate value of value stored with storage unit 202) to the temperature value received from sensor 108.The value interpolation that interpolating logic 212 can export storage unit 202 becomes the actual temperature measured value that sensor 108 provides.Similarly, system 200 can comprise voltage and round off logic 214(such as, being used for rounds off to present threshold value and/or voltage value becomes and the immediate value of value that storage unit 204 stores) and voltage interpolating logic 218(is such as, being used for becomes to the value interpolation that storage unit 204 exports the actual voltage value that steering logic 110 provides).Multiplier 208 by the determined temperature calibration factor (such as searching from storage unit 202 according to the detected temperatures of sensor 108), determined voltage calibration factor (current voltage value such as provided according to logical one 10 is searched from storage unit 204) and can be multiplied with reference to leakage value (from storage unit 206).Then, this product value just can be used to managing power setting value (such as being managed by Power management logic 112) as discussed in Figure 1 like that.

Referring now to Fig. 2 B.System 250 can comprise with reference to leaking storage unit 252, is corresponding one group of store voltages benchmark leakage value.Correspondingly, in one embodiment, single storage unit (252) can store multiple value, and these values are corresponding with the combination that the analog value stored in the voltage calibration factor storage unit 204 of value and Fig. 2 A stored in storage unit 206 is leaked in the reference of Fig. 2 A.For example, multiple leakage power value can be indexed according to temperature factor (such as, being provided by sensor 108) and voltage factor (such as, corresponding with the threshold voltage value that logical one 10 provides and/or voltage value).Such embodiment can pass through single look-up (such as, searching according to from the present threshold value of logical one 10 and/or voltage value) provides the reference leakage value can being undertaken by the temperature calibration factor of searching (the detected temperatures value such as provided according to sensor 108 is searched) via multiplier 254 from storage unit 202 demarcating.Another kind method is, the value stored in storage unit 202,204,206 and/or 252 can be incorporated into single storage unit (not shown), to allow single look-up to provide with the temperature value of the detection that sensor 108 provides and/or from the present threshold value of logical one 10 and/or the corresponding leakage value of voltage value.And, system 250 can comprise according to some embodiments round off and/or interpolating logic (such as, can with logic 210,212,214 and/or 218 same or similar).

Fig. 3 represents the block scheme of the processor core 300 according to embodiment.In one embodiment, core 300 can represent the various parts (such as with reference to those parts that Fig. 5 and Fig. 6 discusses) that may exist in processor or some processors.Processor core 300 can comprise one or more territory, such as second level cache domains 302, head end domain 304 and one or more back-end domain 306.Parts in each territory in territory 302,304 and 306 can carry out timing by the different clocks signal with reference to Fig. 1 discussion.And in different embodiments, the parts included by each territory (such as 302,304 and 306) can greater or less than the parts shown in Fig. 3.

The second level (L2) cache domains 302 can comprise L2 high-speed cache 308(and such as can be used to store the data comprising instruction), sensor 108 and logical one 06,110 and 112.In one embodiment, L2 high-speed cache 308 can be shared by the multiple cores in the polycaryon processor with reference to figure 5 and Fig. 6 discussion.And, L2 high-speed cache 308 perhaps with these processor cores from same tube core.So in various embodiments of the present invention, processor can comprise territory 304 and 306, and processor can comprise L2 high-speed cache 308, also can not comprise.

As shown in Figure 3, head end domain 304 can comprise sensor 108, logical one 06,110 and 112, rearrangement buffer 318, renames and guide unit 320, instruction cache 322, decoding unit 324, sequencer 326, and/or one or more in inch prediction unit 328.In one embodiment, head end domain 304 can comprise miscellaneous part, such as instruction fetch unit.

It is one or more that back-end domain 306 can comprise in the first order (L1) cache domains 328 and one or more execution domains 330 – 1 to 330-N.L1 cache domains 328 can comprise L1 high-speed cache 332(such as, is used for storing the data comprising instruction), sensor 108, and logical one 06,110 and 112.And execution domains 330-1 to 330-N can comprise one or more Integer Execution Units and/or performance element of floating point.Each territory in execution domains 330-1 to 330-N can comprise initiates queue (being respectively 338-1 to 338-N), register file (being respectively 340-1 to 340-N), sensor 108, logical one 06,110 and 112, and/or performance element (being respectively 346-1 to 346-N).

In one embodiment, each territory in territory 302,304 and 306 can comprise the communication of (such as between territory 302,304 and/or 306) between one or more first-in first-out (FIFO) buffer 348 each clock zone synchronous.

In addition, the back-end domain 306 of (such as in the embodiment shown in fig. 3) in processor core 300(and embodiment) interconnection or bus 350 can be comprised, so that the communication between all parts of processor core 300.For example, after instruction is successfully executed (after such as being performed by execution domains 330 – 1 to 330-N), the submission of this instruction can be sent to ROB318(and such as transmit via interconnection 350) to recall this instruction.In addition, the territory (such as territory 328 and 330 – 1 to 330 – N) in back-end domain can communicate via interconnection 350.For example, for type conversion instructions, the communication between performance element (330 – 1 to 330 – N) may just be there is.The further operation of the parts of Fig. 1 to Fig. 3 is discussed with reference to the method 400 of Fig. 4.

In addition, although Fig. 3 each territory shown in territory 302,304 and 306 can comprise sensor 108 and logical one 06,110 and 112, identical sensor 108 and logical one 06,110 and 112 also can be shared in each territory.For example, all territories of processor core 300 only can use one group of sensor 108 and logical one 06,110 and 112.

Fig. 4 represent according to embodiment, the process flow diagram of method 400 estimating leakage power is provided.In one embodiment, the operation of method 400 can be performed by one or more parts, such as, performed by the parts discussed with reference to Fig. 1 ~ Fig. 3 and Fig. 5 and Fig. 6.

Refer now to Fig. 1 ~ Fig. 4.In operation 402, sensor 108 can detect corresponding one or more temperature value with IC device.Measured temperature value can be used for determining the temperature calibration factor (such as utilizing storage unit 202 to be determined) in operation 404.In operation 404, voltage calibration factor also can be determined (such as utilizing storage unit 204 and/or 252 to be determined) as discussed with reference to Fig. 2 A and Fig. 2 B.In operation 406, operation 404 determined calibration factors can be used to reference-calibrating leakage value (such as unit 206 and/or 252 stores) as discussed with reference to Fig. 2 A and Fig. 2 B.In operation 408, can produce and the corresponding signal of estimation leakage power (such as by multiplier 205 and 254 produce) of this IC device.Just as was discussed in reference to fig. 1, the leakage power (408) of estimation can be used to the power consumption of one or more parts of regulating calculation system (such as with reference to the system that Fig. 1, Fig. 5 and/or Fig. 6 discuss).

In an embodiment, following equation is used to provide estimation leakage power in operation 408:

$P(V_{\mathrm{dd}},V_{\mathrm{th}},T)=P_0\·\frac{V_{\mathrm{dd}}}{V_{\mathrm{dd}0}}\·e^{\mathrm{\β}(V_{\mathrm{dd}}-V_{\mathrm{dd}0})}\·e^{\mathrm{\γ}\·(-|V_{\mathrm{th}}|+|V_{\mathrm{th}0}\left|\right)}\·e^{\mathrm{\δ}(T-T_0)}$

In above formula, P corresponds to and estimates leakage power value, P ₀corresponding to benchmark leakage power value (can be such as be stored in unit 206 and/or 252), V _ddcorresponding to supply voltage (can be provided by logical one 10), V _thcorresponding to threshold voltage (can be provided by logical one 10), V _dd0v when leaking corresponding to measuring basis _dd, V _thov when leaking corresponding to measuring basis _th, T corresponds to the current temperature value detected by sensor 108, T ₀temperature when leaking corresponding to measuring basis, δ, β and γ are set by designer, depend on the constant of circuit.In various embodiments, and corresponding value can be stored in storage unit 202, and and

$V(V_{\mathrm{dd}},V_{\mathrm{th}})=\frac{V_{\mathrm{dd}}}{V_{\mathrm{dd}0}}\·e^{\mathrm{\β}(V_{\mathrm{dd}}-V_{\mathrm{dd}0})}\·e^{\mathrm{\γ}\·(-|V_{\mathrm{th}}|+|V_{\mathrm{th}0}\left|\right)}$

Corresponding value can be stored in storage unit 204(or 252).So multiplier (208,254) can be used to T (T) and V (V _dd, V _th) carry out being multiplied to provide the value of P.

And, in one embodiment, also (such as when there is no dynamic power consumption) dynamic calibration of IC parts can be carried out at the idling mode.In this case, the temperature rise of (relative to controlled environment temperature) in each part (such as all functional blocks) of this IC parts is perhaps relevant with this leakage power.The thermal sensor 108 that can be installed among all functional blocks can report this stable temperature (such as reporting after the relatively long time interval).Utilize this hygrogram, instrument (computing equipments outside such as these IC parts) can derive the power diagram causing this situation, such as, can derive via reverse-engineering.Then, leakage value (such as, this is because other constants may be known, supply voltage, threshold voltage and environment temperature) can be calculated according to the static temperature of each several part.Once calculate 2 to go out this power diagram, just can be stored to reference to leaking storage unit 206.In an embodiment, special special microcode can be used to communication between the IC parts calibrated and testing apparatus (for example, so as to report these temperature readings and perform benchmark leak upgrade).

Fig. 5 represents the block scheme of computing system 500 according to an embodiment of the invention.Computing system 500 can comprise the one or more CPU (central processing unit) (CPU) 502 or processor that communicate via interconnection network (or bus) 504.Processor 502 can be the processor of any type, such as general processor, network processing unit (processor to the data of communication on computer network 503 process), or the processor of other types (comprising Reduced Instruction Set Computer (RISC) processor or complex instruction set computer (CISC) (CISC) processor).And processor 502 can have monokaryon or multinuclear design.Have multinuclear design processor 502 can on same integrated circuit (IC) tube core integrated dissimilar processor core.And the processor 502 with multinuclear design can also realize according to symmetrical or asymmetric multiprocessor system form.In an embodiment, one or more processor 502 can utilize the embodiment discussed with reference to Fig. 1 ~ Fig. 4.For example, one or more processor 502 can comprise one or more processor core (300).And the operation with reference to Fig. 1 ~ Fig. 4 discussion also can be performed by one or more parts of system 500.

Chipset 506 can also communicate with interconnection network 504.Chipset 506 can comprise memory control hub (MCH) 508.MCH508 can comprise the Memory Controller 510 communicated with storer 512.The instruction sequence that storer 512 can store data and the CPU502 that comprised by computing system 500 or any other equipment perform.In one embodiment of the invention, storer 512 can comprise one or more volatile storage devices (storer), such as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) etc., also nonvolatile memory can be utilized, such as hard disk.Other equipment also can be communicated by interconnection network 504, such as multi-CPU and/or multisystem storer.

MCH508 also comprises the graphic interface 514 of carrying out with graphics accelerator 516 communicating.In one embodiment of the invention, graphic interface 514 can communicate with graphics accelerator 516 via Accelerated Graphics Port (AGP).In an embodiment of the present invention, display (such as flat-panel monitor) can communicate with graphic interface 512 via such as signal converter, and the numerical method of the image be stored in memory device (such as video memory or system storage) is converted to the display that can explained by display and show by this signal converter.The display produced by this display apparatus needed by various opertaing device before also being shown over the display subsequently by explanation.

Hub-interface 518 can make MCH508 communicate with I/O control center (ICH) 520.ICH520 can for providing interface with the I/O equipment that the parts of computing system 500 carry out communicating.ICH520 can communicate with bus 522 via peripheral bridge (or controller) 524, such as, communicate via peripheral component interconnect (pci) bridge, USB (universal serial bus) (USB) controller etc.Bridge 524 can provide the data channel between CPU502 and peripherals.Also the topological structure of other types can be adopted.And multiple bus can communicate with ICH520, such as, communicated by multiple bridge or controller.In addition, in various embodiments of the present invention, other peripheral hardwares communicated with ICH520 also comprise integrated drive electronics (IDE) or small computer system interface (SCSI) hard disk drive, USB port, keyboard, mouse, parallel port, serial port, floppy disk, numeral output support equipment (such as digital visual interface (DVI)) etc.

Bus 522 can be carried out communicate (Network Interface Unit 530 communicates with computer network 503) with audio frequency apparatus 526, one or more disc driver 528 and Network Interface Unit 530.Other equipment can communicate with bus 522.And in some embodiments of the invention, all parts (such as Network Interface Unit 530) can communicate with MCH508.In addition, processor 502 and MCH508 can be combined formation one single chip.And in other embodiments of the invention, graphics accelerator 516 can be contained among MCH508.

In addition, computing system 500 can comprise volatibility and/or nonvolatile memory (or memory storage).For example, nonvolatile memory can comprise the one or more equipment in following equipment: ROM (read-only memory) (ROM), programming ROM (PROM), erasable PROM(EPROM), electronics EPROM(EEPROM), disc driver, floppy disk, CD ROM(CD-ROM), digital versatile disk [Sony] (DVD), flash memories, magneto-optic disk or other types can the nonvolatile machine-readable media of store electrons instruction and/or data.

Fig. 6 represents according to an embodiment of the invention, according to the computing system 600 of point-to-point (PtP) structural design.Particularly, Fig. 6 shows the system that processor, storer and input-output apparatus are connected to each other by some point-to-point interfaces.The operation discussed with reference to Fig. 1 ~ Fig. 5 can be performed by one or more parts of system 600.

As shown in Figure 6, system 600 can comprise several processor, but for clarity, wherein only depicts 2 processors: processor 602 and 604.Processor 602 and 604 can each self-contained local memory controller hub (MCH) 606 and 608 to communicate with storer 610 and 612.Storer 610 and/or 612 can store various data, such as, with reference to those data that storer 512 is discussed.

Processor 602 and 604 can be the processor of any type, such as, with reference to that class processor that the processor 502 of Fig. 5 is discussed.Processor 602 and 604 can adopt PtP interface circuit 616 and 618 to exchange data via point-to-point (PtP) interface 614.Processor 602 and 604 can adopt point-to-point interface circuit 626,628,630 and 632 and chipset 620 to exchange data via independent PtP interface 622 and 624 separately.Chipset 620 can also adopt PtP interface circuit 637 and high performance graphics circuit 634 to exchange data via high performance graphics interface 636.

At least one embodiment of the present invention can realize in processor 602 and 604 inside.For example, one or more territories 102 of discussing with reference to Fig. 1 and/or processor core 300 can be positioned within processor 602 and 604.But other circuit, logical block or equipment within the system 600 of Fig. 6 also can adopt other embodiments of the present invention.In addition, other embodiments of the present invention can be distributed among several circuit, logical block or the equipment shown in Fig. 6.

Chipset 620 can adopt PtP interface circuit 641 to communicate with bus 640, and bus 640 can have one or more equipment communicated with it, such as bus bridge 642 and I/O equipment 643.Bus bridge 643 can communicate with other equipment via bus 644, the modulator-demodular unit, Network Interface Unit etc. that such as such as can communicate with computer network 503 with keyboard/mouse 645, communication facilities 646(), audio frequency I/O equipment and/or data storage device 648.Data storage device 648 can store the code 649 performed by processor 602 and/or 604.

In various embodiments of the present invention, operation discussed in this article (such as with reference to Fig. 1 ~ Fig. 6 discuss) can realize by as the software of computer program, firmware, microcode, hardware (circuit) or their combination, such as, these products comprise machine-readable or computer-readable medium, these media then store and is used for computer programming to perform the instruction of process described herein.And exemplarily, term " logic " can comprise the combination of software, hardware, firmware or software and hardware.This machine readable media can comprise memory device, such as, with reference to those equipment that Fig. 1 ~ Fig. 6 discusses.In addition, these computer-readable mediums can be downloaded as computer program, wherein, this program can by realizing by carrier format or being transferred to requesting computer (such as client computer) via communication linkage (such as bus, modulator-demodular unit or network connect) from remote computer (such as server) by the data-signal that other propagation mediums realize.So, in this article, will think that carrier wave comprises machine readable media.

In this specification, mentioned " embodiment " or " embodiment " refers to, can be included at least among embodiment about characteristic, structure or the feature described by this embodiment.The phrase " in one embodiment " occurred in the difference place of this instructions may all refer to same embodiment, also may not all refer to same embodiment.

And, in the specification and in the claims, term " coupling " and " connection " and their derivation term can be adopted.In some embodiments of the invention, " connection " two or more element direct physical or electrical contact each other can be used to represent." coupling " can represent two or more element direct physical or electrical contact; But " coupling " can also represent that perhaps two or more element does not directly contact each other, but still can coordinated with each other or reciprocation.

So, although all embodiments of the present invention have adopted the language being exclusively used in architectural feature and/or square sexual act to be described, should be appreciated that the theme to it proposes claim may be not limited to these described special characteristics or action.On the contrary, these special characteristics and behavior just as theme required by realizing exemplary forms and announced.

Claims (14)

1. a processor, comprising:

Multiple core, wherein, each core comprises:

For extracting the instruction fetch unit of instruction;

For the instruction decode unit of decoding to described instruction;

Inch prediction unit;

Register file;

There is the high-speed cache of multiple level cache, comprise the first order (L1) high-speed cache and the second level (L2) high-speed cache;

For performing multiple performance elements of described instruction;

Wherein, each core is organized into multiple territory, and each territory operates with the voltage of specifying and frequency,

Wherein, by described L2 cache assignment to first territory with the first voltage and frequency, and at least one other logical block of described processor is distributed to second territory with the second voltage and frequency;

For performing the logic of the operation relevant with power service condition while determining leakage contribution.

2. processor as claimed in claim 1, wherein, each territory in described multiple territory is communicated with other territories in described multiple territory by one or more impact damper.

3. processor as claimed in claim 2, wherein, described one or more impact damper comprises fifo buffer.

4. processor as claimed in claim 1, wherein, voltage and/or the frequency in each territory in described multiple territory are adjustable.

5. processor as claimed in claim 1, wherein, each core in described multiple core comprises interconnection or bus, so that the communication between all parts in this core.

6. processor as claimed in claim 1, wherein, each core in described multiple core comprises rearrangement impact damper.

7. processor as claimed in claim 1, wherein, each core in described multiple core comprises renames and guide unit.

8. a method, comprising:

A processor core is organized into multiple territory, each territory operates with the voltage of specifying and frequency, wherein, by the second level (L2) cache assignment of described processor core to first territory with the first voltage and frequency, and at least one other logical block of described processor core is distributed to second territory with the second voltage and frequency;

The operation relevant with power service condition is performed while determining leakage contribution.

9. method as claimed in claim 8, wherein, each territory in described multiple territory is communicated with other territories in described multiple territory by one or more impact damper.

10. method as claimed in claim 9, wherein, described one or more impact damper comprises fifo buffer.

11. methods as claimed in claim 8, wherein, voltage and/or the frequency in each territory in described multiple territory are adjustable.

12. methods as claimed in claim 8, wherein, described processor core comprises interconnection or bus, so that the communication between all parts in this processor core.

13. methods as claimed in claim 8, wherein, described processor core comprises rearrangement impact damper.

14. methods as claimed in claim 8, wherein, described processor core comprises renames and guide unit.