CN102931205B - A kind of memory device and formation method - Google Patents
A kind of memory device and formation method Download PDFInfo
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- CN102931205B CN102931205B CN201110231646.7A CN201110231646A CN102931205B CN 102931205 B CN102931205 B CN 102931205B CN 201110231646 A CN201110231646 A CN 201110231646A CN 102931205 B CN102931205 B CN 102931205B
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Abstract
A kind of memory device, comprising: transistor area, is formed with the transistor of at least one deck in described transistor area; Interconnection structure district, comprise the metal level interconnected mutually of at least one deck, described interconnection structure district is positioned at the top of transistor area, and is electrically connected with described transistor area; Between described interconnection structure district and transistor area, be also formed with magnetic tunnel interface.The present invention also provides a kind of formation method of memory device.By the MTJ of original position in interconnection structure district being positioned over the region between transistor area and interconnection structure district, make the size restrictions of the metal level in the not restricted described interconnection structure district of described MTJ, the size of MTJ can be reduced, to improve the number of densities of the MTJ in memory device, improve the memory capacity of memory device.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of memory device and formation method.
Background technology
MAGNETIC RANDOM ACCESS MEMORY (MagnetoResistiveRandomAccessMemory, MRAM) be solid-state memory, it mainly utilizes the change of the direction of magnetization of the MTJ (MTJ) as information recording carrier, to reach the effect of writing and reading recorded information.
There is in described MTJ self fixing magnetic direction, when the electric current provided flows through described MTJ, described MTJ will be magnetized, and namely in described MTJ, produce the direction of magnetization when the external world.When the direction of magnetization is identical with fixing magnetic direction, described MTJ is in parastate; When the direction of magnetization is contrary with fixing magnetic direction, then described MTJ is in antiparallel state.The parastate of described MTJ and antiparallel state carry out corresponding with binary one, 0 respectively, with the record of the information of carrying out.Particularly, when MTJ is in parastate, described MTJ has low resistance, and this state is " 0 " state.Otherwise when MTJ is in antiparallel state, described MTJ has high value, and this state is one state.More can a kind of MAGNETIC RANDOM ACCESS MEMORY structure of referenced patent number for providing in the patent document of ZL200510069671.4.
Usually, semiconductor device comprises the transistor area and the interconnection structure district for being connected the transistor of transistor area that are positioned at bottom, and described interconnection structure district is positioned at the top of transistor area, and is made up of more metal layers and dielectric layer.Wherein, from the metal level near transistor area calculate, be followed successively by the first metal layer, the second metal level, the 3rd metal level ...Above-mentioned MTJ is generally positioned in interconnection structure district, and is usually located at the position between first layer metal layer and the second metal level, or the position between the second metal level and the 3rd metal level.
Prior art usually through the density of the MTJ increased in memory device, to improve the memory capacity of memory device.But because described MTJ is positioned at interconnection structure district, the size of described MTJ will be subject to the size constrained of the metal level formed before described MTJ, namely the size of described MTJ must not be less than and is adjacent, and the size of the size of the metal level formed before being positioned at it.
Summary of the invention
The problem that the present invention solves is to provide a kind of memory device and forming method thereof, to avoid the size of the MTJ in memory device by the size restrictions in interconnection structure district, further, the size of MTJ can be reduced, to improve the number of densities of the MTJ in memory device, improve the memory capacity of memory device.
For solving the problem, the invention provides a kind of memory device, comprising:
Transistor area, is formed with the transistor of at least one deck in described transistor area;
Interconnection structure district, described interconnection structure district is positioned at the top of transistor area, and is electrically connected with described transistor area;
Between described interconnection structure district and transistor area, be also formed with magnetic tunnel interface.
Optionally, the MTJ one end in described magnetic tunnel interface is electrically connected with described transistor area, and one end is electrically connected with described interconnection structure district.
Optionally, described magnetic tunnel interface is electrically connected with described transistor area by bottom syndeton, and described bottom syndeton comprises dielectric layer and is positioned at the metal throuth hole of described dielectric layer.
Optionally, the surface in described dielectric layer nearly magnetic tunnel interface flushes with the apparent height in the nearly magnetic tunnel interface of described metal throuth hole.
Optionally, be formed with the metal level of at least one deck in described metal throuth hole, wherein, the Mohs' hardness coefficient of the metal level in nearly magnetic tunnel interface is less than the Mohs' hardness coefficient of tungsten.
Optionally, be formed with the metal level of at least one deck in described metal throuth hole, wherein, the Mohs' hardness coefficient of the metal level in nearly magnetic tunnel interface is less than 7.0.
Optionally, be formed with at least one deck metal level in described metal throuth hole, wherein, the metal level in nearly magnetic tunnel interface is titanium nitride, one of titanium or copper or combination.
Optionally, described magnetic tunnel interface comprises the MTJ of at least one deck, and described MTJ comprises nailed layer and free magnetic layer, and the tunnel barriers between described nailed layer and free magnetic layer.
The present invention also provides a kind of formation method of memory device, comprising:
The substrate being formed with transistor area is provided;
Form the interconnection structure district be positioned at above substrate, be electrically connected with described transistor area;
Before the described interconnection structure district of formation, also comprise and form magnetic tunnel interface, described magnetic tunnel interface is electrically connected with transistor area.
Optionally, comprising: form bottom syndeton at described substrate surface; Then form magnetic tunnel interface on described bottom syndeton surface, described magnetic tunnel interface is connected with described transistor area by bottom syndeton.
Optionally, comprising: described formation bottom syndeton comprises: form dielectric material at described substrate surface, and carry out etching the dielectric layer forming through hole and be positioned at adjacent through-holes to described dielectric material; Carry out metal filled to described through hole, form metal throuth hole, described metal throuth hole and dielectric layer form bottom syndeton, and wherein, described dielectric layer surface flushes with described metal throuth hole apparent height.
Optionally, described to described through hole carry out metal filled after, also comprise and carry out cmp to described dielectric layer surface and flush with described metal throuth hole apparent height.
Optionally, be formed with the metal level of at least one deck in described metal throuth hole, wherein, the Mohs' hardness coefficient of the metal level in nearly magnetic tunnel interface is less than the Mohs' hardness coefficient of tungsten.
Optionally, the hardness factor of the metal level in described nearly magnetic tunnel interface is less than 7.0.
Optionally, describedly metal filledly to comprise: first described through hole is carried out first metal filled, then etching is carried out back to the first metal, make the packed height of described first metal be less than described via height; Then again carry out filling second metal to described dielectric layer surface to described through hole to flush with described metal throuth hole apparent height.
Optionally, describedly filling is carried out again to described through hole comprise: first to described filling through hole second metal, and the surface of packed height is higher than the surface of described dielectric layer; Adopt the second metal described in cmp, until described dielectric layer surface flushes with described metal throuth hole apparent height.
Optionally, described first metal is tungsten, and described second metal is titanium nitride, one of titanium or copper or combination.
Optionally, comprising: described via top opening is greater than bottom opening.
Compared with prior art, the present invention has the following advantages:
By the MTJ of original position in interconnection structure district being positioned over the region between transistor area and interconnection structure district, make described MTJ not by the size restrictions of the metal level in described interconnection structure district, the size of MTJ can be reduced, to improve the number of densities of the MTJ in memory device, improve the memory capacity of memory device.
Further, the surface in the metal throuth hole nearly magnetic tunnel interface in described bottom syndeton flushes with the surface in the nearly magnetic tunnel interface of dielectric layer, make the surfacing in described bottom syndeton nearly magnetic tunnel interface smooth, then make the location criteria of the MTJ of follow-up formation, and then the magnetic direction stability criterion that described MTJ produces, improve the reliability of described memory device.
Prior art generally adopts tungsten to form metal throuth hole, be connected with interconnection structure district to make described transistor area, the present invention first carries out part to the tungsten in metal throuth hole and returns etching, recharge the less metal being easy to grind of hardness factor, dielectric layer surface is flushed with the surface of described metal throuth hole.With existing process compatible, can not affect the electric property of device, and can not cause the complexity of technique, tungsten is as the metal be connected with described bottom syndeton simultaneously, and its reliability is higher.
Accompanying drawing explanation
Fig. 1 is the structural representation of the memory device of one embodiment of the invention.
Fig. 2 is the structural representation of the memory device of further embodiment of this invention.
Fig. 3 to Figure 13 is the structural representation of the formation method of the memory device of one embodiment of the invention.
Embodiment
The MTJ of prior art is positioned at interconnection structure district, the size of described MTJ will be subject to the size constrained of the metal level formed before described MTJ, and namely described MTJ is not less than and is adjacent and is positioned at the size of the size of the metal level formed before it.Limit the number of densities of the MTJ in memory device, further limit the memory capacity of memory device.
For solving the problem, the invention provides a kind of structure of memory device, comprising:
Transistor area, is formed with the transistor of at least one deck in described transistor area;
Interconnection structure district, described interconnection structure district is positioned at the top of transistor area, and is electrically connected with described transistor area;
Between described interconnection structure district and transistor area, be also formed with magnetic tunnel interface.
The present invention is by being positioned over the region between transistor area and interconnection structure district by the MTJ of original position in interconnection structure district, make the size restrictions of the metal level in the not restricted described interconnection structure district of described MTJ, the size of MTJ can be reduced, to improve the number of densities of the MTJ in memory device, improve the memory capacity of memory device.
Be illustrated in figure 1 the structural representation of the memory device of one embodiment of the invention, comprise: transistor area 001, in described transistor area 001, be formed with the transistor of at least one deck;
Be positioned at the interconnection structure district 005 on surface, described transistor area 001, described interconnection structure district 005 comprises at least two-layer metal level interconnected mutually, and described interconnection structure district 005 is positioned at the top of transistor area 001, and is electrically connected with described transistor area 001;
Between described interconnection structure district 005 and transistor area 001, be formed with magnetic tunnel interface 003, described magnetic tunnel interface 003 comprises MTJ 0031 and insulating material 0032.Described magnetic tunnel interface 003 comprises the MTJ 0031 of at least one deck, and described MTJ 0031 comprises nailed layer and free magnetic layer, and the tunnel barriers between described nailed layer and free magnetic layer.Structure about MTJ 0031 is introduced in detail by follow-up formation process.
Wherein, the one end in described magnetic tunnel interface 003 is electrically connected with described transistor area 001, and one end is electrically connected with described interconnection structure 005.Wherein, described magnetic tunnel interface 003 is connected with described transistor area 001 by bottom syndeton 220.Described bottom syndeton 220 comprises metal throuth hole 0022 and dielectric layer 0021.Wherein, the surface in the nearly magnetic tunnel interface 003 of described dielectric layer 0021 flushes with the apparent height in the nearly magnetic tunnel interface 003 of described metal throuth hole 0022, to make the MTJ 0031 in magnetic tunnel interface 003, there is a smooth formation surface, then make the location criteria of the MTJ formed on described surface, and then the magnetic direction stability criterion that described MTJ produces, improve the reliability of described memory device.
In prior art, be tungsten to the packing material major part of described metal throuth hole 0022, and the hardness factor of tungsten is higher, is not easy to grinding, easily cause the height of height higher than dielectric layer of the rear metal throuth hole of grinding, namely described MTJ to be formed 0031 is rough smooth.Affect the reliability of device.
For solving the problem, the metal throuth hole that the invention provides in the memory device of an embodiment can for the metal level of at least one layer, and wherein, the hardness factor of the metal level in nearly magnetic tunnel interface is at least less than the hardness factor of tungsten, as being less than 7.5.Or the Mohs' hardness coefficient of the metal level in nearly magnetic tunnel interface is less, as being less than 7.0.
As shown in Figure 2, the metal in described metal throuth hole 0022 can also be that the metal layer stack of at least one deck is formed, and the present embodiment illustrate only 2 layers of metal level, is respectively the first metal layer 0022a and the second metal level 0022b.Wherein, described the first metal layer 0022a is tungsten, and described second metal level 0022b is the material that hardness factor is less than tungsten, as titanium nitride, one of titanium or copper or combination.
The present invention also provides a kind of formation method of memory device, comprising:
The substrate being formed with transistor area is provided;
Form the interconnection structure district be positioned at above substrate, comprise the metal level interconnected mutually of at least one deck, and be electrically connected with described transistor area;
Before the described interconnection structure district of formation, also comprise and form magnetic tunnel interface, described magnetic tunnel interface is electrically connected with transistor area.
Be described below in conjunction with the formation method of accompanying drawing to the memory device of one embodiment of the invention.
As shown in Figure 3, provide substrate 100, described substrate 100 is formed dielectric layer material (not shown).And etching formation through hole 200 and the dielectric layer 110 between described through hole 200 are carried out to described dielectric material.
Further, for improving follow-up filling effect, the top dimension of described through hole 200 is greater than bottom size.
As shown in Figure 4, metal filled to carrying out first in described through hole, form the first metal layer 210.The surface of the first metal layer 210 originally illustrated flushes with the surface of dielectric layer 110.In actual process, described the first metal layer 210 may below or above the surface of described dielectric layer 110.In the present embodiment, described first metal is tungsten.Tungsten is as a kind of metal for connecting transistor area 100, and the current range of bearing is comparatively large, and its reliability is larger.But the Mohs' hardness coefficient of tungsten is higher, is about 7.5, namely be only difficult to make described the first metal layer 210 form the surface flushed with dielectric layer 110 by grinding.In the present embodiment, etching will be carried out back to described the first metal layer 210, and the less material of hard coefficient be filled again to described through hole, the state flushed with dielectric layer 110 surface with the surface reaching metal throuth hole.As other embodiments, also the material of hard coefficient less (as being less than hardness decimal 7.0) can directly be used, as used the material being less than the Mohs' hardness coefficient 7.5 of tungsten, as titanium nitride, titanium or copper, the state flushed with dielectric layer 110 surface with the surface reaching metal throuth hole.But compared with tungsten, other material to bear current range less, the reliability of the device of formation is lower.
Further, prior art generally adopts tungsten that described transistor area is connected with interconnection structure district, the present invention first carries out part to tungsten and returns etching, recharges the less metal being easy to grind of hardness factor, dielectric layer surface is flushed with the surface of metal throuth hole.With existing process compatible, the electric property of device can not be affected, and the complexity of technique can not be caused.
As shown in Figure 5, etching is carried out back to described the first metal layer, form the first metal layer 210 '.The height of described the first metal layer 210 ' is less than the height of described through hole, and namely described through hole has part not also to be filled with metal material.
As shown in Figure 6, depositing second metal layer 220, the hardness factor of described second metal level 220 is lower, as being less than Mohs' hardness coefficient 7.5.The surface of described second metal level 220, higher than the surface of described dielectric layer 110, is carried out cmp so that follow-up to described second metal level 220, is made described second metal level 220 have the surface flushed with dielectric layer 110.
As shown in Figure 7, with described dielectric layer 110 for polish stop layer, cmp is carried out to described second metal level 220, forms the second metal level 220 '.The surface of described second metal level 220 ' is flushed with the surface of described dielectric layer 110.Described second metal level 220 ' forms bottom syndeton with described dielectric layer 110.Described bottom syndeton is connected making the magnetic tunnel interface of follow-up formation with transistor area.
Wherein, the surface of described second metal level 220 ' flushes with the surface of described dielectric layer 110, then described bottom syndeton has smooth surface, and described surface is the formation surface in follow-up formation magnetic tunnel interface, the described smooth position in magnetic tunnel interface and the standard of size that can improve follow-up formation forming surface, again because the magnetic field in magnetic tunnel interface is larger by the position influence of the size in magnetic tunnel interface, the standard improving position and size then can improve the standard in generation magnetic field, magnetic tunnel interface, the reliability of further raising memory device.
As shown in Figure 8, MTJ material layer 230 is formed on described bottom syndeton surface.In the lump with reference to shown in figure 8 and Fig. 9, the photoresist layer (not shown) of patterning is formed at described MTJ material layer 230, and with the photoresist layer of described patterning for mask, described MTJ material layer 230 is etched, form MTJ 231.Described MTJ 231 is electrically connected with transistor area 100 by bottom syndeton.
Wherein, hard mask layer (not shown) can also be formed between described photoresist layer (not shown) and described MTJ material layer 230, with the photoresist layer of described patterning for mask, described hard mask layer and described MTJ material layer 230 are etched, form MTJ 231, finally remove the hard mask layer of post-etch residue.
Be the structural representation of described MTJ as shown in Figure 10 and Figure 11, described MTJ comprises: bottom electrode (BottomElectrode) 010, the pinned magnetosphere (PinnedMagneticLayer) 020 being positioned at described bottom electrode 010 surface and the free magnetic layer 040 be positioned in described pinned magnetic 020, be formed with tunnel barriers 030 between described free magnetic layer and described pinned magnetosphere 020.
As shown in arrow in the pinned magnetosphere 020 of Figure 10, the magnetic orientation in pinned magnetosphere 020 is fixed.Can obtain by making bottom electrode 010 contact also heat treatment (temperature range is about 200 DEG C ~ 300 DEG C) with nailed layer 020.By heat treatment process, the magnetic direction of nailed layer 020 becomes fixing and is exposed to afterwards in external magnetic field and also can not overturn.Namely the magnetic moment of described nailed layer 020 is fixed to the direction shown by the arrow in Figure 10 nailed layer 020.On the contrary, be formed between nailed layer 020 and free magnetic layer 040 because tunnel barriers 030 is fixed, so the magnetic direction of free magnetic layer 040 keeps non-stationary state, can be following situation: as shown in Figure 10, the magnetic direction of described free magnetic layer 040 be consistent with the magnetic direction of nailed layer 020; As shown in figure 11, the magnetic direction of described free magnetic layer 040 is contrary with the magnetic direction of nailed layer 020.Under the impact of extraneous magnetic field, the magnetic direction of free magnetic layer 040 can change.
When the magnetic direction of described free magnetic layer 040 is consistent with the magnetic direction of nailed layer 020 time, be the parastate of MTJ, described magnetic tunnel becomes low resistive state, and it is defined as " 0 " state of logical states; When the magnetic direction of described free magnetic layer 040 is contrary with the magnetic direction of nailed layer 020, be the antiparallel state of MTJ, described magnetic tunnel becomes high-impedance state, and it is defined as the one state of logical states.
As an embodiment, as shown in figure 12, described nailed layer 020 is formed by three layers, comprises bottom magnetosphere 021, metal level 022 and top magnetosphere 023.As an embodiment, described top magnetosphere 021 and bottom magnetosphere 023 can be CoFe, and described metal level 022 can be Ru.
Described tunnel barriers 030 is insulator, and as an embodiment, described tunnel barriers 030 can be Al
2o
3.
Described free magnetic layer 040 is a double-decker, and the lower magnetosphere 041 thin by one deck and the upper magnetosphere 042 of thick layer form.As an embodiment, described lower magnetosphere 041 can be CoFe, and described upper magnetosphere 042 can be NiFe.
As shown in figure 13, insulation material layer 232 will be formed between described MTJ 231.Described insulation material layer 232 forms magnetic tunnel district with described MTJ 231.
Continue with reference to Figure 13, subsequently in described magnetic tunnel district, form interconnection structure 130, the metal level that described interconnection structure 130 comprises at least one deck is formed, and described interconnection structure 130 is electrically connected with described transistor area 100 by magnetic tunnel interface and bottom syndeton.
Compared with prior art, the present invention has the following advantages: by the MTJ of original position in interconnection structure district being positioned over the region between transistor area and interconnection structure district, make the size restrictions of the metal level in the not restricted described interconnection structure district of described MTJ, the size of MTJ can be reduced, to improve the number of densities of the MTJ in memory device, improve the memory capacity of memory device.
Further, the surface in the metal throuth hole nearly magnetic tunnel interface in described bottom syndeton flushes with the surface in the nearly magnetic tunnel interface of dielectric layer, make the surfacing in described bottom syndeton nearly magnetic tunnel interface smooth, then make the location criteria of the MTJ of follow-up formation, and then the magnetic direction stability criterion that described MTJ produces, improve the reliability of described memory device.
Prior art generally adopts tungsten to form metal throuth hole, be connected with interconnection structure district to make described transistor area, the present invention first carries out part to the tungsten in metal throuth hole and returns etching, recharge the less metal being easy to grind of hardness factor, dielectric layer surface is flushed with the surface of described metal throuth hole.With existing process compatible, can not affect the electric property of device, and can not cause the complexity of technique, tungsten is as the metal be connected with described bottom syndeton simultaneously, and its reliability is higher.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (5)
1. a memory device, is characterized in that, comprising:
Transistor area, is formed with the transistor of at least one deck in described transistor area;
Interconnection structure district, described interconnection structure district is positioned at the top of transistor area, and is electrically connected with described transistor area;
Between described interconnection structure district and transistor area, also be formed with magnetic tunnel interface, described magnetic tunnel interface is electrically connected with described transistor area by bottom syndeton, described bottom syndeton comprises dielectric layer and is positioned at the metal throuth hole of described dielectric layer, at least one deck metal level is formed in described metal throuth hole, wherein, the metal level in nearly magnetic tunnel interface is copper, the surface in described dielectric layer nearly magnetic tunnel interface is flushed with the surface in the nearly magnetic tunnel interface of described metal throuth hole, and near described copper metal layer in described metal throuth hole is tungsten.
2. memory device as claimed in claim 1, it is characterized in that, the MTJ one end in described magnetic tunnel interface is electrically connected with described transistor area, and one end is electrically connected with described interconnection structure district.
3. memory device as claimed in claim 1, it is characterized in that, described magnetic tunnel interface comprises the MTJ of at least one deck, and described MTJ comprises nailed layer and free magnetic layer, and the tunnel barriers between described nailed layer and free magnetic layer.
4. a formation method for memory device, is characterized in that, comprising:
The substrate being formed with transistor area is provided;
Bottom syndeton is formed at described substrate surface;
Form the interconnection structure district be positioned at above substrate, be electrically connected with described transistor area;
Before the described interconnection structure district of formation, be also included in described bottom syndeton surface and form magnetic tunnel interface, described magnetic tunnel interface is electrically connected with transistor area by bottom syndeton;
Wherein, described formation bottom syndeton comprises: form dielectric material at described substrate surface, and carries out etching the dielectric layer forming through hole and be positioned at adjacent through-holes to described dielectric material; Carry out metal filled to described through hole, form metal throuth hole, describedly metal filledly to comprise: first described through hole is carried out first metal filled, then carry out back etching to the first metal, make the packed height of described first metal be less than described via height; Then filling second metal is carried out again to described through hole, and the surface of packed height is higher than the surface of described dielectric layer; Adopt the second metal described in cmp, until described dielectric layer surface flushes with described metal throuth hole surface, described first metal is tungsten, and described second metal is copper.
5. the formation method of memory device as claimed in claim 4, is characterized in that, comprising: described via top opening is greater than bottom opening.
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| US9159910B2 (en) * | 2008-04-21 | 2015-10-13 | Qualcomm Incorporated | One-mask MTJ integration for STT MRAM |
| JP2010103224A (en) * | 2008-10-22 | 2010-05-06 | Toshiba Corp | Magneto-resistance element and magnetic memory |
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