Summary of the invention
In view of this, the problem of addressing for improving prior art, an example embodiment of the present invention provides a kind of source electrode driving device, and it comprises at least: output buffer stage and province's electric line.Wherein an output buffer stage operates under the dual power supply, and comprises that at least a positive output passage and that couples one first data line of a display panel couples a negative output passage of one second data line of this display panel.Economizing electric line is coupled between output buffer stage and the display panel, be used in this output buffer stage by positive output passage and negative output passage with before driving the first data line and one second data line, collect from the electric charge of the equivalent load capacitance of described the first data line and the second data line; And this output buffer stage by positive output passage and negative output passage with drive the first data line and one second data line during, adopt collected electric charge and one in a positive supply of this dual power supply and the negative supply charged.
In the present invention's one example embodiment, the output buffer stage comprises at least: the first impact damper and the second impact damper.Wherein, the first impact damper and corresponds to this positive output passage under this positive supply and an earthing potential.The second impact damper and corresponds to described negative output passage under described negative supply and described earthing potential.
In the present invention's one example embodiment, the source electrode driving device of being carried can more comprise: a Channel Exchange circuit, be coupled between this output buffer stage and this province's electric line, in order to two output channels and the first data line of display panel and the annexation between the second data line that alternately changes this output buffer stage, wherein, this first data line is coupled in positive output passage and the negative output passage one by this Channel Exchange circuit, and this second data line is coupled to another one in positive output passage and the negative output passage by this Channel Exchange circuit.
In the present invention's one example embodiment, to economize electric line and possess an ability of charging that has in described positive supply and the described negative supply, this province's electric line can comprise: the first to the 8th switch and striding capacitance.Wherein, the first end of the first switch couples described the first data line.The first end of striding capacitance couples the second end of the first switch.The first end of second switch couples the second end of striding capacitance, and the second end of second switch then is coupled to described the second data line.The first end of the 3rd switch couples described the first data line, and the second end of the 3rd switch then is coupled to described earthing potential.The first end of the 4th switch couples described the second data line, and the second end of the 4th switch then is coupled to described earthing potential.The first end of the 5th switch couples the first end of striding capacitance, and the second end of the 5th switch then is coupled to described positive supply.The first end of the 6th switch couples the first end of striding capacitance, and the second end of the 6th switch then is coupled to described earthing potential.The first end that minion is closed couples the second end of striding capacitance, and the second end that minion is closed then is coupled to described earthing potential.The first end of the 8th switch couples the second end of striding capacitance, and the second end of the 8th switch then is coupled to described negative supply.
In the present invention's one example embodiment, province's electric line (only) possesses the ability that described negative supply is charged is arranged, and this province's electric line can comprise: the first to the 6th switch and striding capacitance.Wherein, the first end of the first switch couples described the first data line.The first end of striding capacitance couples the second end of the first switch.The first end of second switch couples the second end of striding capacitance, and the second end of second switch then is coupled to described earthing potential.The first end of the 3rd switch couples described the first data line, and the second end of the 3rd switch then is coupled to described earthing potential.The first end of the 4th switch couples described the second data line, and the second end of the 4th switch then is coupled to described earthing potential.The first end of the 5th switch couples the first end of striding capacitance, and the second end of the 5th switch then is coupled to described the second data line.The first end of the 6th switch couples the second end of striding capacitance, and the second end of the 6th switch then is coupled to described negative supply.
In the present invention's one example embodiment, province's electric line (only) possesses the ability that described positive supply is charged is arranged, and this province's electric line can comprise: the first to the 6th switch and striding capacitance.The first end of the first switch couples described the second data line.The first end of striding capacitance couples the second end of the first switch.The first end of second switch couples the second end of striding capacitance, and the second end of second switch then is coupled to described earthing potential.The first end of the 3rd switch couples described the first data line, and the second end of the 3rd switch then is coupled to described earthing potential.The first end of the 4th switch couples described the second data line, and the second end of the 4th switch then is coupled to described earthing potential.The first end of the 5th switch couples the first end of striding capacitance, and the second end of the 5th switch then is coupled to described the first data line.The first end of the 6th switch couples the second end of striding capacitance, and the second end of the 6th switch then is coupled to described positive supply.
Another example embodiment of the present invention provides a kind of flat-panel screens, and it comprises: display panel and aforementioned carry in order to drive at least described the first data line in the display panel, the source electrode driving device of the second data line.
In an example embodiment of the present invention, display panel can more comprise the multi-strip scanning line.The base this, the flat-panel screens of carrying can more comprise: gate drive device and time schedule controller.Wherein, a gate drive device drives described multi-strip scanning line in order to order; And time schedule controller couples this source electrode driving device and this gate drive device, does in order to the running of controlling this source electrode driving device and this gate drive device.
In an example embodiment of the present invention, the flat-panel screens of carrying can be liquid crystal display.Base this, the flat-panel screens of carrying can more comprise: backlight module, it is in order to supplying display panel required light source, and for example can be cold-cathode tube (CCFL) backlight module or light-emittingdiode (LED) backlight module.
Based on above-mentioned, in the present invention, before driving each data line of display panel, can be first collect from the electric charge of the equivalent load capacitance of each data line by economizing striding capacitance in the electric line, then again the residual charge of the equivalent load capacitance of each data line is released into ground.On the other hand, during each data line that drives display panel, can utilize collected electric charge to carry out (mistakes) with the one to the positive and negative dual power supply of output buffer stage and charge.Thus, based on collected electric charge is carried out behavior/mode that (mistakes) charges with the one of positive and negative dual power supply to the output buffer stage, can be so that source electrode driving device has the mechanism of power saving.
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, concrete example embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Yet, will be appreciated that, above-mentioned general description and following embodiment only are exemplary and illustrative, it can not limit the scope that institute of the present invention wish is advocated.
Now will in detail with reference to example embodiment of the present invention, the example of described example embodiment be described in the accompanying drawings.In addition, all possibility parts, the element of use same numeral in graphic and embodiment/the identical or similar portions of member representative.
Fig. 1 is the system schematic of the flat-panel screens (flat panel display) 10 of the present invention's one example embodiment.See also Fig. 1, flat-panel screens 10 for example can be liquid crystal display (liquid crystaldisplay, LCD), but is not restricted to this.The base this, flat-panel screens 10 can comprise: (liquid crystal) display panel (display panel) 101, source electrode driving device (source driving apparatus) 103, gate drive device (gate driving apparatus) 105, time schedule controller (timing controller, T-con) 107, and backlight module (backlight module) 109.
In this example embodiment, display panel 101 has many vertically disposed data lines (datalines) DL, many horizontally disposed sweep traces (scan lines) SL, and a plurality of picture element (pixels) P that arranges (M*N) with matrix-style.In what this be worth to explain be because (liquid crystal) display panel 101 itself does not have self luminous characteristic, so 109 of backlight modules must supply (liquid crystal) display panel 101 required (back of the body) light sources (backlight source).Wherein, backlight module 109 can or be light-emittingdiode (light emitting diode, LED) backlight module for cold-cathode tube (cold cathode fluorescent lamp, CCFL) backlight module.
Time schedule controller 107 couples between source electrode driving device 103 and the gate drive device 105, in order to control the overall operation of source electrode driving device 103 and gate drive device 105.In other words, gate drive device 105 is controlled by time schedule controller 107, in order to sequentially to produce scanning signal (scan signal) to drive one by one all sweep trace SL in (liquid crystal) display panel 101 (or meaning, open one by one all the row picture elements in the display panel 101); In addition, source electrode driving device 103 is controlled by time schedule controller 107, in order to provide/to produce corresponding data voltage (data voltage) to the row picture element of being opened by gate drive device 105.
In brief, under the control of time schedule controller 107, source electrode driving device 103 can work in coordination with the scanning signals that produce in 105 in gate drive device order and in finishing display panel 101 data of all pixel P write (data-writing).Thus, add (back of the body) light source that backlight module 109 is supplied, then (liquid crystal) display panel 101 will the show image picture.
In this example embodiment, source electrode driving device 103 can receive the control of time schedule controller 107 and drive all pixel P in the display panel 101 with the type of drive of polarity dots counter-rotating (dot inversion), polarity row counter-rotating (column inversion), polarity row counter-rotatings (row inversion) or polarity frame counter-rotating (frame inversion), uses the liquid crystal molecule that prevents each pixel P in (liquid crystal) display panel 101 and produces deteriorated.With this understanding, source electrode driving device 103 can be for using arbitrary type source driver/wafer (sourcedriver/chip) of positive/negative-pressure structure matching direct current common voltage (DC Vcom).
In this, function mode for ease of explanation source electrode driving device 103, Fig. 2 is that the source electrode driving device 103 of Fig. 1 corresponds to two adjacent odd even data line DL_odd in (liquid crystal) display panel 101 and the schematic diagram of DL_even, that is: i bar and i+1 bar data line, i are the odd number positive integer.For instance, the 1st with the 2nd data line, the 3rd and the 4th data line, please the rest may be inferred.
In addition, Fig. 3 is the enforcement schematic diagram of the source electrode driving device 103 of Fig. 2.Please merge and consult Fig. 1~Fig. 3, source electrode driving device 103 comprises: data voltage produces main body (data signal generation mainbody) 201, at positive and negative dual power supply (PAVDD, NAVDD) the output buffer stage under (output bufferstage) 203, Channel Exchange circuit (channel interchanging circuit) 203, and economize electric line (power-saving circuit) 205.
In this example embodiment, data voltage produces main body 201 and receives the control of time schedule controller 107 and produce positive and negative data voltage V+, the V-that corresponds to data line DL_odd and DL_even.Wherein, data voltage produces main body 201 can be by the shift registor that does not show (shift register), data working storage (data register), level shift unit (level shifter) and digital-analog convertor (digital-to-analog converter, ADC) form, but be not restricted to this.
In this, so-called " positive data voltage V+ " is a certain data/GTG (gray level) voltage greater than the direct current common voltage (DC Vcom) of (liquid crystal) display panel 101; In addition, so-called " negative data voltage V-" is a certain data/gray scale voltage less than the direct current common voltage (DC Vcom) of (liquid crystal) display panel 101.
Output buffer stage 203 couples data voltage and produces main body 201, and has at least positive output passage (positive output channel) OUT+ and negative output passage (negative output channel) OUT-.Clearer, output buffer stage 203 comprises at least: impact damper (buffer) Buf1 and Buf2.Wherein, impact damper Buf1 operates under positive supply PAVDD and earthing potential (ground potential, the i.e. zero potential) GND, and corresponds to positive output passage OUT+; In addition, impact damper Buf2 operates under negative supply NAVDD and the earthing potential GND, and corresponds to negative output passage OUT-.
Channel Exchange circuit 205 is coupled between output buffer stage 203 and the province electric line 207, in order to alternately to change the annexation between output channel OUT+, OUT-and data line DL_odd, DL_even based on the cause/demand of reversal of poles.In other words, data line DL_odd can be coupled among output channel OUT+, the OUT-one by Channel Exchange circuit 205; In addition, data line DL_even can be coupled among output channel OUT+, the OUT-one by Channel Exchange circuit 205.
Clearer, Channel Exchange circuit 205 comprises: switch SW 1~SW6.Wherein, the first end of switch SW 1 couples the output (that is, output channel OUT+) of impact damper Buf1.The first end of switch SW 2 couples the second end of switch SW 1, and the second end of switch SW 2 then is coupled to data line DL_odd.The first end of switch SW 3 couples the output (that is, output channel OUT-) of impact damper Buf2.The first end of switch SW 4 couples the second end of switch SW 3, and the second end of switch SW 4 then is coupled to data line DL_even.The first end of switch SW 5 couples the second end of switch SW 1, and the second end of switch SW 5 then is coupled to data line DL_even.The first end of switch SW 6 couples the second end of switch SW 3, and the second end of switch SW 6 then is coupled to data line DL_odd.
Economizing electric line 207 is coupled to via Channel Exchange circuit 205 between output buffer stage 203 and the display panel 101, and it is configured to: in output buffer stage 203 by output channel OUT+, OUT-with before driving data line DL_odd, DL_even, collect from the electric charge (charges) of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even; And output buffer stage 203 by output channel OUT+, OUT-with drive data line DL_odd, DL_even during, adopts collected electric charge and one of them of positive and negative dual power supply PAVDD, NAVDD is carried out (mistake) charge.
Clearer, province's electric line 207 can possess the ability of one among positive and negative dual power supply PAVDD, the NAVDD being carried out (mistake) charging is arranged, and it comprises: switch SW 7~SW14 and striding capacitance (flying capacitor) CF.Wherein, the first end of switch SW 7 couples data line DL_odd.The first end of striding capacitance CF couples the second end of switch SW 7.The first end of switch SW 8 couples the second end of striding capacitance CF, and the second end of switch SW 8 then is coupled to data line DL_even.The first end of switch SW 9 couples data line DL_odd, and the second end of switch SW 9 then is coupled to earthing potential GND.The first end of switch SW 10 couples data line DL_even, and the second end of switch SW 10 then is coupled to earthing potential GND.
The first end of switch SW 11 couples the first end of striding capacitance CF, and the second end of switch SW 11 then is coupled to positive supply PAVDD.The first end of switch SW 12 couples the first end of striding capacitance CF, and the second end of switch SW 12 then is coupled to earthing potential GND.The first end of switch SW 13 couples the second end of striding capacitance CF, and the second end of switch SW 13 then is coupled to earthing potential GND.The first end of switch SW 14 couples the second end of striding capacitance CF, and the second end of switch SW 14 then is coupled to negative supply NAVDD.
Based on above-mentioned, correspond to data line DL_odd and negative output passage OUT-corresponds under the starting condition of data line DL_even at positive output passage OUT+, receive the control of time schedule controller 107, data voltage produces main body 201 and can produce with respect to the positive data voltage V+ of the direct current common voltage (DC Vcom) of (liquid crystal) display panel 101 and negative data voltage V-to data line DL_odd, DL_even.With this understanding, switch SW 1~SW4 meeting conducting, and remaining switch SW 5~SW14 can close.
On the other hand, want to carry out at source electrode driving device 103 to receive the control of time schedule controller 107 under the condition of behavior of reversal of poles, only have the switch SW 7, SW8 can conducting, and remaining switch SW 1~SW6, SW9~SW14 can close.Thus, the striding capacitance CF part negative charge that namely can collect the part positive charge of the equivalent load capacitance CDL_odd that before had been stored in data line DL_odd and before be stored in the equivalent load capacitance CDL_even of data line DL_even.At this moment, in this example embodiment, suppose the pressure reduction (voltage difference) at striding capacitance CF two ends greater than the absolute value of positive supply PAVDD (that is, | PAVDD|) or greater than the absolute value of negative supply NAVDD (that is, | NAVDD|).
Collect behind the electric charge of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even at striding capacitance CF, receive the control of time schedule controller 107, switch SW 9, SW10 meeting conducting are only arranged, and remaining switch SW 1~SW8, SW11~SW14 can close.Thus, residue in the electric charge of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even namely can all be released into ground (that is, earthing potential GND).In other words, this moment, each data line DL_odd, DL_even all corresponded to zero potential (0V).
After the residual charge of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even all is released into ground, then source electrode driving device 103 will carry out the behavior of reversal of poles.With this understanding, suppose the words that this moment, wish was carried out (mistake) charging to positive supply PAVDD, then receive the control of time schedule controller 107, data voltage produces main body 201 and can produce with respect to another positive data voltage V+ of the direct current common voltage (DC Vcom) of (liquid crystal) display panel 101 and another negative data voltage V-to data line DL_even, DL_odd.Base this, switch SW 1, SW3, SW5, SW6, SW11, SW13 can conductings, and remaining switch SW 2, SW4, SW7~SW10, SW12, SW14 can be closed.At this moment, the capacitance coupling effect (capacitance couplingeffect) that causes based on striding capacitance CF, the electric charge that before had been stored in striding capacitance CF can carry out (mistake) charging (that is the level that, is higher than original positive supply PAVDD) to positive supply PAVDD.Hence one can see that, based on behavior/mode that collected electric charge is charged positive supply PAVDD is carried out (mistake), and can be so that source electrode driving device 103 has the mechanism of power saving.
On the other hand, after the residual charge of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even all is released into ground, then source electrode driving device 103 will carry out the behavior of reversal of poles.With this understanding, suppose the words that this moment, wish was carried out (mistake) charging to negative supply NAVDD, then receive the control of time schedule controller 107, data voltage produces main body 201 and can distinctly produce with respect to another positive data voltage V+ of the direct current common voltage (DC Vcom) of (liquid crystal) display panel 101 and another negative data voltage V-to data line DL_even, DL_odd.Base this, switch SW 1, SW3, SW5, SW6, SW12, SW14 can conductings, and remaining switch SW 2, SW4, SW7~SW11, SW13 can be closed.At this moment, based on the capacitance coupling effect that striding capacitance CF causes, the electric charge that before had been stored in striding capacitance CF can carry out (mistake) charging (that is, being lower than the level of original negative supply NAVDD) to negative supply NAVDD.Hence one can see that, based on behavior/mode that collected electric charge is charged negative supply NAVDD is carried out (mistake), and can be so that source electrode driving device 103 has the mechanism of power saving.
On the other hand, Fig. 4 is another enforcement schematic diagram of the source electrode driving device 103 of Fig. 2.Please merge and consult Fig. 3 and Fig. 4, the difference of Fig. 3 and embodiment shown in Figure 4 only is: province's electric line 207 (only) shown in Figure 4 can possess the ability that has couple negative supply NAVDD to carry out (mistake) charging.With this understanding, province's electric line 207 shown in Figure 4 comprises: switch SW 7~SW12 and striding capacitance CF.
As shown in Figure 4, the first end of switch SW 7 couples data line DL_odd.The first end of striding capacitance CF couples the second end of switch SW 7.The first end of switch SW 8 couples the second end of striding capacitance CF, and the second end of switch SW 8 then is coupled to earthing potential GND.The first end of switch SW 9 couples data line DL_odd, and the second end of switch SW 9 then is coupled to earthing potential GND.The first end of switch SW 10 couples data line DL_even, and the second end of switch SW 10 then is coupled to earthing potential GND.The first end of switch SW 11 couples the first end of striding capacitance CF, and the second end of switch SW 11 then is coupled to data line DL_even.The first end of switch SW 12 couples the second end of striding capacitance CF, and the second end of switch SW 12 then is coupled to negative supply NAVDD.
Under embodiment shown in Figure 4, correspond to data line DL_even and negative output passage OUT-corresponds under the starting condition of data line DL_odd at positive output passage OUT+, receive the control of time schedule controller 107, data voltage produces main body 201 and can produce with respect to the positive data voltage V+ of the direct current common voltage (DC Vcom) of display panel 101 and negative data voltage V-to data line DL_even, DL_odd.With this understanding, switch SW 1, SW3, SW5, SW6 can conductings, and remaining switch SW 2, SW4, SW7~SW12 can be closed.
On the other hand, want to carry out at source electrode driving device 103 to react on the control of time schedule controller 107 under the condition of behavior of reversal of poles, only have the switch SW 7, SW8 can conducting, and remaining switch SW 1~SW6, SW9~SW12 can close.Thus, striding capacitance CF namely can collect the part negative charge of the equivalent load capacitance CDL_odd that before had been stored in data line DL_odd.At this moment, in this example embodiment, the pressure reduction of supposing striding capacitance CF two ends be negative supply NAVDD absolute value half (that is, 1/2*|NAVDD|).
Collect behind the electric charge of the equivalent load capacitance CDL_odd of data line DL_odd, to receive the control of time schedule controller 107 at striding capacitance CF, only have the switch SW 9, SW10 can conducting, and remaining switch SW 1~SW8, SW11~SW14 can close.Thus, residue in the electric charge of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even namely can all be released into ground (that is, earthing potential GND).In other words, this moment, each data line DL_odd, DL_even all corresponded to zero potential (0V).
After the residual charge of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even all is released into ground, then source electrode driving device 103 will carry out the behavior of reversal of poles.With this understanding, receive the control of time schedule controller 107, data voltage produces main body 201 and can produce with respect to another positive data voltage V+ of the direct current common voltage (DC Vcom) of (liquid crystal) display panel 101 and another negative data voltage V-to data line DL_even, DL_odd.Base this, switch SW 1~SW4, SW11, SW12 can conductings, and remaining switch SW 7~SW10 can close.At this moment, be 1/2*|NAVDD| based on the previous two ends of striding capacitance CF pressure reduction, therefore only the voltage on the equivalent load capacitance CDL_even of data line DL_even be lower than-during 1/2*|NAVDD|, the electric charge that before had been stored in striding capacitance CF just can carry out (mistake) charging (that is, being lower than the level of original negative supply NAVDD) to negative supply NAVDD.Hence one can see that, based on behavior/mode that collected electric charge is charged negative supply NAVDD is carried out (mistake), and can be so that source electrode driving device 103 has the mechanism of power saving.
On the other hand, Fig. 5 is another enforcement schematic diagram of the source electrode driving device 103 of Fig. 2.Please merge and consult Fig. 3 and Fig. 5, the difference of Fig. 3 and enforcement aspect shown in Figure 5 only is: province's electric line 207 (only) shown in Figure 5 can possess the ability that has couple positive supply PAVDD to carry out (mistake) charging.With this understanding, province's electric line 207 shown in Figure 5 comprises: switch SW 7~SW12 and striding capacitance CF.
As shown in Figure 5, the first end of switch SW 7 couples data line DL_even.The first end of striding capacitance CF couples the second end of switch SW 7.The first end of switch SW 8 couples the second end of striding capacitance CF, and the second end of switch SW 8 then is coupled to earthing potential GND.The first end of switch SW 9 couples data line DL_odd, and the second end of switch SW 9 then is coupled to earthing potential GND.The first end of switch SW 10 couples data line DL_even, and the second end of switch SW 10 then is coupled to earthing potential GND.The first end of switch SW 11 couples the first end of striding capacitance CF, and the second end of switch SW 11 then is coupled to data line DL_odd.The first end of switch SW 12 couples the second end of striding capacitance CF, and the second end of switch SW 12 then is coupled to positive supply PAVDD.
Under embodiment shown in Figure 5, correspond to data line DL_even and negative output passage OUT-corresponds under the starting condition of data line DL_odd at positive output passage OUT+, receive the control of time schedule controller 107, data voltage produces main body 201 and can distinctly produce with respect to the positive data voltage V+ of the direct current common voltage (DC Vcom) of display panel 101 and negative data voltage V-to data line DL_even, DL_odd.With this understanding, switch SW 1, SW3, SW5, SW6 can conductings, and remaining switch SW 2, SW4, SW7~SW12 can be closed.
On the other hand, want to carry out at source electrode driving device 103 to receive the control of time schedule controller 107 under the condition of behavior of reversal of poles, only have the switch SW 7, SW8 can conducting, and remaining switch SW 1~SW6, SW9~SW12 can close.Thus, striding capacitance CF namely can collect the part positive charge of the equivalent load capacitance CDL_even that before had been stored in data line DL_even.At this moment, in this example embodiment, the pressure reduction of supposing striding capacitance CF two ends be positive supply PAVDD absolute value half (that is, 1/2*|PAVDD|).
Collect behind the electric charge of the equivalent load capacitance CDL_even of data line DL_even, to receive the control of time schedule controller 107 at striding capacitance CF, only have the switch SW 9, SW10 can conducting, and remaining switch SW 1~SW8, SW11~SW14 can close.Thus, residue in the electric charge of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even namely can all be released into ground (that is, earthing potential GND).In other words, this moment, each data line DL_odd, DL_even all corresponded to zero potential (0V).
After the residual charge of equivalent load capacitance CDL_odd, the CDL_even of each data line DL_odd, DL_even all is released into ground, then source electrode driving device 103 will carry out the behavior of reversal of poles.With this understanding, receive the control of time schedule controller 107, data voltage produces main body 201 and can produce with respect to another positive data voltage V+ of the direct current common voltage (DC Vcom) of (liquid crystal) display panel 101 and another negative data voltage V-to data line DL_even, DL_odd.Base this, switch SW 1~SW4, SW11, SW12 can conductings, and remaining switch SW 7~SW10 can close.At this moment, be 1/2*|PAVDD| based on the previous two ends of striding capacitance CF pressure reduction, when therefore only the voltage on the equivalent load capacitance CDL_odd of data line DL_odd is higher than 1/2*|PAVDD|, the electric charge that before had been stored in striding capacitance CF just can carry out (mistake) charging (that is the level that, is higher than original positive supply PAVDD) to positive supply PAVDD.Hence one can see that, based on behavior/mode that collected electric charge is charged positive supply PAVDD is carried out (mistake), and can be so that source electrode driving device 103 has the mechanism of power saving.
It is worth mentioning that at this, disclosed three kinds and (that is, be illustrated in distinctly that Fig. 3~Fig. 5), the present invention is not restricted to this with respect to the enforcement aspects of economizing electric line 207 although above-mentioned each example embodiment is clear.In other words, content based on above-mentioned example embodiment institute teaching, other are different from above-mentioned three kinds of any circuit structures with respect to the enforcement aspect of economizing electric line 207 and can replace to be applied in wherein, as long as keep the set running of province's electric line 207.
In sum, in the present invention, before driving each data line of display panel, can be first collect from the electric charge of the equivalent load capacitance of each data line by economizing striding capacitance in the electric line, then again the residual charge of the equivalent load capacitance of each data line is released into ground.On the other hand, during each data line that drives display panel, can utilize collected electric charge to carry out (mistake) charging to one in the positive and negative dual power supply of output buffer stage.Thus, based on collected electric charge to carry out behavior/mode that (mistakes) charges to one in the positive and negative dual power supply of output buffer stage, can be so that source electrode driving device has the mechanism of power saving.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore working as the scope of looking the wish protection of claims institute, protection scope of the present invention is as the criterion.
In addition, arbitrary embodiment of the present invention or protection domain must not reached the disclosed whole purposes of the present invention or advantage or characteristics.In addition, summary part and title only are the usefulness of auxiliary patent document search, are not to limit protection scope of the present invention.