CN102930008A - Vector table looking up method and processor - Google Patents
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Abstract
Provided are a vector table looking up method and a processor. A first multi-time table looking up instruction field is used for marking vector table looking up operation, a second multi-time table looking up instruction field and a third multi-time table looking up instruction field are index numbers of a source operand register, and a fourth multi-time table looking up instruction field is the index number of a target register. The content of the register designated by the second multi-time table looking up instruction field is a query base address, the content of the register designated by the third multi-time table looking up instruction field contains deviation value of a plurality of vector elements to be checked relative to the query base address, and the fourth multi-time table looking up instruction field designates a single target register storing the final query results. A vector table looking up result is spliced according to the splicing format of the content to the register designated by the third multi-time table looking up instruction field and is written into the target register designated by the fourth multi-time table looking up instruction field. The position of the deviation value of the vector elements to be checked in the register designated by the third multi-time table looking up instruction field formulates the final position of corresponding elements in the target register designated by the fourth multi-time table looking up instruction field.
Description
Technical field
The present invention relates to the Computer Design field, more particularly, the present invention relates to a kind of vectorial look-up method and adopted should the vector look-up method processor.
Background technology
Along with the supercomputer development, the vector calculation instruction of single instruction multiple data becomes the gordian technique that improves the system peak performance.But, be subjected to the restriction of port memory, can't Parallel Implementation in the general processor of prior art and the vectorial table-look-up instruction of vector calculation instruction coupling.In fact, in the general processor of prior art, usually by vectorial table lookup operation being split into multi-shift and loading operation is realized.
Specifically, in the general processor of prior art, on average each element corresponding three operations of tabling look-up: off-set value is moved to low level from specific instruction field (DISP_V $); Send common loading instruction (LOAD) and obtain the element Query Result; Query Result is moved to a high position.
In the aforesaid operations process of above-mentioned prior art, the process need that vectorial table lookup operation is realized carries out vector, scalar conversion repeatedly, takies the general-purpose register resource, affects track performance.
Summary of the invention
Technical matters to be solved by this invention is for there being defects in the prior art, provide a kind of and realize method and the processor that quick vector is tabled look-up in common single port or dual-ported memory, in the realization that solves prior art, need repeatedly vector, scalar conversion, take the general-purpose register resource, affect the technical matters of track performance.
According to a first aspect of the invention, a kind of vectorial look-up method is provided, it comprises: repeatedly table-look-up instruction is set, makes described repeatedly table-look-up instruction comprise successively more than first table-look-up instruction field, more than second table-look-up instruction field, more than the 3rd table-look-up instruction field and more than the 4th table-look-up instruction field; And utilize described repeatedly table-look-up instruction to carry out vectorial table lookup operation; Wherein, described more than first table-look-up instruction field is used for indicating vectorial table lookup operation, the content of registers of described more than second table-look-up instruction field appointment is the inquiry base address, second, third repeatedly the table-look-up instruction field be the call number of source operand register, more than the 4th table-look-up instruction field is the call number of destination register; The content of registers of described more than the 3rd table-look-up instruction field appointment comprises the offset segment of a plurality of vector elements to be checked, described more than the 4th table-look-up instruction field represents the target register address of checking result, and wherein, calculate the destination address of each vector element to be checked according to base address and each field offset value; Described more than the 4th table-look-up instruction field specified the single target register of depositing final Query Result.
Preferably, described vectorial look-up method also comprises: the instruction stream at processor is processed in the operating process, and when having extracted described repeatedly table-look-up instruction, processor is interpreted as a plurality of table-look-up instructions with described repeatedly table-look-up instruction.The quantity of a table-look-up instruction equals repeatedly the vector element number to be checked in the table-look-up instruction.
Preferably, in described vectorial look-up method, the element number of vectorial checking result equals the number of the off-set value of vector element to be checked in the destination register; And the finally position in destination register of corresponding element has been stipulated in the position of off-set value in register.
Preferably, in described vectorial look-up method, a described table-look-up instruction comprise successively the first table-look-up instruction fields, the second table-look-up instruction fields, the three table-look-up instruction field, the four table-look-up instruction field and May Day time table-look-up instruction field; Wherein, described the first table-look-up instruction fields are used for indicating single vector table lookup operation; Described second, third table-look-up instruction field is the source operand register; Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction; Described May Day, time table-look-up instruction field was destination register.The content of registers of described the second table-look-up instruction field appointments is the inquiry base address; The content of registers of described the three table-look-up instruction field appointment comprises the offset segment of a plurality of vector elements to be checked, wherein calculates the destination address of each vector element to be checked according to base address and each field offset value; Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction; Described May Day, time table-look-up instruction field was the target register address of checking result, and the single target register of its appointment is deposited final vectorial checking result.
Preferably, in described vectorial look-up method, with one repeatedly the result of table-look-up instruction write back once destination register.
According to a second aspect of the invention, a kind of processor is provided, it utilizes described repeatedly table-look-up instruction to carry out vectorial table lookup operation, wherein, described repeatedly table-look-up instruction comprises more than first table-look-up instruction field, more than second table-look-up instruction field, more than the 3rd table-look-up instruction field and more than the 4th table-look-up instruction field successively; And wherein, described more than first table-look-up instruction field is used for indicating vectorial table lookup operation, the content of registers of described more than second table-look-up instruction field appointment is the inquiry base address, the content of registers of described more than the 3rd table-look-up instruction field appointment comprises the offset segment of a plurality of vector elements to be checked, described more than the 4th table-look-up instruction field represents the target register address of checking result, wherein, calculate the destination address of each vector element to be checked according to base address and each field offset value; The content of registers of described more than the 4th table-look-up instruction field appointment is vectorial checking result.
Preferably, process in the operating process at the instruction stream of processor, when having extracted described repeatedly table-look-up instruction, processor is interpreted as a plurality of table-look-up instructions with described repeatedly table-look-up instruction.The quantity of a table-look-up instruction equals repeatedly the vector element number to be checked in the table-look-up instruction.
Preferably, the element number of vectorial checking result equals the number of the skew segment value of vector element to be checked in the destination register, and the finally position in destination register of corresponding element has been stipulated in the position of off-set value in register.
Preferably, a described table-look-up instruction comprise successively the first table-look-up instruction fields, the second table-look-up instruction fields, the three table-look-up instruction field, the four table-look-up instruction field and May Day time table-look-up instruction field; Wherein, described the first table-look-up instruction fields are used for indicating single vector table lookup operation; Described second, third table-look-up instruction field is the source operand register; Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction; Described May Day, time table-look-up instruction field was destination register.The content of registers of described the second table-look-up instruction field appointments is the inquiry base address; The content of registers of described the three table-look-up instruction field appointment comprises the offset segment of a plurality of vector elements to be checked, wherein calculates the destination address of each vector element to be checked according to base address and each field offset value; Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction; Described May Day, time table-look-up instruction field was the target register address of checking result, and the single target register of its appointment is deposited final vectorial checking result.
Preferably, with one repeatedly the result of table-look-up instruction write back once destination register.
According to the present invention, realize tabling look-up of a plurality of vector elements to be checked by single operation, compared with prior art, each element inquiry all can reduce by two operations, reduced simultaneously the register quantity that takies in the implementation, realized that with less hardware costs efficient vector tables look-up.Thus, the invention provides and a kind ofly realize method and the processor that quick vector is tabled look-up at common single port or dual-ported memory, solve repeatedly vector, the scalar conversion of needs of prior art, taken the general-purpose register resource, affected the technical matters of track performance.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the synoptic diagram according to the vectorial look-up method of the embodiment of the invention.
Fig. 2 schematically shows another synoptic diagram according to the vectorial look-up method of the embodiment of the invention.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
Vectorial look-up method according to the embodiment of the invention comprises:
Repeatedly table-look-up instruction is set, makes described repeatedly table-look-up instruction comprise successively more than first table-look-up instruction field, more than second table-look-up instruction field, more than the 3rd table-look-up instruction field and more than the 4th table-look-up instruction field;
Utilize described repeatedly table-look-up instruction to carry out vectorial table lookup operation.
Wherein, described more than first table-look-up instruction field is used for indicating vectorial table lookup operation, second, third repeatedly the table-look-up instruction field be the call number of source operand register, more than the 4th table-look-up instruction field is the call number of destination register.Specifically, described more than second table-look-up instruction field is the source operand register, the content of registers of its appointment is the inquiry base address, described more than the 3rd table-look-up instruction field is the source operand register, the content of registers of its appointment comprises the offset segment of a plurality of vector elements to be checked (according to base address and each field offset value, can calculate the destination address of each vector element to be checked), the target register address that described more than the 4th table-look-up instruction field is checking result, take out each vector element according to the destination address of each vector element to be checked, write the register of more than the 4th table-look-up instruction field appointment after the splicing.The number of the element number address value of vectorial checking result equals the number of the skew segment value of vector element to be checked in the destination register, and the position of off-set value in register, has stipulated the finally position in destination register of corresponding element.
More than the 4th time the table-look-up instruction field is specified the single target register of depositing final Query Result.Calculate the destination address of each vector element to be checked according to base address and each field offset value, access each destination address and obtain each vector element to be checked, the splicing form of the content of registers of more than the 3rd table-look-up instruction field of reference appointment, be spliced into vectorial checking result, write the destination register of more than the 4th table-look-up instruction field appointment.The finally position in the destination register of more than the 4th table-look-up instruction field appointment of corresponding element has been stipulated in the position of vector element off-set value to be checked in the register of more than the 3rd table-look-up instruction field appointment.
And, preferably, vectorial look-up method according to the embodiment of the invention also comprises: process in the operating process at the instruction stream of processor, when having extracted described repeatedly table-look-up instruction, processor is interpreted as a plurality of table-look-up instructions with described repeatedly table-look-up instruction, and the quantity of a table-look-up instruction equals repeatedly the vector element number to be checked in the table-look-up instruction.
A wherein said table-look-up instruction comprise successively the first table-look-up instruction fields, the second table-look-up instruction fields, the three table-look-up instruction field, the four table-look-up instruction field and May Day time table-look-up instruction field.
Wherein, described the first table-look-up instruction fields are used for indicating single vector table lookup operation;
Described the second table-look-up instruction fields are the source operand register, and the content of registers of its appointment is the inquiry base address;
Described the three table-look-up instruction field is the source operand register, and the content of registers of its appointment comprises the offset segment of a plurality of vector elements to be checked, according to base address and each field offset value, can calculate the destination address of each vector element to be checked;
Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction;
Described May Day, time table-look-up instruction field was the target register address of checking result, took out each vector element according to the destination address of each vector element to be checked, write the register of more than the 4th table-look-up instruction field appointment after the splicing.The corresponding vectorial checking result of the destination address of each vector element to be checked, so the number of vectorial checking result preferably equals the number of the skew segment value of vector element to be checked in the destination register.
Fig. 1 schematically shows the synoptic diagram according to the vectorial look-up method of the embodiment of the invention.
Vectorial look-up method according to the embodiment of the invention comprises:
A) according to the source-register in the instruction number (BADDR $, DISP_V $), the access general-purpose register obtains inquiring about base address and element to be visited (example: 1st, 13,6,26 elements) off-set value (example: a1, a13, a6, a26) in table;
B) inquire about base address and off-set value addition, obtain the storage address of element to be visited;
C) reference-to storage obtains the value (example: d1, d13, d6, d26) of each element;
D) with reference to the splicing form of off-set value among the DISP V $, splice vectorial checking result;
E) vectorial checking result writes the destination register of DEST $ appointment.
Specifically, as shown in Figure 1, in the vectorial look-up method according to the embodiment of the invention, repeatedly the table-look-up instruction formatting is: " more than first table-look-up instruction field of VLUPT() "+" BADDR (more than second table-look-up instruction field) "+" DISP_V (more than the 3rd table-look-up instruction field) "+" DEST (more than the 4th table-look-up instruction field) ", as shown in Figure 1.Wherein:
VLUPT: the operation name is used for indicating once (single) vectorial table lookup operation;
BADDR $: source operand register, its content of registers are the heading address, namely inquire about the base address;
DISP_V $: source operand register, its content of registers is offset field, the skew segment value that wherein comprises a plurality of vector elements to be checked (table element), the number of concrete skew segment value is determined by the vector width of tabling look-up, according to base address and each field offset segment value, can calculate the destination address of each vector element to be checked; Specifically, as shown in Figure 1, for example, address shown in " 0 " in the instruction memory of heading address, a1 represents that interior the 1st vector element to be checked is with respect to the offset address of the address shown in " 0 " in the storer, then by with the offset address addition of the 1st element in the address shown in " 0 " in the storer and the table with respect to the address shown in " 0 " in the storer, then can obtain being offset the specific address of the vector element to be checked of segment value a1 indication.
DEST $: destination register, final vectorial checking result writes this register.The element number of vector checking result equals the number of the off-set value of vector element to be checked; And the finally position in destination register of corresponding element has been stipulated in the position of off-set value in register.Specifically, d1 represents the value of interior the 1st vector element to be checked.As shown in Figure 1, after vectorial table lookup operation finishes, the position of d1 in the specified register of DEST $, and the position consistency of a1 in the specified register of DISP_V $.
Thus, in corresponding hardware design, adopt repeatedly inquiry, once write back the result mode realization, reduce the address resolution expense.
Specifically, process in the operating process at the instruction stream of processor, when having extracted repeatedly table-look-up instruction, processor repeatedly table-look-up instruction is interpreted as a plurality of " table-look-up instructions ", wherein a table-look-up instruction formatting is: " the first table-look-up instruction fields of SELLD() "+" BADDR (the second one time table-look-up instruction field) "+" DISP_V (the three table-look-up instruction field) "+" the four table-look-up instruction field of #c() "+" DEST (time table-look-up instruction field on May Day) ", as shown in Figure 2.Wherein:
SELLD: the operation name indicates one time table lookup operation;
BADDR $: source operand register, its content of registers are the heading address, namely inquire about the base address;
DISP_V $: source operand register, its content of registers is offset field, the skew segment value that wherein comprises a plurality of vector elements to be checked (table element), the number of concrete skew segment value is determined by the vector width of tabling look-up, according to base address and each field offset segment value, can calculate the destination address of each vector element to be checked;
#c: represent the index value (that is, represent this table look-up element be which to be checked vector element in DISP_V $) of this element of tabling look-up (vector element to be checked) skew in DISP_V $; Specifically, as shown in Figure 2, repeatedly the index value of last skew (a26) in DISP_V $ of table-look-up instruction is 0, and " index value 0 " represents last vector element to be checked, " index value 1 " expression penult vector element to be checked, third from the bottom vector element to be checked of " index value 2 " expression, the like;
DEST: destination register, deposit checking result, the number of checking result equals the number of the skew segment value of vector element to be checked.
Each table lookup operation correspondence is fetched an element, is stored in the adhoc buffer; Behind #c traversal index value, all elements in the vectorial table lookup operation all obtains, can be written back in the destination register, and concrete end mark can arrange by specific #c value (for example show the vector end of tabling look-up when #c is 0, can writes back the result).
In addition, in the specific embodiment of the invention, adhoc buffer can be set, adopt repeatedly inquiry, once write back result mode and realize, that is, with one repeatedly the result of table-look-up instruction write back once destination register.More particularly, as shown in Figure 2, one repeatedly last result (d26) all results (d1, d13, d6 etc.) before of table-look-up instruction all temporarily deposit in the impact damper, when confirming to have extracted last result (d26), last result (d26) and result (d1, d13, d6 etc.) are before write back destination register once.
Thus, in the specific embodiment of the invention, reduce the address resolution expense, reduced the general-purpose register resource occupation.Hardware is finished off-set value and Query Result shifting function, and compared with prior art, each element inquiry all can reduce by two operations.
In sum, can find out that above preferred embodiment of the present invention has following useful technique effect at least:
In the general processor of prior art, this operation realizes by displacement and loading operation, on average each element three operations of correspondence of tabling look-up: off-set value is moved to low level from DISP_V $; Send common reprinting instruction LOAD and obtain the element Query Result; Query Result is moved to a high position.On the contrary, the embodiment of the invention realizes tabling look-up of a plurality of vector elements to be checked by single operation, and compared with prior art, each element inquiry all can reduce by two operations, reduced simultaneously the register quantity that takies in the implementation, realized that with less hardware costs efficient vector tables look-up.
According to another preferred embodiment of the invention, the present invention also provides a kind of processor that adopts above-mentioned vectorial look-up method.
Be understandable that although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. vectorial look-up method is characterized in that comprising:
Repeatedly table-look-up instruction is set, makes described repeatedly table-look-up instruction comprise successively more than first table-look-up instruction field, more than second table-look-up instruction field, more than the 3rd table-look-up instruction field and more than the 4th table-look-up instruction field; And
Utilize described repeatedly table-look-up instruction to carry out vectorial table lookup operation;
Wherein, described more than first table-look-up instruction field is used for indicating vectorial table lookup operation, described second, third repeatedly the table-look-up instruction field be the call number of source operand register, more than the 4th table-look-up instruction field is the call number of destination register; The content of registers of described more than second table-look-up instruction field appointment is the inquiry base address, the content of registers of described more than the 3rd table-look-up instruction field appointment comprises the offset segment of a plurality of vector elements to be checked, described more than the 4th table-look-up instruction field specified the single target register of depositing final Query Result
And wherein, calculate the destination address of each vector element to be checked according to base address and each field offset value; The access destination address obtains each vector element to be checked; With reference to the splicing form of each field offset value, each vector element of finding is spliced into vectorial checking result; The corresponding vector element of finding of each off-set value, the finally position in the destination register of more than the 4th table-look-up instruction field appointment of corresponding element has been stipulated in the position of off-set value in the register of more than the 3rd table-look-up instruction field appointment.
2. vectorial look-up method according to claim 1 characterized by further comprising: the instruction stream at processor is processed in the operating process, and when having extracted described repeatedly table-look-up instruction, processor is interpreted as a plurality of table-look-up instructions with described repeatedly table-look-up instruction; The quantity of a table-look-up instruction equals repeatedly the vector element number to be checked in the table-look-up instruction.
3. vectorial look-up method according to claim 2 is characterized in that, after vector was tabled look-up and finished, the element number of vectorial checking result equaled the number of the skew segment value of vector element to be checked in the destination register; And the finally position in destination register of corresponding element has been stipulated in the position of off-set value in register.
4. vectorial look-up method according to claim 2, it is characterized in that, a described table-look-up instruction comprise successively the first table-look-up instruction fields, the second table-look-up instruction fields, the three table-look-up instruction field, the four table-look-up instruction field and May Day time table-look-up instruction field;
Wherein, described the first table-look-up instruction fields are used for indicating single vector table lookup operation; Described second, third table-look-up instruction field is the source operand register; Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction; Described May Day, time table-look-up instruction field was destination register; The content of registers of described the second table-look-up instruction field appointments is the inquiry base address; The content of registers of described the three table-look-up instruction field appointment comprises the offset segment of a plurality of vector elements to be checked, wherein calculates the destination address of each vector element to be checked according to base address and each field offset value; Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction; Described May Day, time table-look-up instruction field was the target register address of checking result, and the single target register of its appointment is deposited final vectorial checking result.
5. according to claim 1 to one of 4 described vectorial look-up methods, it is characterized in that, wherein with one repeatedly the result of table-look-up instruction write back once destination register.
6. processor, it is characterized in that utilizing described repeatedly table-look-up instruction to carry out vectorial table lookup operation, wherein, described repeatedly table-look-up instruction comprises more than first table-look-up instruction field, more than second table-look-up instruction field, more than the 3rd table-look-up instruction field and more than the 4th table-look-up instruction field successively;
And wherein, described more than first table-look-up instruction field is used for indicating vectorial table lookup operation, the content of registers of described more than second table-look-up instruction field appointment is the inquiry base address, the content of registers of described more than the 3rd table-look-up instruction field appointment comprises the offset segment of a plurality of vector elements to be checked, described more than the 4th table-look-up instruction field represents the target register address of checking result, wherein, calculate the destination address of each vector element to be checked according to base address and each field offset value; After vectorial table lookup operation finished, the content of registers of described more than the 4th table-look-up instruction field appointment was vectorial checking result.
7. processor according to claim 6 is characterized in that, processes in the operating process at the instruction stream of processor, and when having extracted described repeatedly table-look-up instruction, processor is interpreted as a plurality of table-look-up instructions with described repeatedly table-look-up instruction; The quantity of a table-look-up instruction equals repeatedly the vector element number to be checked in the table-look-up instruction.
8. processor according to claim 7, it is characterized in that, the element number of vectorial checking result equals the number of the skew segment value of vector element to be checked in the destination register, and the finally position in destination register of corresponding element has been stipulated in the position of off-set value in register.
9. processor according to claim 7, it is characterized in that, a described table-look-up instruction comprise successively the first table-look-up instruction fields, the second table-look-up instruction fields, the three table-look-up instruction field, the four table-look-up instruction field and May Day time table-look-up instruction field;
Wherein, described the first table-look-up instruction fields are used for indicating single vector table lookup operation; Described second, third table-look-up instruction field is the source operand register; Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction; Described May Day, time table-look-up instruction field was destination register; The content of registers of described the second table-look-up instruction field appointments is the inquiry base address; The content of registers of described the three table-look-up instruction field appointment comprises the offset segment of a plurality of vector elements to be checked, wherein calculates the destination address of each vector element to be checked according to base address and each field offset value; Described the four table-look-up instruction field is the index value of this vector element offset segment to be checked in described repeatedly table-look-up instruction; Described May Day, time table-look-up instruction field was the target register address of checking result, and the single target register of its appointment is deposited final vectorial checking result.
10. according to claim 6 to one of 9 described processors, it is characterized in that, wherein with one repeatedly the result of table-look-up instruction write back once destination register.
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| WO2014187348A1 (en) * | 2013-08-23 | 2014-11-27 | 中兴通讯股份有限公司 | Method and device for packet processing |
| CN109814926A (en) * | 2018-12-28 | 2019-05-28 | 东软集团股份有限公司 | A kind of method and apparatus for extracting data |
| CN111813447A (en) * | 2019-04-12 | 2020-10-23 | 杭州中天微系统有限公司 | Processing method and processing device for data splicing instruction |
| CN115951937A (en) * | 2023-03-10 | 2023-04-11 | 北京微核芯科技有限公司 | Vector instruction form filling and table looking-up method and device in processor and electronic equipment |
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| CN1672128A (en) * | 2002-07-26 | 2005-09-21 | 皇家飞利浦电子股份有限公司 | Method and apparatus for accessing multiple vector elements in parallel |
| US7366873B1 (en) * | 2003-08-18 | 2008-04-29 | Cray, Inc. | Indirectly addressed vector load-operate-store method and apparatus |
| CN102629191A (en) * | 2011-04-25 | 2012-08-08 | 中国电子科技集团公司第三十八研究所 | Digital signal processor addressing method |
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