CN102923636B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN102923636B CN102923636B CN201210425466.7A CN201210425466A CN102923636B CN 102923636 B CN102923636 B CN 102923636B CN 201210425466 A CN201210425466 A CN 201210425466A CN 102923636 B CN102923636 B CN 102923636B
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Abstract
The invention provides a kind of semiconductor structure and preparation method thereof.Semiconductor structure provided by the present invention comprises substrate and is formed at described suprabasil dielectric layer; described dielectric layer comprises the first medium being positioned at first area and the second medium being positioned at second area; described first medium surrounds described second medium and connects with described second medium and form the interface that connects, and is formed with boundary belt in described first medium and/or described second medium.Owing to being formed with boundary belt in medium; boundary belt can discharge and eliminate medium at the stress of near interface that connects; preventing first medium and second medium from occurring the phenomenon peeled off, break or rupture in the interface that connects, solving the problem that the MEMS assembly based on above-mentioned semiconductor structure breaks down because there is above-mentioned phenomenon.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of semiconductor structure and preparation method thereof.
Background technology
Semiconductor refers to that resistivity has a material of negative temperature-coefficient of electrical resistance between metal and insulator.Semiconductor technology is material with semiconductor, is made into the technology of assembly and integrated circuit.The processing procedure of semiconductor is similar to builds a house, and is divided into plurality of layers, from bottom to top successively forms according to blueprint layout is repeatedly long-pending, the material that every one deck is had nothing in common with each other and function.
Semiconductor devices usually needs two kinds of different mediums to be produced on together to form some ad hoc structure in manufacturing process, and will inevitably form the interface that connects when two kinds of different mediums are produced on together.Because the physical property of different medium is usually different, the stress that medium corresponding to the both sides at the interface that connects can bear is different.Existing way is produced on by direct for two media smooth engagement to be formed together to connect interface, and this thus obtained semiconductor structure easily occurs peeling off (peeling) at the medium of the near interface that connects, break or the problem such as fracture.
Microelectric technique is based upon with integrated circuit the high-new electronic technology on the various semiconductor devices bases being core.MEMS (Micro-Electro-MechanicalSystems, MEMS) be a kind of industrial technology microelectric technique and mechanical engineering are fused together, MEMS is a large amount of for safe automobile air bag at first, then be widely applied the every field at automobile with the form of sensor, along with further developing of MEMS technology, small size high performance MEMS product growth trend is swift and violent, currently include collection micro mechanism, microsensor, micro actuator and signal transacting and control circuit, until interface, communication and power supply etc. are in microdevice integrally or system, at consumer electronics, also there is the figure of MEMS product in a large number in the fields such as medical treatment.
MEMS assembly is set up based on semiconductor structure, once there is the situation that above-mentioned semiconductor structure is peeled off (peeling) at the medium of the near interface that connects, broken or rupture, whole MEMS just may break down, and causes scrapping of product.
Summary of the invention
For this reason, inventor provide the problem that peeling off, breaking or rupture easily appears with the medium solving in existing semiconductor structure two kinds of different mediums and be produced on the near interface that connects formed together in a kind of semiconductor structure and preparation method thereof, and together solve the problem that the MEMS assembly based on above-mentioned semiconductor structure breaks down because of the problems referred to above.
For solving the problem, a kind of semiconductor structure provided by the invention, comprising:
Substrate;
Be formed at described suprabasil dielectric layer, described dielectric layer comprises the first medium being positioned at first area and the second medium being positioned at second area, and described first medium surrounds described second medium and connects with described second medium and form the interface that connects;
Boundary belt is formed in described first medium and/or described second medium.
Optionally, described boundary belt is 1 ~ 40 μm with the described distance connected between interface.
Optionally, described boundary belt is 5 ~ 20 μm with the described distance connected between interface.
Optionally, the boundary belt be formed in described first medium is made up of the material of described second medium, and the boundary belt be formed in described second medium is made up of the material of described first medium.
Optionally, the width of described boundary belt is 1 ~ 20 μm.
Optionally, the width of described boundary belt is 5 ~ 20 μm.
Optionally, described boundary belt first place connects, and forms protection ring.
Optionally, each limit of described boundary belt is linear, wave is linear, sawtooth is linear or irregular linear.
Optionally, described first medium and described second medium are the one in silica and carbon-based material, and both are not identical.
Optionally, described carbon-based material is carbon (C), photoresist (PR) or polymer (polymer).
Optionally, described first area is circular, oval or polygon, and described second area is circular, oval or polygon.
Optionally, described semiconductor structure is MEMS assembly.
Present invention also offers a kind of preparation method of semiconductor structure, comprising:
Substrate forms first medium;
Utilize photoetching, lithographic technique, in first medium, form hole and surround at least one groove in described hole;
Fill second medium in described hole and described groove.
Optionally, in described photoetching, etching, the groove of formation is twice.
Optionally, the width of described groove is 1 ~ 20 μm.
Optionally, the distance between described hole and described groove is 1 ~ 40 μm.
Optionally, described first medium and described second medium are the one in silica and carbon-based material, and both are not identical.
Optionally, described carbon-based material is carbon (C), photoresist (PR) or polymer (polymer).Compared with prior art, the present invention has the following advantages:
1. owing to setting up boundary belt in medium; can discharge and eliminate medium at the stress of near interface that connects; solve the stripping that medium easily appears in the two media semiconductor structure be produced on together, the problem of breaking or rupturing, and together solve the problem that the MEMS assembly based on described semiconductor structure breaks down because of described problem.
2., in possibility of the present invention, in first medium and second medium, form boundary belt simultaneously, like this, can discharge simultaneously and eliminate two media interior internal stress separately, semiconductor structure is better protected.And the boundary belt be formed in described first medium is made up of the material of described second medium, the boundary belt be formed in described second medium is made up of the material of described first medium.Like this, in manufacturing process, do not need other additional process can obtain corresponding boundary belt, technique makes simple.
3. in possibility of the present invention; formed wave linear, sawtooth is linear or irregular linear boundary belt in medium; the boundary belt of these shapes adds very Da I Member length than common linear boundary belt; like this; just there is the boundary belt of larger lengths for discharging and eliminate the internal stress of medium, make protected effect better.
Accompanying drawing explanation
Fig. 1 is the schematic diagram in each region of semiconductor structure;
Fig. 2 is the regional area schematic diagram with the semiconductor structure in Fig. 1 of existing method making;
Fig. 3 is the cut-away view that the semiconductor structure in Fig. 2 cuts along A-A line;
Fig. 4 is the regional area schematic diagram of the semiconductor structure of first embodiment of the invention;
Fig. 5 is the cut-away view that the semiconductor structure in Fig. 4 cuts along B-B line;
Fig. 6 is the regional area schematic diagram of the semiconductor structure of second embodiment of the invention;
Fig. 7 is the schematic flow sheet of the preparation method of semiconductor structure of the present invention.
1-first area 2-second area 3-regional area
4-first medium 41-boundary belt 5-second medium 51,52-boundary belt
6-connects interface 7-substrate
Detailed description of the invention
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail below to the specific embodiment of the present invention.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public detailed description of the invention.
Please refer to Fig. 1, Fig. 1 is each area schematic of semiconductor structure.In Fig. 1, first area 1 and second area 2 are rectangular area, and first area 1 surrounds second area 2.First area 1 and second area 2 is follow-up will be formed with different media respectively, because first area 1 surrounds second area 2, thus can be connected together at follow-up formed two kinds of different media.Definition regional area 3 is a part for first area 1 and second area 2, as shown in the rectangular broken line frame in Fig. 1.
It should be noted that; first area 1 and second area 2 are not defined as rectangle; namely first area 1 and second area 2 can also be circle, ellipse or other polygon etc.; other shape any can form corresponding two media and be produced on semiconductor structure together, thus also falls within protection scope of the present invention.
Please refer to Fig. 2, Fig. 2 be regional area 3(as shown in Figure 1) in existing two media be produced on semiconductor structure schematic diagram together.Mention first area 1 above and second area 2 is formed with different media respectively, can specifically find out from Fig. 2, being formed in first area 1 is first medium 4, and what be formed at second area 2 is second medium 5.Further, first medium 4 and second medium 5 are connected together formation and connect interface 6.
Please refer to Fig. 3, Fig. 3 is the cut-away view that the semiconductor structure in Fig. 2 cuts along A-A line.Upper as can be seen from Fig. 3, first medium 4 and second medium 5 are all formed at above substrate 7, and the place that first medium 4 connects with second medium 5 forms the interface 6 that connects.Substrate 7 can be the substrate of germanium, silicon or its composition, also can be the substrate being formed with multilayer interconnect structure or other structure.
Existing two media as shown in Figures 2 and 3 does semiconductor structure together, wherein first medium 4 and second medium 5 directly smoothly to connect interface 6 in conjunction with formation, in the phenomenon that peeling off between two media, breaking or rupturing very easily appears in interface 6 place that connects.
Inventor finds, occurs above-mentioned stripping, to break or the reason of phenomenon of rupture is that the physical property of two media is different, the thermal coefficient of expansion of such as two media, particle (atom or molecule) polarity, the varying in size of internal stress that can bear.The difference of these physical propertys causes the two media directly smoothly combined that concentrating of stress very easily occurs in the interface that connects that they are formed, and once stress concentrates the size having exceeded the internal stress that medium can bear, the phenomenon that the corresponding medium of the near interface that connects just there will be stripping, breaks or rupture.Such as be produced on carbon together and silica (as silica), because their physical property is different, after the formation that completes connects interface, they are different in both sides, the interface internal stress separately that connects.The interfacial stress of carbon is comparatively large, and the carbon that thus there will be the near interface that connects peels off serious situation, thus causes the MEMS assembly applying this semiconductor structure to break down in manufacturing process further.
Inventor concentrates on studies and provides a kind of semiconductor structure to solve the problem.
Inventor draws, for the problems referred to above, can take to arrange boundary belt within distance connects any side of interface certain distance or the medium of both sides and solve.The physical property of the medium at the physical property of this boundary belt and its place adapts, and similar or identical with the physical property of another medium.Like this, this boundary belt neither affects its place medium, can absorb again the internal stress of its place medium, and then effectively can prevent the concentrated of near interface interfacial stress that connect, and reaches the effect of release and elimination interfacial stress.Thus; set up the problem that peeling off, breaking or rupture easily appears in medium that this boundary belt can solve the above-mentioned near interface both sides that connect, also solve MEMS assembly based on this semiconductor structure because the medium problem that occurs stripping, break or rupture and break down simultaneously.Technique scheme of the present invention is applicable in semiconductor structure, and a level is taken up an official post the situation of stress between what two kinds of different medium longitudinal handing-over interface.
Please refer to Fig. 4, Fig. 4 is the semiconductor structure schematic diagram that the two media of first embodiment of the invention in regional area 3 is produced on together.As shown in Figure 4, still the interface 6 that connects is formed between first medium 4 with second medium 5.In the present embodiment; because the stress between first medium 4, second medium 5 does not mate, the words directly connected can cause the instability of device, even there will be the phenomenons such as above-mentioned stripping, fracture; thus, the present invention sets up boundary belt to do buffering, the absorption of stress at the near interface that connects.In the present embodiment, be set up boundary belt 51 in second medium 5.Wherein the physical property of boundary belt 51 and the physical property of second medium 5 adapt, and similar or identical with the physical property of first medium 4.Like this, due to the existence of boundary belt 51, can effectively discharge and eliminate the stress near the interface 6 that connects, prevent the phenomenon peeled off, break or rupture.Preferably; the present embodiment boundary belt 51 is made up of the material of first medium; the manufacture craft of boundary belt 51 can be made like this to become simple; do not need to increase additional technique; only need just to form this boundary belt 51 in the process making whole semiconductor structure, and in the semiconductor structure formed, boundary belt 51 discharges and eliminates the effective of internal stress simultaneously.
Please refer to Fig. 5, Fig. 5 is the cut-away view that the semiconductor structure in Fig. 4 cuts along B-B line.As shown in Figure 5, first medium 4 and second medium 5 are all formed at above substrate 7, and form the interface 6 that connects between first medium 4 with second medium 5.Meanwhile, boundary belt 51 is formed in second medium 5, and along stretching near the whole interface 6 that connects.Boundary belt 51 linearly shape in the present embodiment, is thus parallel to each other with the rectilinear interface 6 that connects.And boundary belt 51 is formed at apart from connecting the place of distance between 1 ~ 40 μm, interface 6, and this distance range is the scope of second medium 5 stress concentration, and boundary belt 51 is formed in the internal stress that can effectively discharge and eliminate second medium 5 in this segment distance.Being more preferably, is that the internal stress of the local second medium 5 of 5 ~ 20 μm is the most concentrated at the distance interface 6 that connects, thus, when being produced on by boundary belt 51 between this distance, to release with to eliminate the action effect of internal stress better.Consider the effect of absorption internal stress and the requirement of technique of boundary belt 51; the width of boundary belt 51 can at 1 ~ 20 μm, and when this width, boundary belt 51 can either play the effect discharging and eliminate stress; do not affect second medium 5 again, and technique also easily makes.Preferably, the width of boundary belt 51 is 5 ~ 20 μm.
It should be noted that, though not shown in figure, but boundary belt 51 is entirely centered around near the interface 6 that connects.If connected, interface 6 is closed shape, and so boundary belt 51 also can correspondingly connect around whole 6 to the first place, interface that connects, and forms protection ring.
Please refer to Fig. 6, Fig. 6 is the semiconductor structure schematic diagram that the two media of second embodiment of the invention in regional area 3 is produced on together.As shown in Figure 6, except being produced on first medium 4 together and second medium 5 and the interface 6 that connects that formed between them, in this semiconductor structure, in first medium 4, being also provided with boundary belt 41, in second medium 5, being also provided with boundary belt 52.Wherein preferred; the boundary belt 41 be formed in first medium 4 is made up of the material of second medium 5; the boundary belt 52 be formed in second medium 5 is made up of the material of first medium 4; technique can be made like this to make more simple; additional process can not be needed just to complete corresponding semiconductor structure, and boundary belt release and eliminate the effective of internal stress in the semiconductor structure formed.
The present embodiment is identical with principle major part with the structure of the first embodiment, and same section please refer to embodiment one.The present embodiment and the first embodiment difference are, the present embodiment arranges boundary belt simultaneously in first medium 4 and second medium 5, and set boundary belt 41 and boundary belt 52 are zigzag.In first medium 4 and second medium 5, arrange boundary belt makes the internal stress of two media inside all be discharged and eliminate simultaneously, prevents two media from occurring the phenomenon peeled off, break or rupture.And the boundary belt length that makes of zigzag boundary belt increases; in extension around when the whole interface 6 that connects; zigzag boundary belt adds very Da I Member length than the linear boundary belt in embodiment one; like this; just have the boundary belt of larger lengths for discharging and eliminate the internal stress of medium, protected effect is better.
It should be noted that; except zigzag, the shape of boundary belt can also be waveform or other is irregular linear, and these shapes make the length of boundary belt increase equally; protected effect is better, and thus the boundary belt of these shapes all belongs to the scope that the present invention protects.
It should be noted that, in the present embodiment, first medium 4 can be wherein a kind of in silica and carbon-based material, second medium 5 is correspondingly another in silica and carbon-based material, this carbon-based material can be carbon (C), photoresist (PR) or polymer (polymer) etc., and first medium 4 is different with second medium 5, is not namely identical material.Known, the present invention does not limit first medium 4 and second medium 5 is specific materials, as long as two kinds of unlike materials are produced on and will form the interface that connects together, can utilize the solution of the present invention to process the stress problem at interface of connecting.As a kind of specific embodiment, when first medium 4 is carbon medium, when second medium 5 is silica medium, preferably, boundary belt 41 is made up of silica material, and boundary belt 52 is made up of material with carbon element.Like this, above-mentioned carbon is peeled off serious situation at the near interface that connects that carbon and silica are formed and just can effectively be solved, and in whole semiconductor structure, carbon is together with silica stable bond.
Present invention also offers two media and be produced on the preparation method being formed together and have the semiconductor structure of boundary belt, please refer to Fig. 7, the method is specific as follows:
First in substrate, form first medium, by physical vaporous depositions such as magnetron sputterings, target as sputter can be formed first medium in substrate.
Then utilize photoetching, lithographic technique, in first medium, form hole and surround at least one groove in described hole.Particularly, first on above-mentioned first medium, form photoresist, then carry out exposing, developing and remove appropriate section photoresist formation photo etched mask, obtain the first medium being formed with given shape photo etched mask.Again the first medium that this is formed with given shape photo etched mask is etched afterwards, with in first medium etching formed porose together with at least groove.Dry etching can be utilized such as to utilize the dry etching modes such as plasma etching (PlasmaEtching), high pressure plasma etching, high density plasma etch to etch, also can utilize wet etching, such as, utilize solution to carry out wet etching.
Finally fill second medium in described hole and described groove.Can select after completing the etching to first medium layer, and before also photo etched mask not being removed, fill second medium in described hole and described groove, finally just photo etched mask is removed.Also can select after eliminating the photo etched mask on first medium, finally carry out fill process and second medium is filled in described hole and described groove.Concrete filling mode also can utilize the mode of magnetron sputtering to carry out, and this technology be well known to those skilled in the art does not repeat them here.
In above-mentioned photoetching, etching, preferably, in first medium, form groove described in twice.Like this; through filling second medium in groove described in the twice formed; just can be formed in the structure having a boundary belt in described first medium and second medium respectively, make the semiconductor structure obtained have better protective effect, not easily occur the phenomenon peeled off, break or rupture.
In above-mentioned photoetching, etching, the distance between the described hole of formation and described groove is at 1 ~ 40 μm.The reason selecting this distance as previously mentioned, is because this distance range stress concentration, makes boundary belt and can discharge corresponding internal stress after this distance range arranges groove.Further preferably, the distance between the described hole of formation and described groove is 5 ~ 20 μm.Reason is same to be mentioned above, and this distance range internal stress is the most concentrated, arranges the latter made boundary belt release of groove and to eliminate the effect of corresponding internal stress better at this distance range.
In above-mentioned photoetching, etching, the width of the described groove of formation is 1 ~ 20 μm.Groove is arranged to this width on the one hand it is considered that whether technique easily realizes, consider on the other hand to impact medium itself, consider, suitable width is 1 ~ 20 μm.Preferred further, the width of the described groove of formation is 5 ~ 20 μm.
In above-mentioned photoetching, etching, described first medium can be the one in silica and carbon-based material, described second medium can be another in silica and carbon-based material, and this carbon-based material can be carbon (C), photoresist (PR) or polymer (polymer) etc.When first medium carbon, accordingly, second medium can be silica, and like this, preferably, the boundary belt in first medium can be made for silica, and the boundary belt in second medium can be carbon, in above-mentioned manufacturing process, just can obtain whole semiconductor structure.
The foregoing is only specific embodiments of the invention; object is to make those skilled in the art better understand spirit of the present invention; but protection scope of the present invention not with the specific descriptions of this specific embodiment for limited range; any those skilled in the art without departing from the spirit of the scope of the invention; can make an amendment specific embodiments of the invention, and not depart from protection scope of the present invention.
Claims (15)
1. a semiconductor structure, is characterized in that, comprising:
Substrate;
Be formed at described suprabasil dielectric layer, described dielectric layer comprises the first medium being positioned at first area and the second medium being positioned at second area, and described first medium surrounds described second medium and connects with described second medium and form the interface that connects;
Boundary belt is formed in described first medium and/or described second medium;
Described boundary belt is 1 ~ 40 μm with the described distance connected between interface;
The boundary belt be formed in described first medium is made up of the material of described second medium, and the boundary belt be formed in described second medium is made up of the material of described first medium.
2. semiconductor structure as claimed in claim 1, it is characterized in that, described boundary belt is 5 ~ 20 μm with the described distance connected between interface.
3. semiconductor structure as claimed in claim 1, it is characterized in that, the width of described boundary belt is 1 ~ 20 μm.
4. semiconductor structure as claimed in claim 1, it is characterized in that, the width of described boundary belt is 5 ~ 20 μm.
5. semiconductor structure as claimed in claim 1, it is characterized in that, described boundary belt is end to end, forms protection ring.
6. semiconductor structure as claimed in claim 1, is characterized in that, each limit of described boundary belt is linear, wave is linear, sawtooth is linear or irregular linear.
7. semiconductor structure as claimed in claim 1, it is characterized in that, described first medium and described second medium are the one in silica and carbon-based material, and both are not identical.
8. semiconductor structure as claimed in claim 7, it is characterized in that, described carbon-based material is carbon, photoresist or polymer.
9. semiconductor structure as claimed in claim 1, is characterized in that, described first area is circular, oval or polygon, and described second area is circular, oval or polygon.
10. semiconductor structure as claimed in claim 1, it is characterized in that, described semiconductor structure is MEMS assembly.
The preparation method of 11. 1 kinds of semiconductor structures, is characterized in that, comprising:
Substrate forms first medium;
Utilize photoetching, lithographic technique, in first medium, form hole and surround at least one groove in described hole;
Fill second medium in described hole and described groove;
Distance between described hole and described groove is 1 ~ 40 μm.
The preparation method of 12. semiconductor structures as claimed in claim 11, is characterized in that, in described photoetching, etching, the groove of formation is twice.
The preparation method of 13. semiconductor structures as claimed in claim 12, is characterized in that, the width of described groove is 1 ~ 20 μm.
The preparation method of 14. semiconductor structures as claimed in claim 11, it is characterized in that, described first medium and described second medium are the one in silica and carbon-based material, and both are not identical.
The preparation method of 15. semiconductor structures as claimed in claim 14, it is characterized in that, described carbon-based material is carbon, photoresist or polymer.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1713349A (en) * | 2004-06-15 | 2005-12-28 | 中国科学院半导体研究所 | Production of silicon-base III family nitride thin-membrane without crack from self-adaption flexible layer |
| CN101154652A (en) * | 2006-09-30 | 2008-04-02 | 海力士半导体有限公司 | Stack package and method for manufacturing the same |
| JP4197799B2 (en) * | 1999-06-02 | 2008-12-17 | 株式会社リコー | Diffraction grating type polarization element |
| CN101640190A (en) * | 2008-07-29 | 2010-02-03 | 台湾积体电路制造股份有限公司 | Structure for reducing integrated circuit corner peeling |
| CN101764082A (en) * | 2008-12-25 | 2010-06-30 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnecting line forming method |
| CN102201361A (en) * | 2010-03-25 | 2011-09-28 | 上海宏力半导体制造有限公司 | Method for reducing dislocation effectively and semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0668423A (en) * | 1992-08-19 | 1994-03-11 | Japan Energy Corp | Thin-film magnetic head |
| US20070102792A1 (en) * | 2005-11-07 | 2007-05-10 | Ping-Chang Wu | Multi-layer crack stop structure |
-
2012
- 2012-10-30 CN CN201210425466.7A patent/CN102923636B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4197799B2 (en) * | 1999-06-02 | 2008-12-17 | 株式会社リコー | Diffraction grating type polarization element |
| CN1713349A (en) * | 2004-06-15 | 2005-12-28 | 中国科学院半导体研究所 | Production of silicon-base III family nitride thin-membrane without crack from self-adaption flexible layer |
| CN101154652A (en) * | 2006-09-30 | 2008-04-02 | 海力士半导体有限公司 | Stack package and method for manufacturing the same |
| CN101640190A (en) * | 2008-07-29 | 2010-02-03 | 台湾积体电路制造股份有限公司 | Structure for reducing integrated circuit corner peeling |
| CN101764082A (en) * | 2008-12-25 | 2010-06-30 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnecting line forming method |
| CN102201361A (en) * | 2010-03-25 | 2011-09-28 | 上海宏力半导体制造有限公司 | Method for reducing dislocation effectively and semiconductor device |
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Effective date of registration: 20230217 Address after: 201203 501b, building 5, No. 3000, Longdong Avenue, Pudong New Area, Shanghai Patentee after: LEXVU OPTO MICROELECTRONICS TECHNOLOGY (SHANGHAI) Ltd. Address before: 323000 room 307, block B, building 1, No.268 Shiniu Road, nanmingshan street, Liandu District, Lishui City, Zhejiang Province Patentee before: Zhejiang Core Microelectronics Co.,Ltd. |
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Effective date of registration: 20230613 Address after: 323000 room 307, block B, building 1, No.268 Shiniu Road, nanmingshan street, Liandu District, Lishui City, Zhejiang Province Patentee after: Zhejiang Core Microelectronics Co.,Ltd. Address before: 201203 501b, building 5, No. 3000, Longdong Avenue, Pudong New Area, Shanghai Patentee before: LEXVU OPTO MICROELECTRONICS TECHNOLOGY (SHANGHAI) Ltd. |
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