CN102915293B - Method for multiplexing hardware resource in system architecture in SOC (system on a chip) - Google Patents
Method for multiplexing hardware resource in system architecture in SOC (system on a chip) Download PDFInfo
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- CN102915293B CN102915293B CN201210314998.3A CN201210314998A CN102915293B CN 102915293 B CN102915293 B CN 102915293B CN 201210314998 A CN201210314998 A CN 201210314998A CN 102915293 B CN102915293 B CN 102915293B
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Abstract
The invention relates to a method for multiplexing hardware resources in a system architecture in an SOC (system on a chip). The method comprises the following steps that: when an SOC memory system architecture can already meet the application requirements in I-cache, an ICCM which is originally used as a code space is completely combined into a space of a DCCM of a data system; when the SOC memory system architecture can already meet the application requirements in D-cache, the DCCM which is originally used as a data space is completely combined to the space of the ICCM of an instruction system; and when the SOC memory system architecture can already meet the application requirements in I-cache and D-cache, the address spaces of the ICCM and the DCCM can be completely butted with an RAM (random access memory) in a Memory controller through control signals, and the addresses are continuous. The method has the beneficial effects that through the steps, internal hardware resources are flexibly adjusted to better meet the requirements on the application of the system, and a multiplexable system architecture adjusting mechanism is provided; and with the adoption of the system architecture adjusting mechanism, the waste of internal resources inside a CPU (central processing unit) is reduced, and the system resources can be utilized more effectively.
Description
Technical field
The present invention relates to SOC integrated circuit (IC) design field, the multiplexing method of the hardware resource in the system architecture mainly in a kind of SOC.
Background technology
SOC related chip in the market gets more and more, it is fiercer to compete, market is also more changeable, the demand of user is also different, the producer of SOC design is when definition chip requires, all pursuing when reducing chip cost, meet more user's request, based on this point, require that designer has better been beneficial to the hardware resource (expansion of internal resource of SOC inside, the increase of corresponding is chip cost), the construction characteristic of the processor utilizing SOC embedded, makes the chip better meeting the market demand.
The memory resource of SOC generally comprises: ROM, RAM, SDRAM, flash etc.
From the mechanism of system, if it is mutual that these storage unit realize with CPU by cache mechanism, the operation of 1 or several cache-line during the operation of the renewal correspondence of each cache, the speed of bus also can limit speed mutual between CPU.
In these memory cells, ROM (being merely able to read), the read or write speed of RAM is the highest, the speed of SDRAM and flash all wants slow, so the code higher to rate request is placed in ROM or RAM (ICCM) time user uses, ROM just secures when chip production, user make based on chip develop in can not revise, the program inside ROM can only be called.Data put other storage unit such as flash or RAM on the system bus, and the speed that CPU operates it is slower.
The framework that cordis5+ processor is provides the fast access passage of a kind of data and program, access program (RAM or ROM is as program's memory space) and data (RAM is as data space) can be delivered on the streamline of CPU within a clock period. corresponding code and the position of data respectively in ICCM and DCCM, the data interaction that can by cache realize CPU and live storer between not high to rate request.
In the market according to the structural approach of existing storer, user can build the memory organization of the SOC of oneself product applicable, RAM inside order set and data system, CPU is to being a clock its access cycle, and the requirement degree of application to speed according to chip can flexible configuration.Conventional is configured with:
Configuration one: do not have order set and data system, all fetchings and the access to data are all operated the access of external memory storage by bus interface.
Configuration two: arrange in pairs or groups in order set I-Cache, and arrange in pairs or groups in data system D-Cache, and relevant access is all visit external memory storage by bus; What the size of the size of corresponding Cache can have more application needs configuration.
Configuration three: arrange in pairs or groups in order set ICCM; DCCM is configured in data system; What the size of the size of corresponding CCM can have more application needs configuration.
Configuration four: arrange in pairs or groups in order set I-Cache, ICCM; D-Cache is configured, DCCM in data system; What the size of the size of corresponding Cache and CCM can have more application needs configuration.
Above-mentioned several collocation methods are some more typical collocation methods, and user can choose CCM or Cache according to demand flexibly, and the size of corresponding size also can flexible configuration.But ICCM is merely able to deposit instruction code in this framework, DCCM can only use as data space, which limit the use of user to internal hardware resources.This structure can be good at meeting the application high to rate request, but the application lower to application velocity ratio, and can waste be compared in this configuration, how reasonably to utilize these internal resources to be exactly the emphasis that the present invention studies.
Such as: less demanding to the travelling speed of instruction, I-Cache is utilized to meet the demands, but require larger to the size of data space, expect to want fast, if adopt present structure to the access of the data space of CPU simultaneously, find that ICCM can, D-Cache and DCCM that SOC carries can not meet the demands, and the time that D-Cache refreshes cache-line is long, and the size of DCCM is limited, can not meet application requirement, these just bring trouble to system application.The present invention, just based on these application, adjusts inner hardware resource flexibly to better meet the demand of application.
Different application and developments, requires difference to cpu performance: the user low to rate request, and program can arrange position flexibly, can be placed in outside flash; The application high to rate request, program just must be placed in inner RAM. different application, the resource arrangement of the inside of CPU is had any different, in order to coordinate these application, simultaneously in order to avoid the waste of SOC internal storage resource, the present invention adopts the method for resource multiplex in system architecture to realize the resource of the allotment SOC inside of user flexibility.
Summary of the invention
The object of the invention is the deficiency overcoming above-mentioned technology, and the multiplexing method of the hardware resource in the system architecture in a kind of SOC is provided, the present invention realizes the framework of the storer of converting system acquiescence by the control of signal, to reach when lower to application velocity ratio, can the hardware resource of Appropriate application inside effectively, meet the object of systematic difference demand.
The technical solution used in the present invention: the multiplexing method of the hardware resource in the system architecture in this SOC, mainly comprises the following step:
(1), SOC banks of memory system structure can meet application demand at I-cache, but during the situation of DCCM insufficient space, by the selection of control signal, using the space being merged into the DCCM of data system complete for this ICCM as code space, address can with DCCM complete to connecting, do not go out the discontinuous of current address;
(2), SOC banks of memory system structure can meet application demand at D-cache, but during the situation of ICCM insufficient space, by the selection of control signal, using the space being merged into the ICCM of order set complete for this DCCM as data space, address can with ICCM complete to connecting, do not go out the discontinuous of current address;
(3), SOC banks of memory system structure can meet application demand at I-cache and D-cache, and by control signal the address space of ICCM and DCCM realized and the complete docking of RAM below Memory controller, address is continuous; Such user can allocation of codes or data space on so large RAM flexibly, facilitates application and development.
(4), when system has special speed requirement to instruction or data access, also only the RAM of ICCM can be multiplexed into the ram location below Memory controller;
(5), when system has special speed requirement to instruction or data access, also only the RAM of DCCM can be multiplexed into the ram location below Memory controller.
The SOC banks of memory system structure of described system default, mainly comprises CPU (cordis5+), order set and data system, bus interface, Memory Controller Hub, RAM and other storeies.
Described control signal can realize the framework conversion of the storer of system default, can control with the pin of register signal control or chip exterior.
The effect that the present invention is useful: the present invention can adjust by above-mentioned steps the demand that inner hardware resource better meets system application flexibly, provides a kind of reusable system architecture modulation scheme.Adopt this system architecture modulation scheme, the waste of CPU internal resource can be reduced, more effectively utilize system resource.
Accompanying drawing illustrates:
Fig. 1 is system default SOC banks of memory system structure.
Fig. 2 is the step 1 memory architecture transition diagram of the inventive method.
Fig. 3 is the step 2 memory architecture transition diagram of the inventive method.
Fig. 4 is the step 3 memory architecture transition diagram of the inventive method.
Fig. 5 is the step 4 memory architecture transition diagram of the inventive method.
Fig. 6 is the step 5 memory architecture transition diagram of the inventive method.
Embodiment
Be further described below in conjunction with drawings and Examples.
Fig. 1 is the SOC banks of memory system structure of system default of the present invention, mainly comprises CPU (cordis5+), order set and data system, bus interface, Memory Controller Hub, RAM and other storeies.
Fig. 2 is that system can meet application demand at I-cache, but during the situation of DCCM insufficient space, by the selection of control signal, the space that is merged into the DCCM of data system using complete for this ICCM as code space (address can with DCCM complete to connecting, do not go out the discontinuous of current address) memory architecture transition diagram.
Fig. 3 is that system can meet application demand at D-cache, but during the situation of ICCM insufficient space, by the selection of control signal, using this DCCM as data space can be complete be merged into the ICCM of order set space (address can with ICCM complete to connecting, do not go out the discontinuous of current address) memory architecture transition diagram.
Fig. 4 is that system can meet application demand at I-cache and D-cache, by control signal the memory architecture transition diagram of the complete docking of RAM (address is continuous) below the realization of the address space of ICCM and DCCM and Memory controller, such user can allocation of codes or data space on so large RAM flexibly, facilitates application and development.
Fig. 5 is when system has special speed requirement to instruction or data access, only the RAM of ICCM is multiplexed into the memory architecture transition diagram of the ram location below Memory controller.
Fig. 6 is when system has special speed requirement to instruction or data access, only the RAM of DCCM is multiplexed into the memory architecture transition diagram of the ram location below Memory controller.
The control signal of the concocting method of the above-mentioned several hardware resource of the present invention can control with register signal or the pin of chip exterior controls.
The present invention utilizes chip internal register to control, and arranges register SYS_MEM_CONFIG [2:0]
BIT [2:0]: 0x0: the collocation method of system default, configuration structure as corresponding in Fig. 1
0x1: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 2
0x2: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 3
0x3: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 4
0x4: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 5
0x5: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 6
The present invention also can utilize outside different PAD to control to configure inner different RAM, can be packaged into different chips like this.Utilize the control pin P_CONFIG [2:0] of chip exterior
P_CONFIG [2:0]: 0x0: the collocation method of system default, configuration structure as corresponding in Fig. 1
0x1: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 2
0x2: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 3
0x3: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 4
0x4: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 5
0x5: the configuration of the storer of system is according to structural adjustment corresponding to Fig. 6
Terminological interpretation
SOC: SOC (system on a chip), SOC (system on a chip) inside comprises CPU, storer, the resources such as control unit interface.
ROM: ROM (read-only memory), a kind of solid state semiconductor memory that can only read prior stored data.
RAM: random access memory, can realize read-write operation within a clock period.
Data buffer storage (D-Cache): generally have band data buffer storage in the system architecture in embedded chip, data buffer storage is the temporary data memory between processor and internal memory, general capacity is smaller, but data access speed is fast, when the datarams mounted under processor needs a large amount of access of system bus time, processor can determine the need of each all access memory according to the data status stored in data buffer storage, if the data in internal memory directly can read the data in data buffer storage in data buffer storage.
Instruction buffer (I-Cache): position and the effect of instruction buffer are equal to data buffer storage substantially, and difference is that instruction buffer is used to store instruction codes.
ICCM: for store instruction codes, and the streamline of CPU is combined closely, and needs a clock period to CPU, CPU directly can not perform write operation to it, exists in the chip of SOC with the form of RAM.
DCCM: for storing data, can not be used as code space, and the streamline of CPU is combined closely, needs a clock period, exist in the chip of SOC with the form of RAM to CPU.
The reduced instruction processor of Cordis 5+:32 position.
Harvard structure: a kind of by programmed instruction storage and data storage memory construction separately.
The order of the streamline of CPU: CPU performs and is divided into multiple step, and the step difference of the flowing water that flush bonding processor adopts is little, mainly wants fetching, decoding, and peek performs, and the step such as to write back.
Cache-line: the least unit of data transmission between main memory and cache.During each CPU access memory, in units of Cache Line, ask one or more Cache Line.
In addition to the implementation, all employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection domain of application claims.
Claims (1)
1. a multiplexing method for the hardware resource in the system architecture in SOC, is characterized in that: mainly comprise the following step:
(1), SOC banks of memory system structure can meet application demand at instruction buffer I-Cache, but during the situation of DCCM insufficient space, by the selection of control signal, using the space being merged into the DCCM of data system complete for this ICCM as code space, address can with DCCM complete to connecting, do not go out the discontinuous of current address;
(2), SOC banks of memory system structure can meet application demand at data buffer storage D-Cache, but during the situation of ICCM insufficient space, by the selection of control signal, using the space being merged into the ICCM of order set complete for this DCCM as data space, address can with ICCM complete to connecting, do not go out the discontinuous of current address;
(3), SOC banks of memory system structure can meet application demand at instruction buffer I-Cache and data buffer storage D-Cache, by control signal the complete docking of RAM below the realization of the address space of ICCM and DCCM and Memory controller, address is continuous;
(4) when SOC memory organization framework has demand to the speed of data access and space, by control signal, the address space of ICCM is multiplexed into ram location below Memory controller;
(5) when SOC memory organization framework has demand to the speed of instruction access and space, by control signal, the address space of DCCM is multiplexed into ram location below Memory controller.
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| CN102567220A (en) * | 2010-12-10 | 2012-07-11 | 中兴通讯股份有限公司 | Cache access control method and Cache access control device |
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| US7281228B2 (en) * | 2004-02-11 | 2007-10-09 | Infineon Technologies Ag | Configurable memory system for embedded processors |
| US8195879B2 (en) * | 2009-05-08 | 2012-06-05 | International Business Machines Corporation | Demand based partitioning of microprocessor caches |
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| CN101000596A (en) * | 2007-01-22 | 2007-07-18 | 北京中星微电子有限公司 | Chip and communication method of implementing communicating between multi-kernel in chip and communication method |
| CN102567220A (en) * | 2010-12-10 | 2012-07-11 | 中兴通讯股份有限公司 | Cache access control method and Cache access control device |
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Address after: Hangzhou City, Zhejiang province 311121 Yuhang Wuchang Street No. 998 West Sea Park Building 9 East Patentee after: HANGZHOU SYNODATA SECURITY TECHNOLOGY CO., LTD. Address before: Hangzhou City, Zhejiang province 311121 Yuhang Wuchang Street No. 998 West Sea Park Building 9 East Patentee before: Hangzhou Shengyuan Chip Technique Co., Ltd. |