CN102891083B - A kind of method preparing single electron transistor at room temperature - Google Patents
A kind of method preparing single electron transistor at room temperature Download PDFInfo
- Publication number
- CN102891083B CN102891083B CN201110205684.5A CN201110205684A CN102891083B CN 102891083 B CN102891083 B CN 102891083B CN 201110205684 A CN201110205684 A CN 201110205684A CN 102891083 B CN102891083 B CN 102891083B
- Authority
- CN
- China
- Prior art keywords
- source electrode
- electrode
- coulomb island
- drain
- prepare
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
A kind of method preparing single electron transistor at room temperature, with source electrode, drain gate, barrier layer and coulomb island as basic structure, cover layer, coulomb island, barrier layer, electrode, substrate and substrate stack gradually from top to bottom；Barrier layer on source electrode and drain electrode or on source electrode, drain and gate utilizes atomic layer deposition system to prepare, for forming the potential barrier of electron tunneling between electrode and coulomb island；Coulomb island utilizes the e-beam induced deposition of double-beam system to prepare, and its size, quantity and arrangement have controllability.The present invention accurately controls barrier layer thickness, accurately controls the assembling location on coulomb island, significantly reduces single-electronic transistor and prepare difficulty, improves batch and prepare the concordance of single-electronic transistor performance.
Description
Technical field
The present invention relates to nano electron device technical field, particularly to a kind of method using ald and e-beam induced deposition technology to prepare single electron transistor at room temperature.
Background technology
The characteristic size of the integrated circuit with MOSFET device as main flow has evolved to nanometer scale, and application is restricted, and the electronic logic device of the nano-scale that research and development are new becomes growth requirement further.Single-electronic transistor have size little, low in energy consumption, can the advantage such as large-scale integrated, be with a wide range of applications, can be used for the types of applications fields such as computer, sensor, detector.Typical single-electronic transistor is made up of source electrode, drain electrode, grid and coulomb island, is the nano electron device based on coulomb blockade effect and single electron tunneling effect.
1987, the aluminum quantum dot that Fulton of AT&T Labs et al. uses mask technique to be prepared for size about 30 nm was coulomb island, observed Single-electron phenomena under the ultralow temperature of 1.7 K.1989, the Scott-Thomas of MIT etc. use the method for X-ray lithography, silicon inversion layer is a narrow electron channel, wide about 30 nm, a length of 1 to 10 m with gap electrode, under 400 mK, has found that the conductance of passage presents periodically vibration with electrode voltage.Using microelectronic technique, a lot of research groups are prepared for the single-electronic transistor of low temperature and room temperature operation.Meanwhile, people have also carried out single-electronic transistor preparation research from bottom to top.Nineteen ninety-five, Chen etc. is prepared for the AuPd nanoparticle of size 2 to 3 nm, shows significant coulomb blockade effect with this single-electronic transistor built, the most at room temperature can also be observed that nonlinear C-V characteristic at a temperature of 77 K.1996, Klein etc. used Au nanoparticle and the CdSe nanoparticle of size about 5.8 nm, observed coulomb staircase curve clearly under temperature 77 K.Hereafter, a lot of research groups utilize approach from bottom to top to prepare single-electronic transistor, at room temperature observed Single-electron phenomena.
But generally there are three key technical problems in the preparation of existing single-electronic transistor: the controlled preparation on small size coulomb island；The controlled location on coulomb island assembles；The accurate control of tunneling barrier size between coulomb island and electrode.This operating temperature being related to device and the concordance of performance thereof.Therefore, research worker thirsts for developing one the most always can accurately control coulomb island size and a location, and controls the preparation method of potential barrier size coulomb between island and electrode, significantly to promote preparation and the application of single-electronic transistor.
Summary of the invention
The technical problem to be solved is: solve the problem that above-mentioned prior art exists, and a kind of method preparing single electron transistor at room temperature is proposed, accurately control barrier layer thickness, accurately control the assembling location on coulomb island, significantly reduce single-electronic transistor and prepare difficulty, improve batch and prepare the concordance of single-electronic transistor performance.
The technical solution used in the present invention is: single electron transistor at room temperature, and with source electrode, drain electrode, grid, barrier layer and coulomb island as basic structure, cover layer, coulomb island, barrier layer, electrode, substrate and substrate stack gradually from top to bottom；Barrier layer on source electrode and drain electrode or on source electrode, drain and gate utilizes atomic layer deposition system to prepare, for forming the potential barrier of electron tunneling between electrode and coulomb island；Coulomb island utilizes the e-beam induced deposition of electrons/ions double-beam system to prepare, and its size, quantity and arrangement have controllability.
In technique scheme, described substrate is prepared from by aoxidizing Si substrate, and source electrode, drain electrode, grid, barrier layer and coulomb island are integrally disposed in SiO2On substrate, coulomb island is located between source electrode and drain electrode, on barrier layer, and is totally independent of source electrode, drain and gate；Coulomb island can be multiple, and arrangement mode combination in any, grid is used for regulating and controlling a coulomb island energy level.
In technique scheme, the preparation process of single electron transistor at room temperature is as follows: first pass through electron-beam direct writing, substrate is prepared source electrode, drain and gate, then ordinary photolithographic technique is utilized to prepare the micron-sized lead-in wire electrode being connected respectively with source electrode, drain and gate, then ald is utilized, forming barrier layer on source electrode and drain electrode, recycling e-beam induced deposition prepares coulomb island between source electrode and drain electrode and on barrier layer.
In technique scheme, described substrate is the SiO thick for 200 to 500 nm formed by thermal oxide Si sheet2Insulating barrier, is positioned on Si substrate.
In technique scheme, described source electrode, drain and gate use electron beam exposure and electron beam evaporation deposition technology to prepare, and employing Ti is metal adhesion layers, and thickness is 2 to 5 nm, use Au for deposition material, and thickness is 3 to 25 nm.
In technique scheme, there is between described source electrode and drain electrode the distance of 5 to 15 nm.
In technique scheme, described grid and source electrode and the spacing of drain electrode, there is the distance of 1 to 5 times of source and drain spacing.
In technique scheme, described barrier layer uses technique for atomic layer deposition, is deposited on source electrode and drain electrode, and its thickness is 2 to 5 nm, thickness controllable precise.
In technique scheme, described barrier layer selects Al2O3Or SiO2Deng material.
In technique scheme, described coulomb island uses e-beam induced deposition technology, is deposited between source electrode and drain electrode, on barrier layer, and a diameter of 5 to 15 nm in coulomb island.
In technique scheme, described coulomb island size, quantity and arrangement mode of deposition between source electrode and drain electrode, on barrier layer can accurately control.
In technique scheme, the deposition materials such as Cu, Au, Al or W are selected on described coulomb island.
In technique scheme, described cover layer uses ald, thermal evaporation or sputtering sedimentation on source electrode, drain electrode, grid and coulomb island.
In technique scheme, described cover layer selects Al2O3Or SiO2Deng material, thickness is 10 to 100 nm.
Electron-beam exposure system of the present invention, ultraviolet lithographic system, electron beam evaporation deposition system, atomic layer deposition system are known maturation process technology, and the e-beam induced deposition of the electrons/ions double-beam system used is also for general known maturation process technology.
The specifically used step (2) asked for an interview in " detailed description of the invention "～step (9).
The electron-beam exposure system of the present invention uses the JBX5500ZA electron beam exposure apparatus of NEC；The ultraviolet lithographic system of the present invention uses the SUSS MA/BA6 litho machine of SUSS MicroTec company of Germany；The electron beam evaporation deposition system of the present invention uses the high vacuum evaporation coating system ei-5z of ULVAC company of Japan.
The atomic layer deposition system of the present invention uses the ald for scientific research and commercial Application (ALD) equipment that Finland times Nike (Beneq) provides.It is indoor that semiconductor base is arranged on ald by the Atomic layer deposition method that the present invention uses, the first precursor gas is made to flow to the substrate of described indoor, thus in substrate, effectively form the first monolayer, indoor at ald, under Surface microwave plasma condition, second precursor gas different from the first precursor gas composition is made to flow to the first indoor monolayer, with described first monolayer reaction, and form the second monolayer on the substrate, second monolayer is different from the composition of the first monolayer, second monolayer includes the first monolayer and the composition of described second precursor gas, and continuously repeat first, the flowing of the second precursor gas, and in substrate, effectively form the material in a large number with the second monolayer composition.
The e-beam induced deposition of the present invention uses the Helios NanoLab double-beam system of U.S. FEI to complete, this double-beam system is by electronic scanner microscope high for resolution together with high-performance beam integrity, and the said firm supplies electronics and ion cluster microscope and nanoscale application apparatus.
The present invention uses e-beam induced deposition to prepare coulomb island, in FEI Helios NanoLab double-beam system, place the barrier layer of stacking, electrode, substrate and substrate, under predetermined electron-beam voltage, electric current, sedimentation rate, carry out e-beam induced deposition, on barrier layer and between source electrode, drain electrode, prepare coulomb island.
Compared with prior art, the beneficial effects of the present invention is: the present invention uses ald can accurately control the size of potential barrier coulomb between island and electrode, utilize e-beam induced deposition can accurately control coulomb size, position and an arrangement mode for island deposition.The present invention solves in single-electronic transistor preparation process, and potential barrier size and location, coulomb island assemble uncontrollable problem, significantly reduce difficulty prepared by single-electronic transistor, improve batch and prepare the concordance of single-electronic transistor performance.
Accompanying drawing explanation
Fig. 1 is the schematic three dimensional views of a kind of single electron transistor at room temperature in the specific embodiment of the invention；
Fig. 2 is the cross-sectional view of single electron transistor at room temperature shown in Fig. 1；
Fig. 3 is the source of single electron transistor at room temperature shown in Fig. 1, leakage and the scanning electron microscope (SEM) photograph of grid three electrode；
Fig. 4 is the microelectrode light micrograph of the source of single electron transistor at room temperature, leakage and grid shown in Fig. 1 and external relation.
Description of reference numerals:
1 grid, 2 source electrodes, 3 substrates, 4 coulombs of islands, 5 barrier layers, 6 drain electrodes, 7 substrates, 8 cover layers, the lead-in wire platform that 9 are connected with source electrode, the 10 lead-in wire platforms being connected with drain electrode, the lead-in wire platform that 11 are connected with grid.
Detailed description of the invention
Seeing accompanying drawing, barrier layer thickness is accurately controlled by the present invention by technique for atomic layer deposition, and utilizes e-beam induced deposition technology accurately to control location, coulomb island, prepares single electron transistor at room temperature.
As shown in Fig. 1～2, this single electron transistor at room temperature is mainly made up of source electrode, drain electrode, grid, barrier layer and coulomb island, is integrally disposed in SiO2On substrate, this substrate is prepared from by thermal oxide Si substrate.Aforementioned coulomb island is between source electrode and drain electrode, on barrier layer, and is totally independent of source electrode, drain and gate.Meanwhile, aforementioned coulomb island can be multiple, and arrangement mode can combination in any.The grid of aforementioned single-electronic transistor is used for regulating and controlling a coulomb island energy level.
The preparation process of this single electron transistor at room temperature is as follows: first pass through electron-beam direct writing, substrate 7 is prepared source electrode 2, drain electrode 6 and grid 1, then ald is utilized, barrier layer 5 is formed on source electrode 2 and drain electrode 6, then utilize e-beam induced deposition between source electrode 2 and drain electrode 6, on barrier layer 5, prepare coulomb island 4.
Further saying, the processing technology of the present invention comprises the following specific steps that:
(1) clean Si substrate, then aoxidize 2 hours under the conditions of 1000 ° of C in oxidation furnace, prepare SiO2Insulating barrier, as substrate；
(2) using the technology such as electron-beam direct writing, electron beam evaporation, metal-stripping to complete the preparation (as shown in Figure 3) of the source electrode of nano-scale, drain and gate, electrode minimum feature is 25 nm；
(3) by the technology such as ultraviolet photolithographic, electron beam evaporation, metal-stripping prepare respectively with source electrode, the micron order wire of drain and gate UNICOM and lead-in wire platform (as shown in Figure 4), for device is transitioned into macroscopic circuit, this electrode minimum feature is 2 μm；
(4) on sample, coat one layer of AZ5214 photoresist, after front baking, use ultraviolet photolithographic machine to carry out G line exposing, recycling immersion method development, formed by source electrode, drain and gate connecting portion centered by, size be the mask pattern of 2 × 2 μm；
(5) using atomic layer deposition system to prepare barrier layer on source electrode and drain electrode, substrate temperature controls at 80 ° of about C, thickness about 2 nm of barrier layer deposition；
(6) utilize acetone to carry out wet method to remove photoresist；
(7) use double-beam system, utilize scanning electron microscope accurately to adjust sample position, then by electron beam-induced assistant depositing, between source electrode and drain electrode, on barrier layer, prepare coulomb island or coulomb island array, scanning electron microscope amplification 25W ×, electron-beam voltage 30kV, line 70pA；
(8) on sample, coat one layer of AZ5214 photoresist, after front baking, use ultraviolet photolithographic machine to carry out G line exposing, recycling immersion method development, in the region beyond the Pad of lead packages, formed centered by coulomb island, size is the mask pattern of 2 × 2 μm；
(9) on source electrode, drain electrode, grid and coulomb island, the SiO of 100 nm thickness is prepared by technology such as electron beam evaporations2Cover layer；
(10) utilize acetone to carry out wet method to remove photoresist；
(11) on sample, one layer of AZ5214 photoresist is coated, as the protective layer in scribing processes；
(12) use sand-wheel slice cutting machine, the wafer carrying out device architecture is cut into fritter, then cleans, remove photoresist；
(13) use wiring machine to carry out gold ball bonding, device is encapsulated on base, completes the preparation of this single electron transistor at room temperature.
In sum, the present invention is by using the technology such as ald and e-beam induced deposition, solve and accurately control potential barrier size and coulomb island between coulomb island and electrode and assemble the problem of location, thus for efficiently, batch prepares single electron transistor at room temperature and provides a kind of new method.
Claims (1)
1. the method preparing single electron transistor at room temperature, it is characterised in that concrete processing technology comprises the following specific steps that:
(1) clean Si substrate, then aoxidize 2 hours under the conditions of 1000 ° of C in oxidation furnace, prepare SiO2Insulating barrier, as substrate；
(2) using electron-beam direct writing, electron beam evaporation, metal lift-off techniques to complete the preparation of the source electrode of nano-scale, drain and gate, electrode minimum feature is 25 nm；
(3) by ultraviolet photolithographic, electron beam evaporation, metal lift-off techniques prepare respectively with source electrode, the micron order wire of drain and gate UNICOM and lead-in wire platform, for device is transitioned into macroscopic circuit, this electrode minimum feature is 2 μm；
(4) on sample, coat one layer of AZ5214 photoresist, after front baking, use ultraviolet photolithographic machine to carry out G line exposing, recycling immersion method development, formed by source electrode, drain and gate connecting portion centered by, size be the mask pattern of 2 × 2 μm；
(5) using atomic layer deposition system to prepare barrier layer on source electrode and drain electrode, substrate temperature controls at 80 ° of C, thickness 2 nm of barrier layer deposition；
(6) utilize acetone to carry out wet method to remove photoresist；
(7) use double-beam system, utilize scanning electron microscope accurately to adjust sample position, then by electron beam-induced assistant depositing, between source electrode and drain electrode, on barrier layer, prepare coulomb island or coulomb island array, scanning electron microscope amplification 25W ×, electron-beam voltage 30kV, line 70pA；
(8) on sample, coat one layer of AZ5214 photoresist, after front baking, use ultraviolet photolithographic machine to carry out G line exposing, recycling immersion method development, in the region beyond the Pad of lead packages, formed centered by coulomb island, size is the mask pattern of 2 × 2 μm；
(9) on source electrode, drain electrode, grid and coulomb island, the SiO of 100 nm thickness is prepared by electron beam evaporation technique2Cover layer；
(10) utilize acetone to carry out wet method to remove photoresist；
(11) on sample, one layer of AZ5214 photoresist is coated, as the protective layer in scribing processes；
(12) use sand-wheel slice cutting machine, the wafer carrying out device architecture is cut into fritter, then cleans, remove photoresist；
(13) use wiring machine to carry out gold ball bonding, device is encapsulated on base, completes the preparation of this single electron transistor at room temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110205684.5A CN102891083B (en) | 2011-07-22 | 2011-07-22 | A kind of method preparing single electron transistor at room temperature |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110205684.5A CN102891083B (en) | 2011-07-22 | 2011-07-22 | A kind of method preparing single electron transistor at room temperature |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102891083A CN102891083A (en) | 2013-01-23 |
| CN102891083B true CN102891083B (en) | 2016-10-19 |
Family
ID=47534548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110205684.5A Expired - Fee Related CN102891083B (en) | 2011-07-22 | 2011-07-22 | A kind of method preparing single electron transistor at room temperature |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102891083B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105502276B (en) * | 2016-01-06 | 2017-03-22 | 中国科学院物理研究所 | Method for preparing test electrodes on microparticles |
| CN106935501B (en) * | 2016-10-19 | 2023-08-22 | 中国人民解放军国防科学技术大学 | Method for preparing single-electron transistor by assembling gold particles with polystyrene microsphere template |
| CN106383163B (en) * | 2016-10-19 | 2023-10-17 | 中国人民解放军国防科学技术大学 | Ionization type gas sensor based on single-electron transistor and preparation method thereof |
| CN109894162B (en) * | 2019-03-11 | 2021-06-11 | 太原理工大学 | A PEDOT-based: micro-fluidic chip of PSS electrochemical transistor and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1189921A (en) * | 1996-03-26 | 1998-08-05 | 三星电子株式会社 | Tunnelling device and method of producing a tunnelling device |
| US7122413B2 (en) * | 2003-12-19 | 2006-10-17 | Texas Instruments Incorporated | Method to manufacture silicon quantum islands and single-electron devices |
| CN101226879A (en) * | 2007-01-18 | 2008-07-23 | 中国科学院化学研究所 | Method for preparation of nanometer clearance electrode |
| CN101752389A (en) * | 2009-10-16 | 2010-06-23 | 中国科学院上海技术物理研究所 | Al2O3/AlN/GaN/AlN MOS-HEMT device and manufacturing method thereof |
-
2011
- 2011-07-22 CN CN201110205684.5A patent/CN102891083B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1189921A (en) * | 1996-03-26 | 1998-08-05 | 三星电子株式会社 | Tunnelling device and method of producing a tunnelling device |
| US7122413B2 (en) * | 2003-12-19 | 2006-10-17 | Texas Instruments Incorporated | Method to manufacture silicon quantum islands and single-electron devices |
| CN101226879A (en) * | 2007-01-18 | 2008-07-23 | 中国科学院化学研究所 | Method for preparation of nanometer clearance electrode |
| CN101752389A (en) * | 2009-10-16 | 2010-06-23 | 中国科学院上海技术物理研究所 | Al2O3/AlN/GaN/AlN MOS-HEMT device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102891083A (en) | 2013-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9070556B2 (en) | Patterning of nanostructures | |
| US6465782B1 (en) | Strongly textured atomic ridges and tip arrays | |
| CN102891083B (en) | A kind of method preparing single electron transistor at room temperature | |
| CN110310873A (en) | A kind of vertical-type nano gap evacuated transistor of extended grid structure and preparation method thereof | |
| Donatini et al. | A single-step electron beam lithography of buried nanostructures using cathodoluminescence imaging and low temperature | |
| CN111613661B (en) | Tunnel junction, preparation method and application thereof | |
| Sychugov et al. | Sub-10 nm crystalline silicon nanostructures by electron beam induced deposition lithography | |
| CN106935501B (en) | Method for preparing single-electron transistor by assembling gold particles with polystyrene microsphere template | |
| CN103840003B (en) | The double grid grapheme transistor and preparation method thereof being gate medium with aluminium sesquioxide | |
| CN102709133A (en) | Cold cathode electron source array with embedded electrode, method for producing cold cathode electron source array and application of cold cathode electron source array | |
| CN112599419B (en) | Printing type construction method of micro-nano semiconductor device | |
| TWI227516B (en) | Nano-electronic devices using discrete exposure method | |
| US9321633B2 (en) | Process for producing 3-dimensional structure assembled from nanoparticles | |
| JP4631004B2 (en) | Manufacturing method of nanogap electrode | |
| US20050163931A1 (en) | Orientation coating method of the top of micro tip | |
| Zhukov et al. | A study of quantum dots in a multigrain layer of a planar-end microstructure | |
| Wan et al. | High-vacuum electron-beam co-evaporation of Si nanocrystals embedded in Al2O3 matrix | |
| CN109946340B (en) | Preparation method of two-dimensional layered material sample electrical testing microelectrode | |
| CN1160798C (en) | Point contact planar grid type single-electronic transistor and its preparing process | |
| Dutta et al. | Electron-beam direct writing using RD2000N for fabrication of nanodevices | |
| KR100425347B1 (en) | Single electron transistor utilizing nano particle | |
| KR102423791B1 (en) | Nano structure with selectively deposited nano materials and method for selective deposition of nanomaterials on nano structure | |
| Pichon et al. | Fabrication of amorphous silicon nanoribbons by atomic force microscope tip-induced local oxidation for thin film device applications | |
| CN108793066B (en) | Preparation method of nano device | |
| RU2712534C9 (en) | Method of forming thin ordered semiconductor filamentary nanocrystals without participation of external catalyst on silicon substrates |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161019 Termination date: 20210722 |