CN102866548B - Pixel structure of display panel and manufacturing method thereof - Google Patents
Pixel structure of display panel and manufacturing method thereof Download PDFInfo
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- CN102866548B CN102866548B CN201210327819.XA CN201210327819A CN102866548B CN 102866548 B CN102866548 B CN 102866548B CN 201210327819 A CN201210327819 A CN 201210327819A CN 102866548 B CN102866548 B CN 102866548B
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Abstract
The invention discloses a pixel structure of a display panel and a manufacturing method thereof. The pixel structure comprises a first pixel zone and a second pixel zone which are adjacent to each other, wherein a first transparent conductive layer is arranged in the first pixel zone, a second transparent conductive layer is arranged in the second pixel zone, and the first transparent conductive layer in the first pixel zone and the second transparent conductive layer in the second pixel zone are located at different horizontal heights. The pixel structure disclosed by the invention has the advantage that the pixel aperture ratio can be effectively increased.
Description
Technical field
The present invention relates to a kind of image element structure and manufacture method thereof of display panel, especially about a kind of image element structure and the manufacture method thereof that can promote picture element aperture opening ratio.
Background technology
Now, when monitor resolution improves day by day, need the size constantly reducing picture element region, the so incident problem being picture element aperture opening ratio (aperture ratio) and declining, and the decline of aperture opening ratio can cause panel light transmission rate deficiency maybe must increase backlight power, therefore how to improve picture element aperture opening ratio quite important for high-resolution display product.
Current display panel manufacture has gradually increases the trend that optical cover process number carrys out increasing opening rate, such as: bring up to six Dao Huo eight road optical cover process from five traditional road optical cover process.In known technology, one is had to be utilize the mode hiding storage capacitors (storage capacitor) electrode to carry out increasing opening rate.In general, as long as metal level built by cloth in image element structure, the sub-fraction of itself and pixel electrode is overlapped up and down, middlely to separate with insulation course, can storage capacitors be formed, usually this metal level also can Connection Sharing electrode to provide share voltage.For example, having a kind of is built in and sweep trace (or gate line) identical layer by the electrode cloth of storage capacitors, and be arranged on data line (or source electrode line) below, another kind is also be arranged on below data line by the electrode of storage capacitors, but cloth is built in and sweep trace different layers, this electrode is also shared electrode simultaneously, and the signal between sweep trace and data line can be avoided to disturb.
No matter which kind of mode above-mentioned, there is following problem: the spacing of the pixel electrode of two adjacent picture element regions must be greater than a preset distance, if the spacing of two adjacent pixel electrodes is not greater than this preset distance, then has and very high may form short circuit, cause panel cannot normal show image.That is, in known techniques, the design of adjacent two pixel electrodes is still subject to processing procedure restriction, and still cannot effectively promote for picture element aperture opening ratio.
Summary of the invention
The object of the present invention is to provide a kind of image element structure and the manufacture method thereof that can promote the display panel of picture element aperture opening ratio.
For reaching above-mentioned purpose, the invention provides a kind of manufacture method of image element structure, described image element structure comprises one first picture element region adjacent one another are and one second picture element region, it is so that at least scan line and at least one source electrode line mark off region affiliated separately, this first picture element region and this second picture element region respectively have a thin film transistor (TFT), this first picture element region all has first end with the thin film transistor (TFT) in this second picture element region and is electrically connected to this sweep trace, second end is electrically connected to this source electrode line, and the 3rd end, described manufacture method comprises step: form one first transparency conducting layer in this first picture element region, 3rd end of the thin film transistor (TFT) of this first transparency conducting layer and this first picture element region is electrically connected, form one first wall and cover this first picture element region and this second picture element region, form the intersection of a conductive layer in this first picture element region with this second picture element region, form one second wall and cover this first picture element region and this second picture element region, form one second transparency conducting layer in this second picture element region, the 3rd end of the thin film transistor (TFT) of this second transparency conducting layer and this second picture element region is electrically connected, and this first wall above this first transparency conducting layer removing in this first picture element region and this second wall, to expose this first transparency conducting layer.
This first transparency conducting layer in this first picture element region and this second electrically conducting transparent series of strata position in this second picture element region are in different level heights.
The some of this first transparency conducting layer is formed at immediately below this conductive layer, and the some of this first transparency conducting layer and this conduction series of strata by this first spacing layer separates, and form one first storage capacitors; The some of this second transparency conducting layer is formed at directly over this conductive layer, and the some of this second transparency conducting layer and this conduction series of strata by this second spacing layer separates, and form one second storage capacitors.
It is formed at this first storage capacitors between the some of this first transparency conducting layer and this conductive layer and is formed at this second storage capacitors equal and opposite in direction in fact between the some of this second transparency conducting layer and this conductive layer.
It is formed at this first storage capacitors between the some of this first transparency conducting layer and this conductive layer and this second storage capacitors be formed between the some of this second transparency conducting layer and this conductive layer differs in size.
These the first electrically conducting transparent series of strata in this first picture element region are electrically connected with the 3rd end of the thin film transistor (TFT) of this first picture element through one first through hole; These the second electrically conducting transparent series of strata in this second picture element region are electrically connected with the 3rd end of the thin film transistor (TFT) of this second picture element through one second through hole.
This first transparency conducting layer and these the second electrically conducting transparent series of strata, as pixel electrode, are rotated to drive liquid crystal molecule in order to provide voltage.
The present invention provides a kind of manufacture method of image element structure on the other hand, described image element structure comprises one first picture element region adjacent one another are and one second picture element region, it is so that at least scan line and at least one source electrode line mark off region affiliated separately, this first picture element region and this second picture element region respectively have a thin film transistor (TFT), this first picture element region all has first end with the thin film transistor (TFT) in this second picture element region and is electrically connected to this sweep trace, second end is electrically connected to this source electrode line, and the 3rd end, described manufacture method comprises step: form one first transparency conducting layer in this first picture element region, 3rd end of the thin film transistor (TFT) of this first transparency conducting layer and this first picture element region is electrically connected, and under the level height different from this first transparency conducting layer, form one second transparency conducting layer in this second picture element region, the 3rd end of the thin film transistor (TFT) of this second transparency conducting layer and this second picture element region is electrically connected.
It more comprises step: form the intersection of a conductive layer in this first picture element region with this second picture element region, to make immediately below this conductive layer should the some of the first transparency conducting layer, and to should the some of the second transparency conducting layer directly over this conductive layer, wherein the some of this first transparency conducting layer and this conductive layer form one first storage capacitors, and the some of this second transparency conducting layer and this conductive layer form one second storage capacitors.
The image element structure of a kind of display panel of further aspect of the present invention, described image element structure comprises one first picture element region adjacent one another are and one second picture element region, it is so that at least scan line and at least one source electrode line mark off region affiliated separately, this first picture element region and this second picture element region respectively have a thin film transistor (TFT), this first picture element region all has first end with the thin film transistor (TFT) in this second picture element region and is electrically connected to this sweep trace, second end is electrically connected to this source electrode line, and the 3rd end, described image element structure comprises: one first transparency conducting layer, be arranged in this first picture element region, 3rd end of the thin film transistor (TFT) of this first transparency conducting layer and this first picture element region is electrically connected, and one second transparency conducting layer, be arranged in this second picture element region, the 3rd end of the thin film transistor (TFT) of this second transparency conducting layer and this second picture element region is electrically connected, this first transparency conducting layer wherein in this first picture element region and this second electrically conducting transparent series of strata position in this second picture element region are in different level heights.
It more comprises: a conductive layer, and be arranged at the intersection of this first picture element region and this second picture element region, the some of this first transparency conducting layer is formed at immediately below this conductive layer, and the some of this second transparency conducting layer is formed at directly over this conductive layer; One first wall, in order to the some of this conductive layer and this first transparency conducting layer to be separated, makes the some of this conductive layer and this first transparency conducting layer form one first storage capacitors; And one second wall, in order to this conductive layer with the some of this second transparency conducting layer is separated, make the some of this conductive layer and this second transparency conducting layer form one second storage capacitors.
These the first electrically conducting transparent series of strata in this first picture element region are electrically connected with the 3rd end of the thin film transistor (TFT) of this first picture element through one first through hole; These the second electrically conducting transparent series of strata in this second picture element region are electrically connected with the 3rd end of the thin film transistor (TFT) of this second picture element through one second through hole.
The present invention adopts above technical scheme, utilize the first transparency conducting layer and the second transparency conducting layer position in different level heights, the level interval of the first transparency conducting layer and the second electrically conducting transparent interlayer can reduce compared to the spacing in Manufacturing Process, and therefore picture element aperture opening ratio can promote.Conductive layer is set between the first transparency conducting layer and the second transparency conducting layer simultaneously, can shielding effect be played, the voltage of the first transparency conducting layer and the second transparency conducting layer can not be interacted.Moreover, the storage capacitors of picture element data can be formed between conductive layer and the first transparency conducting layer and between conductive layer and the second transparency conducting layer, and the size of storage capacitors can be adjusted by the space layer changed between conductive layer and transparency conducting layer.
Accompanying drawing explanation
Now by reference to the accompanying drawings the present invention is further described:
Fig. 1 is the schematic diagram of first micro image etching procedure in the manufacture method of image element structure of the present invention;
Fig. 2 is the schematic diagram of second micro image etching procedure in the manufacture method of image element structure of the present invention;
Fig. 3 is the schematic diagram of the 3rd road micro image etching procedure in the manufacture method of image element structure of the present invention;
Fig. 4 is the schematic diagram of the 4th road micro image etching procedure in the manufacture method of image element structure of the present invention;
Fig. 5 is the schematic diagram of the 5th road micro image etching procedure in the manufacture method of image element structure of the present invention;
Fig. 6 is the schematic diagram of the 6th road micro image etching procedure in the manufacture method of image element structure of the present invention;
Fig. 7 is the schematic diagram of the 7th road micro image etching procedure in the manufacture method of image element structure of the present invention;
Fig. 8 is the schematic diagram of the 8th road micro image etching procedure in the manufacture method of image element structure of the present invention;
Fig. 9 is the schematic diagram of the 9th road micro image etching procedure in the manufacture method of image element structure of the present invention;
Figure 10 is the cross-sectional schematic of manufacture method Fig. 9 along A-A' section of the image element structure of display panel of the present invention;
Figure 11 is the cross-sectional schematic of manufacture method Fig. 9 along B-B' section of the image element structure of display panel of the present invention;
Figure 12 is the cross-sectional schematic of manufacture method Fig. 9 along C-C' section of the image element structure of display panel of the present invention.
Embodiment
The present invention is image element structure about a kind of display panel and manufacture method thereof, its feature is that the pixel electrode in two adjacent picture element regions is arranged on differentiated levels, alternatively, these two pixel electrodes are formed at different layers, can reduce the spacing of the level interval institute's specification on processing procedure between the pixel electrode of two adjacent picture element regions by this, that is, pixel electrode area occupied has become greatly relatively, and therefore the present invention can effective increasing opening rate.On the other hand, the present invention can arrange conductive layer (or metal conducting layer) at the intersection of two adjacent picture element regions, this conductive layer can form storage capacitors by the pixel electrode respectively with two in adjacent picture element region, this conductive layer also can reduce the coupling influence of two adjacent pixel electrodes by shielding effect, therefore can promote the degree of stability of image display.
The schematic diagram of the manufacture method of image element structure of the present invention is shown as Fig. 1 to Fig. 9, Figure 10 shows in Fig. 9 along the diagrammatic cross-section that A-A' profile line is drawn, Figure 11 shows along the diagrammatic cross-section that B-B' profile line is drawn in Fig. 9, and Figure 12 shows in Fig. 9 along the diagrammatic cross-section that C-C' profile line is drawn.
In following explanation, the present invention illustratively illustrates with two adjacent picture element regions, i.e. the first picture element region 1 and the second picture element region 2, the picture element region alleged by the present invention also can be the sub-picture element region in picture element region, as red bluish-green picture element region.In the present invention, picture element region can define its regional extent by staggered sweep trace (or gate line) and data line (or source electrode line), that is, and the region belonging to the first picture element region 1 and the second picture element region 2 can mark off separately by sweep trace and source electrode line.And, in an exemplary embodiment of the invention, first picture element region 1 and this second picture element region 2 respectively have a foamed film transistor (thin-film transistor), each thin film transistor (TFT) has a first end, one second end and one the 3rd end, it can be sequentially gate, source electrode and drain respectively, the first end of thin film transistor (TFT) and sweep trace are electrically connected, and the second end of thin film transistor (TFT) and source electrode line are electrically connected, and the 3rd end of thin film transistor (TFT) can be electrically connected to pixel electrode.
Refer to Fig. 1, first first micro image etching procedure (photolithographic etching process is utilized, PEP) on substrate, patterned first metal layer 11 is formed, patterned first metal layer 11 comprises the gate of thin film transistor (TFT), in this step, patterned first metal layer 11 also can comprise gate line, and that is, thin film transistor (TFT) gate and gate line are with same material and are formed in same fabrication steps.The some of gate line can be used as the gate of thin film transistor (TFT), and thin film transistor (TFT) gate and gate line are in fact be electrically connected, and the material of patterned first metal layer 11 can be aluminium or other conductor material.Specifically apply as follows, first on substrate, deposit a first metal layer, then form patterning photoresist layer on the first metal layer, then carry out etch process, to form patterned first metal layer 11 as shown in Figure 1.
Then, as shown in one of Figure 10-12, one first insulation course 12 is formed to cover the first picture element region 1 and the second picture element region 2.
Refer to Fig. 2, utilize second micro image etching procedure to form patterned semiconductor layer 13 on the first insulation course 12, patterned semiconductor layer 13 is also called active layers.Patterned semiconductor layer 13 be arranged on thin film transistor (TFT) gate, between source electrode and drain, as channel semiconductor.In the present embodiment, patterned semiconductor layer 13 extends to again the region corresponding with the follow-up source electrode line that will be formed.But in another embodiment, patterned semiconductor layer 13 can not need to extend to the region corresponding with source electrode line.
Refer to Fig. 3, the 3rd road micro image etching procedure is utilized to form patterning second metal level 14, patterning second metal level 14 comprises source electrode 141 and the drain 142 of thin film transistor (TFT), in this step, patterning second metal level 14 also can comprise source electrode line, that is, source electrode 141, drain 142 and source electrode line are with same material and are formed in same fabrication steps.The some of source electrode line can be used as the source electrode 141 of thin film transistor (TFT), and thin film transistor (TFT) source electrode 141 and source electrode line are in fact be electrically connected.The material of patterning second metal level 14 can be composite material or other single or composite conductor material be suitable for of molybdenum/aluminium/molybdenum (Mo/Al/Mo).Specifically apply as follows, first deposit one second metal level, then on the second metal level, form patterning photoresist layer, then carry out etch process, to form patterning second metal level 14 as shown in Figure 3.
Then, as shown in one of Figure 10-12, one second insulation course 15 is formed to cover the first picture element region 1 and the second picture element region 2.
Refer to Fig. 4, utilize the 4th road micro image etching procedure to carry out perforate to form the drain 142 that the first through hole 151, first through hole 151 exposes the thin film transistor (TFT) of the first picture element region 1 to the second insulation course 15 in the first picture element region 1.
Refer to Fig. 5, utilize the 5th corresponding first picture element region 1 of road micro image etching procedure to form the first transparency conducting layer 16, as the pixel electrode of the first picture element region 1.First transparency conducting layer 16 is electrically connected with the drain 142 of the thin film transistor (TFT) of the first picture element region 1 through the first through hole 151, and the voltage that the first transparency conducting layer 16 can provide through the thin film transistor (TFT) drain 142 of the first picture element region 1 is to drive liquid crystal deflecting element.Specifically apply, first can be coated with transparency conducting layer to cover the first picture element region 1 and the second picture element region 2, and after etching removes the transparency conducting layer of corresponding second picture element region 2, only leaves the transparency conducting layer of corresponding first picture element region 1, i.e. the first transparency conducting layer 16.
Then as seen in figures 11 or 12, one first wall 17 is formed to cover the first picture element region 1 and the second picture element region 2.
Refer to Fig. 6, utilize the 6th road micro image etching procedure to form conductive layer 18(or a metal conducting layer at the intersection of the first picture element region 1 and the second picture element region 2).The some of corresponding first transparency conducting layer 16 immediately below conductive layer 18, and the some of corresponding follow-up second transparency conducting layer 20 that will make directly over conductive layer 18.Moreover, above the top that conductive layer 18 may extend to gate line or side, receive the share voltage that common electrode provides.
Then as seen in figures 11 or 12, one second wall 19 is formed to cover the first picture element region 1 and the second picture element region 2.
Refer to Fig. 7, the 7th road micro image etching procedure is utilized to carry out perforate to form the drain 142 that the second through hole 191, second through hole 191 exposes the thin film transistor (TFT) of the second picture element region 2 to the second insulation course 15, first wall 17 and the second wall 19 in the second picture element region 2.
Refer to 8 figure, utilize the 8th corresponding second picture element region 2 of road micro image etching procedure to form the second transparency conducting layer 20, as the pixel electrode of the second picture element region 2.Second transparency conducting layer 20 is electrically connected with the drain 142 of the thin film transistor (TFT) of the second picture element region 2 through the second through hole 191, and the voltage that the second transparency conducting layer 20 can provide through the thin film transistor (TFT) drain 142 of the second picture element region 2 is to drive liquid crystal deflecting element.The material of the first transparency conducting layer 16 and the second transparency conducting layer 20 can be indium tin oxide (Indium Tin Oxide, ITO), and the production method of the second transparency conducting layer 20 and the first transparency conducting layer 16 similar, do not repeat them here.
Refer to Fig. 9, finally utilize the 9th road micro image etching procedure, the first wall 17 above the first transparency conducting layer 16 in the first picture element region 1 and the secondth wall 19 are removed, to expose the first transparency conducting layer 16.
As shown in figure 12, image element structure of the present invention comprises the first picture element region 1 and the second picture element region 2 adjacent one another are, the first transparency conducting layer 16 in first picture element region 1 is that position is in different level heights from the second transparency conducting layer 20 in the second picture element region 2, specifically, first transparency conducting layer 16 and the second transparency conducting layer 20 are formed in different layers, different fabrication steps, and the level interval d of the first transparency conducting layer 16 and the second transparency conducting layer 20 can reduce by this.This is because be located in the example of same layer at the transparency conducting layer of two adjacent picture element regions, in existing factory, the level interval of this two transparency conducting layer of technology needs to be greater than 6 μm, otherwise the voltage of this two transparency conducting layer can interact, and affects the display of image frame.Because in the present invention, the first transparency conducting layer 16 and the second transparency conducting layer are that position is in different level heights, therefore both level interval d can reduce, such as level interval narrows down to 3 μm, thus, first transparency conducting layer 16 is relative with the area that the second transparency conducting layer 20 can occupy have been become greatly, and therefore the present invention effectively can promote the aperture opening ratio of picture element.
As shown in figure 12, the intersection of the first picture element region 1 and the second picture element region 2 is formed with conductive layer 18, the some of the first transparency conducting layer 16 of the first picture element region 1 is formed at the below of conductive layer 18, and the some of the second transparency conducting layer 20 of the second picture element region 2 is formed at the top of conductive layer 18, the some of the first transparency conducting layer 16, separate with the first wall 17 and the second wall 19 between the some of conductive layer 18 and the second transparency conducting layer 20, conductive layer 18 can play shielding effect at this and reduce the first transparency conducting layer 16 and the contingent coupling influence of the second transparency conducting layer 20, therefore the degree of stability of image display can be promoted.In addition, if conductive layer 18 metal conducting layer, then the shield effectiveness produced may be better.
Moreover the some of the first transparency conducting layer 16 of the first picture element region 1 is arranged at immediately below conductive layer 18, and is separated by the first wall 17, between conductive layer 18 like this and the first transparency conducting layer 16, one first storage capacitors C1 can be formed; The some of the second transparency conducting layer 20 of the second picture element region 2 is arranged at directly over conductive layer 18, and is separated by the second wall 19, can form one second storage capacitors C2 between conductive layer 18 like this and the second transparency conducting layer 20.The size of the first storage capacitors C1 and the second storage capacitors C2, except can adjusting by the size changing its area occupied, also can adjust by the thickness of change first wall 17 and the second wall 19.In one embodiment, the first wall 17 is identical with the thickness of the second wall 19, and the first storage capacitors C1 is also identical with the size of the second storage capacitors C2.In another embodiment, realizing the mode that the first storage capacitors C1 and the second storage capacitors C2 has a different capacitance is make the first wall 17 and the second wall 19 have different thickness, and such as, when space layer increases, storage capacitors then can reduce relatively.
In sum; although the invention discloses preferred embodiment; but not limit the present invention with this; persond having ordinary knowledge in the technical field of the present invention; not departing from the scope of the present invention; when being used for a variety of modifications and variations, therefore protection scope of the present invention with the present patent application claim define enclosing of model and be as the criterion.
Claims (11)
1. the manufacture method of image element structure, described image element structure comprises one first picture element region adjacent one another are and one second picture element region, it is so that at least scan line and at least one source electrode line mark off region affiliated separately, this first picture element region and this second picture element region respectively have a thin film transistor (TFT), thin film transistor (TFT) in this first picture element region and this second picture element region all has that first end is electrically connected to this sweep trace, the second end is electrically connected to this source electrode line and the 3rd end, it is characterized in that: described manufacture method comprises step:
Form one first transparency conducting layer in this first picture element region, the 3rd end of the thin film transistor (TFT) of this first transparency conducting layer and this first picture element region is electrically connected;
Form one first wall and cover this first picture element region and this second picture element region;
Form the intersection of a conductive layer in this first picture element region with this second picture element region;
Form one second wall and cover this first picture element region and this second picture element region;
Form one second transparency conducting layer in this second picture element region, the 3rd end of the thin film transistor (TFT) of this second transparency conducting layer and this second picture element region is electrically connected; And
Remove this first wall above this first transparency conducting layer in this first picture element region and this second wall, to expose this first transparency conducting layer;
The some of this first transparency conducting layer is formed at immediately below this conductive layer, and the some of this first transparency conducting layer and this conduction series of strata by this first spacing layer separates, and form one first storage capacitors; The some of this second transparency conducting layer is formed at directly over this conductive layer, and the some of this second transparency conducting layer and this conduction series of strata by this second spacing layer separates, and form one second storage capacitors.
2. the manufacture method of image element structure according to claim 1, is characterized in that: this first transparency conducting layer in this first picture element region and this second electrically conducting transparent series of strata position in this second picture element region are in different level heights.
3. the manufacture method of image element structure according to claim 1, is characterized in that: it is formed at this first storage capacitors between the some of this first transparency conducting layer and this conductive layer and is formed at this second storage capacitors equal and opposite in direction in fact between the some of this second transparency conducting layer and this conductive layer.
4. the manufacture method of image element structure according to claim 1, is characterized in that: it is formed at this first storage capacitors between the some of this first transparency conducting layer and this conductive layer and this second storage capacitors be formed between the some of this second transparency conducting layer and this conductive layer differs in size.
5. the manufacture method of image element structure according to claim 1, is characterized in that: these the first electrically conducting transparent series of strata in this first picture element region are electrically connected with the 3rd end of the thin film transistor (TFT) of this first picture element through one first through hole; These the second electrically conducting transparent series of strata in this second picture element region are electrically connected with the 3rd end of the thin film transistor (TFT) of this second picture element through one second through hole.
6. the manufacture method of image element structure according to claim 1, is characterized in that: this first transparency conducting layer and these the second electrically conducting transparent series of strata, as pixel electrode, are rotated to drive liquid crystal molecule in order to provide voltage.
7. the manufacture method of an image element structure, described image element structure comprises one first picture element region adjacent one another are and one second picture element region, it is so that at least scan line and at least one source electrode line mark off region affiliated separately, this first picture element region and this second picture element region respectively have a thin film transistor (TFT), thin film transistor (TFT) in this first picture element region and this second picture element region all has that first end is electrically connected to this sweep trace, the second end is electrically connected to this source electrode line and the 3rd end, it is characterized in that: described manufacture method comprises step:
Form one first transparency conducting layer in this first picture element region, the 3rd end of the thin film transistor (TFT) of this first transparency conducting layer and this first picture element region is electrically connected; And
Under the level height different from this first transparency conducting layer, form one second transparency conducting layer in this second picture element region, the 3rd end of the thin film transistor (TFT) of this second transparency conducting layer and this second picture element region is electrically connected.
8. the manufacture method of image element structure according to claim 7, is characterized in that: it more comprises step:
Form the intersection of a conductive layer in this first picture element region with this second picture element region, to make immediately below this conductive layer should the some of the first transparency conducting layer, and to should the some of the second transparency conducting layer directly over this conductive layer, wherein the some of this first transparency conducting layer and this conductive layer form one first storage capacitors, and the some of this second transparency conducting layer and this conductive layer form one second storage capacitors.
9. the image element structure of a display panel, described image element structure comprises one first picture element region adjacent one another are and one second picture element region, it is so that at least scan line and at least one source electrode line mark off region affiliated separately, this first picture element region and this second picture element region respectively have a thin film transistor (TFT), thin film transistor (TFT) in this first picture element region and this second picture element region all has that first end is electrically connected to this sweep trace, the second end is electrically connected to this source electrode line and the 3rd end, it is characterized in that: described image element structure comprises:
One first transparency conducting layer, is arranged in this first picture element region, and the 3rd end of the thin film transistor (TFT) of this first transparency conducting layer and this first picture element region is electrically connected; And
One second transparency conducting layer, is arranged in this second picture element region, and the 3rd end of the thin film transistor (TFT) of this second transparency conducting layer and this second picture element region is electrically connected;
This first transparency conducting layer wherein in this first picture element region and this second electrically conducting transparent series of strata position in this second picture element region are in different level heights.
10. the image element structure of display panel according to claim 9, is characterized in that: it more comprises:
One conductive layer, be arranged at the intersection of this first picture element region and this second picture element region, the some of this first transparency conducting layer is formed at immediately below this conductive layer, and the some of this second transparency conducting layer is formed at directly over this conductive layer;
One first wall, in order to the some of this conductive layer and this first transparency conducting layer to be separated, makes the some of this conductive layer and this first transparency conducting layer form one first storage capacitors; And
One second wall, in order to this conductive layer with the some of this second transparency conducting layer is separated, make the some of this conductive layer and this second transparency conducting layer form one second storage capacitors.
The image element structure of 11. display panels according to claim 9, is characterized in that: these the first electrically conducting transparent series of strata in this first picture element region are electrically connected with the 3rd end of the thin film transistor (TFT) of this first picture element through one first through hole; These the second electrically conducting transparent series of strata in this second picture element region are electrically connected with the 3rd end of the thin film transistor (TFT) of this second picture element through one second through hole.
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| CN1945391A (en) * | 2005-09-27 | 2007-04-11 | 三星电子株式会社 | Liquid crystal display |
| JP4812839B2 (en) * | 2006-08-08 | 2011-11-09 | シャープ株式会社 | TFT substrate, liquid crystal display panel including the same, liquid crystal display device, and method for manufacturing TFT substrate |
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| KR101200939B1 (en) * | 2006-01-19 | 2012-11-13 | 삼성디스플레이 주식회사 | Array substrate |
| EP2511760B1 (en) * | 2009-12-08 | 2015-11-04 | Sharp Kabushiki Kaisha | Active matrix substrate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1945391A (en) * | 2005-09-27 | 2007-04-11 | 三星电子株式会社 | Liquid crystal display |
| JP4812839B2 (en) * | 2006-08-08 | 2011-11-09 | シャープ株式会社 | TFT substrate, liquid crystal display panel including the same, liquid crystal display device, and method for manufacturing TFT substrate |
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