CN102832244B - With the semiconductor device and preparation method thereof of the exposed device termination electrode of substrate terminal - Google Patents
With the semiconductor device and preparation method thereof of the exposed device termination electrode of substrate terminal Download PDFInfo
- Publication number
- CN102832244B CN102832244B CN201110170350.9A CN201110170350A CN102832244B CN 102832244 B CN102832244 B CN 102832244B CN 201110170350 A CN201110170350 A CN 201110170350A CN 102832244 B CN102832244 B CN 102832244B
- Authority
- CN
- China
- Prior art keywords
- termination electrode
- substrate
- semiconductor
- exposed
- substrate terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal has with device end, substrate terminal and the Semiconductor substrate (SCS) in semiconductor device district (SDR) being positioned at device end.In order to the operation of device, form device termination electrode (DSE).Straight-through substrate trenches (TST) extends through Semiconductor substrate, touches device termination electrode, it is become the exposed device termination electrode in substrate terminal.Can pass through conductive connecting, through straight-through substrate trenches, interconnect the exposed device termination electrode in substrate terminal.Device termination electrode also can containing one extend bracing frame, storehouse exposed below the device termination electrode of substrate terminal so that when wafer reprocessing encapsulates, for it provides support structure.
Description
Technical field
The present invention relates generally to semiconductor device structure field.Or rather, the invention relates to device architecture and preparation method that preparation simplifies the power semiconductor of wafer reprocessing, such as power metal-Oxide-Semiconductor Field effect pipe (MOSFET) and igbt (IGBT).
Background technology
For the system in package of power MOSFET device, sometimes need bottom source power MOSFET to optimize chip layout and/or to reduce the parasitic interconnection impedance relevant to encapsulation.U. S. application 11/830951 just proposes such example, where it is proposed the encapsulation of a kind of polycrystal chip semiconductor for DC-DC transducer incremental, has a lead frame with the wafer pad of ground connection; Be positioned at the vertical base source electrode N-passage MOSFET above wafer pad; And an anode-substrate Schottky diode, its anode is connected in the drain electrode of vertical MOSFET.Schottky diode wafer and vertical MOSFET wafer are encapsulated in above independent wafer pad in the mode of storehouse jointly, and Schottky diode wafer is positioned at above vertical MOSFET wafer, make the source inductance of vertical MOSFET minimum, and are convenient to heat radiation.But, because source electrode and grid are formed in above wafer usually, be difficult to be connected on gate pad, therefore will upside-down mounting MOSFET wafer be very difficult simply.
Many benefits are brought because bulk device (Bulk Device) resistance is low, therefore extremely bulk device is needed in semi-conductor industry, can also small size be kept while thermal resistance is low, and prepares the ability etc. of thin chip with the substrate thickness that power semiconductor is very little.
Figure 1A is shown in the profile of the bottom described in the United States Patent (USP) 7554154 being entitled as " bottom source LDMOSFET structure and method thereof "-source electrode laterally diffused MOS (BS-LDMOS) device of people's inventions such as the Hebert authorized on June 30th, 2009.By implanting very dark decanting zone 115, prepare bottom-source electrode device architecture.BSLDMOS device is positioned on P+ substrate 105, and P+ substrate 105 is as bottom source electrode.P-epitaxial loayer 110 is positioned at above substrate 105.Below the active cell district of device, with the decanting zone 115 that the doping of P+ Doped ions is very dark, be formed in the depths of epitaxial loayer, and extend laterally to the bottom of drain-drift region 125, to compensate some savings N-alloy in the transistor, thus the doped level of adjustment N-drift region 125, the while of making gate drain capacitor minimized, maintain very low drain-source resistance R.sub.dson.Dark decanting zone 115 also extends to bottom P+ substrate 105 downward vertically, upwards extends vertically up to body zone 150, and the end face below gate oxide 135 forms a passage.Decanting zone 115 is both as a combination passage, also the source-body joint imbedded as, for being connected to the P+ body contact region 155 being formed in adjacent top surface, as a top channel, covered by source metal 170-S, N+ doping source region 160 surrounds source metal 170-S.By the grid 140 of the cingens planform shape of gate spacers 165, covered by grid cover material 170-G, be deposited on above grid oxic horizon 135, grid oxic horizon 135 is formed on the end face between source area 160 and drain-drift region 125.Therefore, the passage formed by the body zone 150 below grid 140, grid 140 controls the electric current between source area 160 and drain-drift region 125, plays a lateral MOS device.Drain region 125 is deposited on below field oxide 130, is covered by bpsg layer 180, and passivation layer 185 also can be selected to cover.Through passivation layer 185 and bpsg layer 180, etching drain connector opening, makes top-side drain metal 199 contact drain region 125 by joint N+ doped region 190, reduces contact resistance.As shown in the figure, the oxide 130 and 135 of the planform shape below platform grid 140 can be formed by diverse ways.These methods comprise growth or deposition oxide, from channel region or utilize the LOCOS type of oxide deposition to etch.The grid 140 of planform shape has a longer grid length, and does not increase cell pitch carry out field plating above drain extension.Platform grid 140 is the flowing between the drain electrode of electric current below passage and gate oxide 135 and field oxide 130, provides necessary connection, reduces gate leakage capacitance.But, corresponding unit interval and this structure and method closely related.That is, because decanting zone 115 occupies too many space, what therefore obtained unit interval can be suitable is large.
Along with the appearance of straight-through substrate through vias (TSV) technology of original technology (such as shown in Figure 1B), nowadays bottom source power MOSFET device also can provide flip chip legal system standby, make its device end downward, by an independently conductive through hole, by its device end gate metal (bottom), redirect to its substrate terminal gate metal (top).Otherwise, substantially just do not have electric charge to flow to other parts of device architecture, and front end preparation process.Exemplarily, independently the structure of conductive through hole can be the metal charge being covered with oxide.Although have above-mentioned advantage, the independence of TSV, and preparation process relevant on the back side of thinned wafer, all still can bring unnecessary technologic loaded down with trivial details and cost.Therefore, still need to simplify device architecture and preparation technology further.
The application relates to following patent application:
U.S. Patent Application No. is 11/830951, and the patent being entitled as " the multi-wafer DC-DC with efficient encapsulation strengthens power converter " submitted on July 31st, 2007 by people such as Francois Hebert, hereinafter referred to as U. S. application 11/830951.
U.S. Patent Application No. is 12/749696, and the patent being entitled as " composite power semiconductor device at the true linerless end and method thereof " submitted on March 30th, 2010 by people such as Tao Feng, hereinafter referred to as U. S. application 12/749696.
Hereby quote above-mentioned patent content, as the reference for any and whole intention.
Summary of the invention
Propose with the exposed device termination electrode (SEDE) of substrate terminal.This semiconductor device has:
A Semiconductor substrate (SCS), have device end, device end opposite substrate terminal and be positioned at the semiconductor device district (SDR) of device end.
Multiple device termination electrode (DSE), is formed in above device end, and contacts with semiconductor device district, for the operation of semiconductor device.
At least one straight-through substrate trenches (TST), extends through Semiconductor substrate, touches device termination electrode, thus it is become the exposed device termination electrode in substrate terminal.
In order to encapsulated semiconductor device, conductive connecting (or being referred to as conductive internal wire) can be passed through, through the straight-through interconnected exposed device termination electrode in substrate terminal of substrate trenches.Conductive internal wire (Conductive interconnector) can be a bonding wire, engage intermediate plate or solder projection pad.
In a more typical embodiment, semiconductor device comprises a substrate terminal electrode (SSE) contacted with substrate terminal, and the substrate terminal passivation (SSPV) with window above a SSE.SSPV defines the exposed area of SSE, for smearing soldering tin material when wafer reprocessing encapsulates at this place.Semiconductor device can be a kind of vertical semiconductor devices (Vertical semiconductor device), and its principal current flow to bottom from top device, or vice versa.
In a preferred embodiment, semiconductor device comprises a device end passivation (DSPV), covers the device end of the exposed device termination electrode in substrate terminal.At least one exposed device termination electrode in substrate terminal corresponding, one in the device termination electrode non-exposed bracing frame extended with at the device termination electrode of substrate terminal, be deposited in (the exposed device termination electrode in substrate terminal) below to be separated by the exposed device termination electrode in substrate terminal of device end passivation and this, to give this exposed support on the device end-electrode structure of substrate terminal when wafer reprocessing encapsulates simultaneously.In addition, the bracing frame of this extension is incident upon the size in main semiconductor substrate plane, substantially encased the exposed projected dimension corresponding at the device termination electrode of substrate terminal, namely the bracing frame size be incident upon in main semiconductor substrate plane is more than or equal to the corresponding size be incident upon in main semiconductor substrate plane of device termination electrode haply.
In another preferred embodiment, straight-through substrate trenches is TSTW along the width of main semiconductor substrate plane, and the degree of depth perpendicular to main semiconductor substrate plane is TSTD, and preferably aspect ratio TSTW/TSTD is about 0.2 to 20.
In a more typical embodiment, this semiconductor device is a kind of bottom source metal oxide semiconductor field effect tube (MOSFET), has the substrate terminal drain electrode (SSDE) contacted with Semiconductor substrate, and correspondingly:
Semiconductor device district has a source area, a gate regions and a body zone.
Device termination electrode has:
The source electrode of a contact source area and body zone, and with the bracing frame extended.
The exposed device termination electrode in substrate terminal of a contact gate regions.
In the embodiment of an expansion, on its device end, this semiconductor device also comprises, by the bonded device end carrier (device end carrier) of insulation intermediary's knitting layer (ILBL).Wherein:
Semiconductor substrate has the thickness TSCS that a substrate is close to disappearance, and this thickness can be comparable with the thickness TSDR in semiconductor device district.
Device end carrier has patterned rear carrier metal, contact devices termination electrode, this device termination electrode is not the exposed device termination electrode in substrate terminal, and rear carrier metal is connected on front support metal gasket by a patterned front support metal gasket and multiple straight-through carrier conductive through hole respectively.
The thickness TDSC of device end carrier is enough large, sufficient structural rigidity can be provided for semiconductor device, the thickness TSCS that substrate is close to disappearance makes the device termination electrode of contact produce very low back resistance substrate, and straight-through carrier conductive through hole makes the device termination electrode of contact produce very low front face resistance.
Propose a kind of for the preparation of the method with the exposed device termination electrode (SEDE) of at least one substrate terminal, so that interconnected with external environment condition.The method comprises:
A) in the device end of Semiconductor substrate (SCS), a semiconductor device district (SDR) is prepared.
B) on device end, prepare multiple device termination electrode (DSE) and device end passivation (DSPV), and contact with semiconductor device district, for the operation of semiconductor device, device end passivation makes device termination electrode mutually insulated.
C) prepare at least one straight-through substrate trenches (TST), extend through Semiconductor substrate, touch prefabricated device termination electrode, thus it is become the exposed device termination electrode in substrate terminal.
In a more typical embodiment, the straight-through substrate trenches of preparation comprises:
On a semiconductor substrate, use and form the pattern of trench mask of band window, mask window is equivalent to the size of straight-through substrate trenches.
Orientation is etched through part Semiconductor substrate in mask window and semiconductor device district, and terminate in the interface of semiconductor device district-exposed device termination electrode in substrate terminal and the interface cut-off of semiconductor device district-device end passivation, thus make straight-through substrate trenches.
The trench mask of removing band window.
In an additional embodiment, at above-mentioned steps b) and c) between, also above device end passivation, extend a device termination electrode with horizontal expansion bracing frame, until it covers the device end surfaces of the exposed device termination electrode in substrate terminal under device end passivation substantially.This device termination electrode is not described predetermined device termination electrode.Can by the mask of utilization band window, plated metal above the device end surfaces of selected device termination electrode, until form the bracing frame extended.
In another exemplary embodiments, proposing a kind of is the method for the bottom source MOSFET of TMOSFET for the preparation of minimal thickness.This bottom source MOSFET has the exposed device end gate electrode (the device end gate electrode that substrate terminal is exposed) of a substrate terminal, is interconnected to external environment condition when being convenient to technique encapsulation after wafer.The method comprises:
A) prepare the interim Semiconductor substrate (ISS) that a thickness is TISS > TMOSFET, TISS is enough large, can be compatible with traditional semiconductor wafer process.
B) above interim semiconductor, traditional semiconductor wafer process is utilized, continuous production MOSFET element district (FETDR) adds device end source electrode (DSSE), device end gate electrode (DSGE) and the device end passivation (DSPV) above device region, wherein:
Device end gate electrode is positioned near device end source electrode.
Device end passivation makes device end gate electrode and device end source electrode mutually insulated.
Device end passivation also covers the device end surfaces of device end gate electrode.
C) at the back side of interim semiconductor, be in the Semiconductor substrate of TSCS ~ TMOSFET at desired thickness, thinning interim semiconductor, and a substrate terminal drain electrode (SSDE) is prepared on it.
D) a straight-through substrate trenches (TST) is prepared, add device region extend through substrate terminal drain electrode, Semiconductor substrate, and expose the substrate terminal of device end gate electrode, thus it is become the exposed device end gate electrode of the exposed device end gate electrode substrate terminal of substrate terminal.
In a more typical embodiment, the straight-through substrate trenches of preparation comprises:
Above the device end of the device in preparation, connect an interim support substrates, and overturn.
Above substrate terminal drain electrode, use and form the pattern that is with the trench mask of window, mask window is equivalent to the size of straight-through substrate trenches, etches away the part substrate terminal drain electrode in mask window, but in substrate terminal drain electrode-Semiconductor substrate interface place cut-off.
Orientation is etched through part Semiconductor substrate in mask window and device region, but in device region-and the interface of device end gate electrode and the interface cut-off of device region-device end passivation, thus make straight-through substrate trenches.
The trench mask of removing band window.
Remove interim support substrates.
Use and formed one band window trench mask pattern before, following improvement can be done for foregoing, the substrate terminal passivation (SSPV) of a band window can be prepared above substrate terminal drain electrode, the exposed area of definition substrate terminal drain electrode, so that after the wafer of bottom source MOSFET during technique encapsulation, coating soldering tin material.
In another embodiment, a kind of semiconductor device with following structure is proposed:
First conductive pad on semiconductor wafer first limit;
A groove below the first conductive pad, wherein eliminates semi-conducting material, and wherein the first pad is out exposed from Second Edge, and Second Edge is on the opposite side of semiconductor wafer; And
A conductive connecting, is connected to conductive pad from Second Edge.
In a more typical embodiment, conductive connecting is bonding wire, conductive clip, conductive strips or solder projection pad.In another more typical embodiment, conductive connecting is arranged in groove at least partly, and first end is connected on the first pad, outside the groove of the second end on the Second Edge of semiconductor wafer.
In another more typical embodiment, semiconductor device can be a vertical field-effect pipe (FET), and the first pad is a gate pad.Position residing for gate pad can be surrounded by the active area of vertical field-effect pipe or part surrounds.Semiconductor device also comprises a supporting construction above gate pad.Gate pad can be surrounded completely by the active area of device, and supporting construction can be a source electrode extended.Conductive connecting can be a bonding wire, conductive clip, conductive strips or solder projection pad.
For those skilled in the art, these aspects of the present invention and multiple embodiment thereof are explained in the remainder of this explanation.
Accompanying drawing explanation
In order to various embodiment of the present invention is more intactly described, can refer to accompanying drawing.But these accompanying drawings are only used as to explain and illustrate, not as the limitation of the scope of the invention.
Figure 1A represents the profile of bottom source laterally diffused MOS (BS-LDMOS) device of the with groove of the original technology of Section 1 described in United States Patent (USP) 7554154;
Figure 1B represents the profile of the Section 2 original technology bottom source power MOSFET device utilizing straight-through substrate through vias (TSV);
Fig. 1 C represents the profile of the bottom drain power MOSFET device of original technology of the grid with multiple with groove;
Fig. 2 A represents the profile of the bottom source power MOSFET device of the grid with multiple with groove described in one embodiment of the present of invention;
Fig. 2 B represents the profile of the bottom source power MOSFET device of the grid with multiple with groove described in an embodiment of the present invention;
Fig. 3 A represents the profile of the bottom source power MOSFET device described in the first embodiment of the present invention;
Fig. 3 B represents and utilizes bonding wire, technique encapsulation after the wafer of device shown in Fig. 3 A;
Fig. 3 C represents a kind of semiconductor packages containing bottom source power MOSFET device of the present invention;
Fig. 4 A to Fig. 4 H represents the preparation technology preparing device shown in Fig. 3 A;
Fig. 5 represents the profile of the second embodiment of bottom source power MOSFET device of the present invention;
Fig. 6 represents the profile of the 3rd embodiment of the bottom source power MOSFET device with extra device end carrier of the present invention; And
Fig. 7 represents the profile of another embodiment of bottom source power MOSFET device of the present invention.
Embodiment
Following explanation and accompanying drawing is addressed only for illustration of one or more existing preferred embodiment of the present invention on herein, and some typical selectable unit and/or embodiment.Illustrate and accompanying drawing for explaining explanation, in itself, do not limit to the present invention.Therefore, those skilled in the art will easily grasp various change, change and correction.These are changed, change and revise and also should think and belong to scope of the present invention.
Fig. 1 C represents the profile of the bottom drain power MOSFET device 1 of original technology, this device is with an an active part 1a and gate interconnection part 1b, and they are all positioned at above the Semiconductor substrate (SCS) 21 with bottom drain metal level 22.Active part 1a is in the semiconductor device district (SDR) 3 of Semiconductor substrate 21, and have the gate regions 24 of multiple spaced source electrode-body zone 23 and with groove, they are all positioned at above Semiconductor substrate 21.In this example, Semiconductor substrate 21 can be made up of a lightly doped extension drift layer 21b above heavily doped contact layer 21a.Multiple source electrode-body zone 23 is connected with a patterned close source electrode (Intimate source electrode) 25 and parallel connection.Similar with it, although in order to avoid producing unnecessary obscuring to those skilled in the art, joint detail herein does not describe in detail, but the gate regions 24 of active part 1a with groove (X-Y plane) in third dimension, by the gate runner district 24a of a with groove, is parallel on the patterned gate electrode 26 of the gate interconnection part 1b be positioned at below device end passivation (DSPV) 29.Device end insulant 28a, 28b are positioned at above Semiconductor substrate 21, make patterned gate electrode 26 and patterned close source electrode 25 insulate with semiconductor device structure below respectively, except those need the place of contact.
Fig. 2 A represents the profile of bottom source power MOSFET 31 of the present invention, and wherein active part 31a and gate interconnection part 31b is positioned in the Semiconductor substrate (SCS) 21 with drain metal layer 22.Although do not describe in detail at this, after the process of front, bottom source power MOSFET 31 can upside-down mounting.Should be clear and definite, the active part 31a of bottom source power MOSFET 31 is except having extra patterned source electrode 55 above patterned close source electrode 25 and with it except electrical connection, and other are all similar with the active part 1a of bottom drain power MOSFET device 1.In gate interconnection part 31b, straight-through substrate trenches (TST) 57 extends through Semiconductor substrate 21, touch the device end gate electrode (SEDGE) 56 that substrate terminal is exposed, with the device end gate electrode portion 56a that exposed substrate terminal is exposed.Straight-through substrate trenches 57 has a straight-through substrate trenches size 57a, and its geometric properties is the degree of depth is TSTD, and width is TSTW.
The device end gate electrode 56 that corresponding substrate end is exposed, patterned source electrode 55 has also extended to gate interconnection part 31b, the bracing frame 55a also extended with one, below, the device end gate electrode 56 exposed with the substrate terminal with device end passivation 29 separates storehouse simultaneously.In addition, the projected dimension (X-Y plane) of the bracing frame 55a of extension must surround the corresponding projected dimension of the exposed device end gate electrode of substrate terminal 56 substantially.Therefore, after the wafer of bottom source power MOSFET 31 during technique encapsulation, the bracing frame 55a of extension can from the exposed device end gate electrode 56 of structural support substrate terminal.
Fig. 2 B represents the profile of an embodiment of the present invention, and the gate interconnection part 31b wherein containing straight-through substrate trenches 57 is between active part 31a.Therefore, source electrode 55 has a bracing frame 55a extended, and can cover completely and support straight-through substrate trenches 57.
Fig. 3 A represents the profile of the first embodiment of bottom source power MOSFET 35 of the present invention.According to the explanation of Fig. 2 A, for a person skilled in the art, for convenience of explanation, the detailed description of the device end (such as source electrode-body zone, gate trench etc.) for bottom source power MOSFET device is saved hereinafter.It should be noted that Fig. 3 A is the flipchart of Fig. 2 A.As special case, Semiconductor substrate 21 can be made up of silicon, and with an a heavily doped contact layer 21a and lightly doped drift layer 21b, lightly doped drift layer 21b is made by epitaxial growth above heavily doped contact layer 21a.Drain metal layer 22 can be made up of titanium-nickel-Yin (TiNiAg).Patterned close source electrode 25 and the exposed device end gate electrode 56 of substrate terminal can be made up of Solder for Al-Cu Joint Welding (AICu).Device end passivation 29 can be made up of oxide and/or polyimides.Patterned source electrode 55 can be made up of copper (Cu).Some relevant geometric parameter scopes are: thickness ~ 1 of device end passivation 29 is micron to 10 microns; Thickness ~ 5 of the bracing frame 55a extended are micron to 20 microns.The bracing frame 55a extended can (in vertical direction) device end gate electrode 56 that completely Substrate Overlay end is exposed, even extends to above the exposed device end gate electrode 56 of substrate terminal, to provide extra support.
Fig. 3 B represents that bottom source power MOSFET 35 saves technique encapsulation after the wafer of active part.In this example, by a conductive connecting 33 (such as bonding wire), through straight-through substrate trenches 57, be connected on the exposed device end gate electrode 56 of substrate terminal.For a person skilled in the art, as long as TSTD and TSTW can adapt to conductive connecting and relevant encapsulation tool thereof, just conductive connecting 33 can be replaced with fish plate or solder projection pad (Solder bump).In this, TSTW/TSTD preferably aspect ratio be about 0.2 to 20.As a more typical embodiment, the scope of TSTW can from 100 microns to 500 microns, and the scope of TSTD can from 25 microns to 500 microns.Be also noted that, if need straight-through substrate trenches 57 to be lined with insulating material, with (see U. S. application 12/749696) during the exposed surface that passivated semiconductor substrate 21 is different, at this moment, as a part for technique encapsulation after wafer, can with surrounding bonding wire 33 and simultaneously straight-through substrate trenches 57 filled by the shaping batch mixing of passivated semiconductor substrate 21.
Exemplarily, Fig. 3 C represents the semiconductor packages 50 containing bottom source MOS EFT 35 and lead frame 32.Bottom source power MOSFET 35 is arranged on leadframe part 32b, and leadframe part 32b is used as lower bolster.Therefore, close source electrode 25 is connected on leadframe part 32b, (such as by installing patterned source electrode 55 on part 32b).By the conductive connecting 33a be applicable to arbitrarily, such as bonding wire, conductive strips, conductive clip etc., through straight-through substrate trenches 57, can be connected to gate electrode (SEDGE 56) on leadframe part 32c.By conductive connecting 36 (also can comprise bonding wire, conductive strips, conductive clip etc.), drain metal layer 22 also can be connected on leadframe part 32a, if necessary, other semiconductor wafer (not indicating in figure) also can encapsulate with bottom source power MOSFET 35 together.After this, shaping batch mixing 37 (its profile as shown in phantom in FIG.) hermetically sealed 50.Shaping batch mixing 37 also can be filled in straight-through substrate trenches 57.
Fig. 4 A to Fig. 4 H represents the preparation process of the bottom source power MOSFET device shown in Fig. 3 A.In Figure 4 A, with traditional semiconductor wafer process, above interim Semiconductor substrate (ISS) 70, prepare MOSFET element district (FETDR) 71 together with patterned close source electrode 25, patterned gate electrode 26 and device end passivation 29, the thickness TISS of interim Semiconductor substrate (ISS) 70 is enough large, can be compatible with traditional semiconductor wafer process.As a typical case, the scope of TISS can between 600-800 micron.Patterned close source electrode 25 is positioned near patterned gate electrode 26, and patterned gate electrode 26 is insulated by device end passivation 29 and it, and device end passivation 29 also cover the device end surfaces of patterned gate electrode 26.
In figure 4b, above device end passivation 29, extend patterned close source electrode 25 together, until it covers the device end surfaces of the patterned gate electrode 26 below device end passivation 29 substantially with the bracing frame 55a extended.Its realization by above the device end surfaces of patterned close source electrode 25, can be with mask (omitting, the to simplify view) plated metal of window herein, until form the bracing frame 55a extended by one.As a typical case, thick copper (Cu) electroplating technology of band mask can be used.In addition, chemico-mechanical polishing (CMP) can be carried out after thick Cu plating, make the end face of plating smooth, then form nickel-Jin (Ni-Au) layer or thin soldering-tin layer, to prevent copper oxidized.
In figure 4 c, the back side of interim Semiconductor substrate (ISS) 70 is thinned to the Semiconductor substrate 21 that desired thickness is TSCS downwards.Then, in substrate terminal (i.e. the opposite of the device end) top of Semiconductor substrate 21, a substrate terminal drain metal layer 22 is formed.Such as, by backgrind technique, the thickness of TSCS can reduce between 50 microns-300 microns, and prepares drain metal layer 22 with titanium-nickel-Yin (Ti-Ni-Ag).
Fig. 4 D to Fig. 4 G represents the straight-through substrate trenches 57 of preparation, extends through drain metal layer 22, and Semiconductor substrate 21 contains MOSFET element district (FETDR) 71 and exposes the exposed device end gate electrode 56 of substrate terminal.In fig. 4d, in preparation device device end on directed connect an interim support substrates 72, and make its substrate (drain electrode) end upwards.Such as, the support substrates 72 that the preparations such as the process wafer of glass, silicon or broad sense are interim can be used.
In Fig. 4 E, above drain metal layer 22, use one be with the trench mask 74 of window and form pattern, mask window 75 is equivalent to the prefabricated straight-through substrate trenches size 57a (X-Y plane) of straight-through substrate trenches 57.Such as, the trench mask 74 being with window can be a kind of photoresist.
In Fig. 4 F, etch away the part drain metal layer 22 in mask window 75, etching terminates in the interface place of drain metal layer 22-Semiconductor substrate 21.
In Fig. 4 G, part Semiconductor substrate 21 below directed etch mask window 75 and device region 71, etching terminates in the interface of the exposed device end gate electrode 56 of device region 71-substrate terminal and the interface place of device region 71-device end passivation 29, thus makes straight-through substrate trenches 57.Such as, some now can be utilized with the plasma etching of the vertical furrow cell wall of tapering.In a more typical embodiment, the scope of TSTD is 100 microns to 300 microns, and the scope of typical TSTW is 150 microns to 200 microns, is minimumly about 100 microns.
In Fig. 4 H, peel off the trench mask 74 of band window, then unsticking remove interim support substrates 72, make the bottom source power MOSFET with desired thickness TMOSFET.
Fig. 5 represents the profile of another embodiment of bottom source power MOSFET part 33b of the present invention.Now, above drain metal layer 22, add the substrate terminal passivation (SSPV) 27 of a band window, thus the drain metal district 80 that restriction one is exposed, for when wafer reprocessing encapsulates, smear and limit soldering tin material and flow into herein.Such as, the preparation SSPV27 such as oxide, nitride or polyimides can be used.In preparation process, can before drain metal layer 22 (Fig. 4 E) top use the trench mask 74 of band window and form pattern, preparation SSPV 27.
Fig. 6 represents the profile of another embodiment of the bottom source power MOSFET part 34b that with the addition of device end carrier (DSC) 40.Bottom source power MOSFET part 34b is except the bracing frame 55a without the source electrode 55 extended and extension, and with the addition of on its device end outside the device end carrier (DSC) 40 (such as by insulation intervening binder layer (ILBL) 60 carrier material 40a combined or be bonded on device end) be made up of carrier material 40a, other are all substantially identical with the device shown in Fig. 3 A.More details please refer to U. S. application 12/749,696, one skilled in the art should appreciate that following characteristics:
Semiconductor substrate 21 should be close to the thickness TSCS of disappearance with substrate, namely the substrate portions contact layer 21a that Semiconductor substrate 21 comprises can reduce and be similar to disappearance on thickness, due to the structural rigidity of device end carrier 40, thickness TSCS can be comparable with the thickness TSDR in semiconductor device district.
Device end carrier (DSC) 40 has multiple patterned rear carrier metal 41a, 41b, 41c, contact patterned source electrode 25, patterned front support metal gasket 42a and multiple straight-through carrier conductive through hole 43a, 43b, 43c respectively patterned rear carrier metallization 41a, 41b, 41c to be connected on patterned front support metalized pads 42a.
The thickness TDSC of device end carrier 40 is enough large, sufficient structural rigidity can be provided for semiconductor device, the thickness TSCS that substrate is close to disappearance produces a very low back resistance substrate, and the patterned close source electrode 25 of straight-through carrier conductive through hole 43a, 43b, 43c to contact produces very low front face resistance.
Another unnoticeably feature be, due to when the wafer-process of bottom source power MOSFET part 34b, device end passivation 29 does not need to cover the exposed device end gate electrode 56 of substrate terminal, the wafer scale probing test that the exposed device end gate electrode 56 of the substrate terminal that therefore top is exposed is relevant before simplifying Mount Device end carrier 40.In some more typical embodiment, the scope of TDCS is about 100 microns to 400 microns.The scope of TSCS is about 5 microns to 100 microns, and in view of the rigidity of device end carrier 40, there is not the danger punctured, TSCS also can be less than 50 microns.
Fig. 7 representation class is similar to the profile of another embodiment of the bottom source power MOSFET of Fig. 6, but wherein device end carrier 40 is replaced by shaping batch mixing 90, shaping batch mixing 90 surrounds solder projection pad 95, by source electrode 55a, is connected on close source electrode 25.Also can select, the device end gate electrode 56 that substrate terminal is exposed forms gate electrode 55b, as the byproduct preparing source electrode 55a, but not connect from source electrode 55a or from solder projection pad 95.The source electrode 55a added can be conducive to being connected to smoothly on the soldering tin material of solder projection pad 95.
Above-mentioned explanation comprises many specific details, and these details only explain explanation as providing the existing preferred embodiment of the present invention, and should not regard the limitation to the scope of the invention as.Such as, add the power MOSFET device with trench-gate, the principle of bottom source power MOSFET of the present invention is also applicable to other type of device such as LDMOSFET (LDMOS) and vertical double-diffused MOS FET (VDMOS).Again such as, principle of the present invention is also applicable to structure and the preparation of micro electronic mechanical system (MEMS).More than illustrate and accompanying drawing reference concrete structure, give various typical embodiment.Should be apparent for those skilled in the art, the present invention also can be used for other concrete form, and above-mentioned various embodiment, through easily amendment, just can be suitable for other embody rule.In view of this patent document, scope of the present invention should not limited by above-mentioned concrete exemplary embodiments, and should be limited by following claims.Any in the content and full scope of equivalents thereof of claims and all revising, should belong in true intention of the present invention and scope.
Claims (18)
1., with a semiconductor device for the exposed device termination electrode (SEDE) in substrate terminal, it is characterized in that, this semiconductor device comprises:
A Semiconductor substrate (SCS), have device end, device end opposite substrate terminal and be positioned at the semiconductor device district (SDR) of device end;
Multiple device termination electrode (DSE), is formed in above device end, and contacts with semiconductor device district, for the operation of semiconductor device; And
At least one straight-through substrate trenches (TST), extend through Semiconductor substrate, touch device termination electrode, thus described device termination electrode is become the exposed device termination electrode in substrate terminal, thus can conductive connecting be passed through, through the straight-through interconnected exposed device termination electrode in substrate terminal of substrate trenches;
Device end passivation (DSPV) of at least one exposed device termination electrode in substrate terminal of correspondence, and
Except described at least one is exposed except the device termination electrode of substrate terminal, the bracing frame that a default electrode extends with one is also had in described device termination electrode, described device end passivation is deposited in the described default base part of the bracing frame with this extension, by described device end passivation, the bracing frame of this extension is separated with at least one the described exposed device termination electrode in substrate terminal under described device end passivation simultaneously, to give at least one described exposed support on the device end-electrode structure of substrate terminal when wafer reprocessing encapsulates.
2. the semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal according to claim 1, it is characterized in that, this semiconductor device is a vertical semiconductor devices.
3. the semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal according to claim 1, is characterized in that, also comprises a substrate terminal electrode (SSE) contacted with substrate terminal.
4. the semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal according to claim 1, is characterized in that, conductive connecting is a bonding wire, engages intermediate plate, conductive strips or solder projection pad.
5. the semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal according to claim 1, it is characterized in that, the bracing frame size of this extension is incident upon the size in main semiconductor substrate plane, has encased the described exposed corresponding projected dimension of device termination electrode in substrate terminal.
6. the semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal according to claim 1, it is characterized in that, straight-through substrate trenches is TSTW along the width of main semiconductor substrate plane, the degree of depth perpendicular to main semiconductor substrate plane is TSTD, aspect ratio TSTW/TSTD is 0.2 to 20.
7. the semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal according to claim 6, it is characterized in that, TSTW is 100 microns to 500 microns, and TSTD is 25 microns to 500 microns.
8. the semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal according to claim 1, is characterized in that, also comprise a substrate terminal drain electrode contacted with Semiconductor substrate, and correspondingly:
Semiconductor device district has a source area, a gate regions and a body zone; And
Device termination electrode has:
The source electrode of a contact source area and body zone, and with the bracing frame extended; And
The exposed device termination electrode in substrate terminal of a contact gate regions,
Thus make this semiconductor device be a kind of bottom source metal oxide semiconductor field effect tube (MOSFET).
9. the semiconductor device with the exposed device termination electrode (SEDE) in substrate terminal according to claim 1, it is characterized in that, also be included in its device end, by the bonded device end carrier (DSC) of insulation intermediary's knitting layer (ILBL), wherein:
Semiconductor substrate has one and is thinned to required thickness TSCS;
Device end carrier has patterned rear carrier metal, contact a device termination electrode, this device termination electrode is not an exposed device termination electrode in substrate terminal, and rear carrier metal is connected on front support metal gasket by a patterned front support metal gasket and multiple straight-through carrier conductive through hole respectively; And
The thickness TDSC of device end carrier is large enough to device end carrier can provide sufficient structural rigidity for semiconductor device, the reduced thickness of described Semiconductor substrate makes the back resistance substrate of the device termination electrode of contact reduce to described thickness TSCS, the front face resistance reduction that described multiple straight-through carrier conductive through hole produces for making the device termination electrode of contact.
10., for the preparation of the method with at least one exposed device termination electrode (SEDE) in substrate terminal, so that interconnected with external environment condition, it is characterized in that, the method comprises:
A) prepare a Semiconductor substrate (SCS), and prepare a semiconductor device district (SDR) in its device end;
B) on device end, prepare multiple device termination electrode (DSE), and contact with semiconductor device district, for the operation of semiconductor device; And
A bracing frame with horizontal expansion is provided to extend a first device termination electrode, until cover the device end surfaces of at least one exposed the second device termination electrode in substrate terminal, this the first device termination electrode is not the second described device termination electrode, the bracing frame and exposed between the second device termination electrode of substrate terminal that device end passivation (DSPV) is extending is provided, and they are separated;
C) prepare at least one straight-through substrate trenches (TST), extend through Semiconductor substrate, touch the second device termination electrode, thus the second described device termination electrode is become at least one described exposed second device termination electrode in substrate terminal.
11. methods according to claim 10, is characterized in that, the straight-through substrate trenches of preparation comprises:
Orientation is etched through part Semiconductor substrate in predetermined mask window and semiconductor device district, and terminates in the interface of semiconductor device district-exposed the second device termination electrode in substrate terminal, thus makes straight-through substrate trenches.
12. methods according to claim 10, is characterized in that, the first device termination electrode described in extension comprises the mask by being with window, plated metal above the device end surfaces of the first described device termination electrode, until form the bracing frame extended.
13. 1 kinds of semiconductor device, is characterized in that having:
A semiconductor wafer be made up of semi-conducting material, and there is the first limit and Second Edge;
A conduction first be positioned on semiconductor wafer first limit pads;
One is padded the groove of below in conduction first, wherein removes semi-conducting material, and by described groove, the first pad is out exposed from the Second Edge of semiconductor wafer; And
The connecting line of a conduction, from described Second Edge through described groove, is connected to described conduction first and pads;
The supporting construction also having default electrode to extend above the first pad with one in the device termination electrode on the first limit, supports exposed the first pad at Second Edge, and supporting construction is separated by exposed to pad at first of Second Edge of device end passivation and this.
14. semiconductor device according to claim 13, is characterized in that, the connecting line of conduction is bonding wire, conductive clip or conductive strips or solder projection pad.
15. semiconductor device according to claim 13, is characterized in that, conductive connecting is positioned at described groove at least partly, and conductive connecting first end is connected on the first pad, outside the groove that conductive connecting second end is described on semiconductor wafer Second Edge.
16. semiconductor device according to claim 13, is characterized in that, described semiconductor device is vertical field-effect pipe (FET), and the first described pad is gate pad.
17. semiconductor device according to claim 16, is characterized in that, the position at gate pad place is surrounded by the active area of FET at least partly.
18. semiconductor device according to claim 16, is characterized in that, conductive connecting is bonding wire, conductive clip, conductive strips or solder projection pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110170350.9A CN102832244B (en) | 2011-06-13 | 2011-06-13 | With the semiconductor device and preparation method thereof of the exposed device termination electrode of substrate terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110170350.9A CN102832244B (en) | 2011-06-13 | 2011-06-13 | With the semiconductor device and preparation method thereof of the exposed device termination electrode of substrate terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102832244A CN102832244A (en) | 2012-12-19 |
| CN102832244B true CN102832244B (en) | 2015-08-26 |
Family
ID=47335302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110170350.9A Active CN102832244B (en) | 2011-06-13 | 2011-06-13 | With the semiconductor device and preparation method thereof of the exposed device termination electrode of substrate terminal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102832244B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113394291A (en) * | 2021-04-29 | 2021-09-14 | 电子科技大学 | Lateral power semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6657255B2 (en) * | 2001-10-30 | 2003-12-02 | General Semiconductor, Inc. | Trench DMOS device with improved drain contact |
| US7352036B2 (en) * | 2004-08-03 | 2008-04-01 | Fairchild Semiconductor Corporation | Semiconductor power device having a top-side drain using a sinker trench |
| US7393770B2 (en) * | 2005-05-19 | 2008-07-01 | Micron Technology, Inc. | Backside method for fabricating semiconductor components with conductive interconnects |
| US7307348B2 (en) * | 2005-12-07 | 2007-12-11 | Micron Technology, Inc. | Semiconductor components having through wire interconnects (TWI) |
| US7705440B2 (en) * | 2007-09-07 | 2010-04-27 | Freescale Semiconductor, Inc. | Substrate having through-wafer vias and method of forming |
| US8294208B2 (en) * | 2008-03-04 | 2012-10-23 | International Rectifier Corporation | Semiconductor device having a gate contact on one surface electrically connected to a gate bus on an opposing surface |
-
2011
- 2011-06-13 CN CN201110170350.9A patent/CN102832244B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102832244A (en) | 2012-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9355953B2 (en) | Vertical semiconductor MOSFET device with double substrate-side multiple electrode connections and encapsulation | |
| TWI401800B (en) | True csp power mosfet based on bottom-source mosfet | |
| US9991192B2 (en) | Semiconductor package | |
| US8294208B2 (en) | Semiconductor device having a gate contact on one surface electrically connected to a gate bus on an opposing surface | |
| US7687902B2 (en) | Semiconductor device and a manufacturing method of the same | |
| US6653740B2 (en) | Vertical conduction flip-chip device with bump contacts on single surface | |
| US7569920B2 (en) | Electronic component having at least one vertical semiconductor power transistor | |
| CN102376765B (en) | Semiconductor device and method for manufacturing the same | |
| US6066877A (en) | Vertical power MOSFET having thick metal layer to reduce distributed resistance | |
| TWI395277B (en) | Wafer level chip scale packaging | |
| US20060169976A1 (en) | Semiconductor device | |
| CN101884097B (en) | Structure and method of forming a topside contact to a backside terminal of a semiconductor device | |
| CN102569297B (en) | Monolithic IGBT and diode structure for quasi-resonant converters and method | |
| EP3951883A1 (en) | Bidirectional power device and manufacturing method therefor | |
| US8193583B2 (en) | Monolithic output stage with vertical high-side PMOS and vertical low-side NMOS interconnected using buried metal, structure and method | |
| WO2019147556A1 (en) | Integrated trench capacitor formed in an epitaxial layer | |
| US20120199911A1 (en) | Vertical discrete device with drain and gate electrodes on the same surface and method for making the same | |
| US10770576B2 (en) | Power MOSFET device and manufacturing process thereof | |
| EP2210265B1 (en) | Semiconductor structure and method of manufacture | |
| CN102832244B (en) | With the semiconductor device and preparation method thereof of the exposed device termination electrode of substrate terminal | |
| US20220254703A1 (en) | Semiconductor Device | |
| KR20110084106A (en) | Monolithic output stage with vertical high-side pmos and vertical low-side nmos interconnected using buried metal, structure and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200518 Address after: Ontario, Canada Patentee after: World semiconductor International Limited Partnership Address before: 475 oakmead Avenue, Sunnyvale, California 94085, USA Patentee before: Alpha and Omega Semiconductor Inc. |