CN102832153A - Method for determining machine generating granule defects in ion injection process section - Google Patents
Method for determining machine generating granule defects in ion injection process section Download PDFInfo
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- CN102832153A CN102832153A CN201210335261XA CN201210335261A CN102832153A CN 102832153 A CN102832153 A CN 102832153A CN 201210335261X A CN201210335261X A CN 201210335261XA CN 201210335261 A CN201210335261 A CN 201210335261A CN 102832153 A CN102832153 A CN 102832153A
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Abstract
The invention provides a method for determining a machine generating granule defects in an ion injection process section. The method comprises the following steps of providing a semiconductor substrate going through the ion injection process section; acquiring a granule defect view of the surface of the semiconductor substrate; defining a granule defect ratio corresponding to each of mask layers, wherein the granule defect ratio is the ratio of the number of the granule defects in the positions not covered by the mask layers of the semiconductor substrate to the number of the granule defects in the positions covered by the mask layers of the semiconductor substrate; and determining the mask layer with the highest granule defect ratio, and the machine adopted in the ion injection process step corresponding to the mask layer is the machine generating the granule defects. The method can determine the ion injection process step causing the granule defects in the ion injection process section and the ion injection machine adopted in the step.
Description
Technical field
The present invention relates to technical field of semiconductors, especially judge the method for the board that the ion of the particle that forms on the Semiconductor substrate injects.
Background technology
The method that forms knot or other impurity that mix on the surface of Semiconductor substrate generally realizes through thermal diffusion or ion implantation technology.Before ion implantation technology, need on Semiconductor substrate, form mask layer, said mask layer is generally patterned photoresist layer, and said mask layer is used to define the zone of ion implantation technology.Usually, the Semiconductor substrate of said mask layer region is covered by photoresist layer, is the zone that ion injects and do not covered Semiconductor substrate by mask layer.
In the manufacture process of integrated circuit, need repeatedly on different ion implantor platforms, to carry out different ions and inject, above-mentioned repeatedly ion injects and is called as an ion implantation process section.Usually after an ion implantation process section is accomplished, can carry out grain defect to Semiconductor substrate and detect, so that this ion implantation process section is judged at the number of the grain defect of semiconductor substrate surface formation.
Because an ion implantation process section can be carried out a plurality of different ion implantation steps on a plurality of different ion implantor platforms; When the grain defect that detects semiconductor substrate surface exceeds standard; Can't judge accurately which ion implantation technology step causes in this ion implantation process section, can't judge that also which ion implantor platform causes.Therefore, need a kind of method, can when the ion implantation process section is carried out the grain defect judgement, confirm to cause the ion implantation technology step and the ion implantor platform of grain defect.
Summary of the invention
The problem that the present invention solves provides a kind of method that produces the board of grain defect in the ion implantation process section of judging, has confirmed in the ion implantation process section, to cause the ion implantation technology step of grain defect and the ion implantor platform of employing.
In order to address the above problem, the present invention provides a kind of method that produces the board of grain defect in the ion implantation process section of judging, comprising:
Semiconductor substrate through the ion implantation process section is provided, and said ion implantation process section comprises a plurality of ion implantation steps, and each ion implantation step adopts corresponding mask layer to carry out;
Obtain the grain defect figure of said semiconductor substrate surface;
Confirm the grain defect ratio that each mask layer is corresponding, said grain defect ratio is: the number of the grain defect of the position that is not covered by this mask layer of this Semiconductor substrate and this Semiconductor substrate by the ratio of the number of the grain defect of the position of this mask layer covering;
Confirm grain defect than maximum mask layer, the board that the ion implantation technology step that this mask layer is corresponding is adopted is the board that produces grain defect.
Alternatively, said grain defect is desired to make money or profit and with the defective scanner acquisition is scanned on the surface of Semiconductor substrate.
Alternatively, said Semiconductor substrate is not to utilize the position of figure correspondence in grain defect figure of this mask layer to carry out the binding analysis acquisition by the number that is covered the grain defect of position by this mask layer of the number of the grain defect of the position of this mask layer covering and this Semiconductor substrate.
Alternatively, said mask layer is a photoresist layer.
Compared with prior art, the present invention has the following advantages:
Method provided by the invention is through figure and grain defect figure binding analysis with mask layer; Confirm the grain defect ratio that each mask layer is corresponding; The ion implantor platform that the corresponding ion implantation step of peaked mask layer is adopted in this grain defect ratio is the board that produces grain defect, does not need so successively to scan, and also need each ion implantor platform not detected; Not only raise the efficiency, and save manpower.
Description of drawings
Fig. 1 is the grain defect distribution schematic diagram that is coated with on the Semiconductor substrate of photoresist layer;
Fig. 2 is the distribution schematic diagram of the grain defect on the Semiconductor substrate after the described photoresist layer of Fig. 1 is removed;
Fig. 3 is the method flow sketch map that produces the board of grain defect in the judgement ion implantation process section of one embodiment of the present of invention.
Embodiment
Prior art can't be judged the board of the generation grain defect in the ion implantation process section quickly and accurately.Because in an ion implantation process section, need a plurality of a plurality of ion implantation steps that on different ion implantor platforms, carry out usually.If each ion implantation step is scanned, the meeting labor intensive is checked each ion implantor platform, also can take great amount of manpower.
Please combine Fig. 1, Fig. 1 is the grain defect distribution schematic diagram that is coated with on the Semiconductor substrate of photoresist layer.When the ion implantation technology process, mask layer 20 covers on the Semiconductor substrate 10, grain defect drop on Semiconductor substrate 10 not by mask layer 20 covered surfaces and mask layer 20 tops.Please combine Fig. 2, after ion implantation technology was accomplished, with removing from Semiconductor substrate 10 in the mask layer 20 (Fig. 1), the grain defect on the mask layer 20 also was removed thereupon.Therefore; The inventor considers; Through the figure of mask layer and the grain defect figure of Semiconductor substrate are carried out binding analysis; Obtain the ratio of number of number and the grain defect that do not covered by mask layer of grain defect of the position of the Semiconductor substrate that mask layer covers, above-mentioned ratio is big more, explains that the ion implantor platform of the ion implantation technology that this mask layer is corresponding is many more at the grain defect that the surface of Semiconductor substrate produces.
The present invention provides a kind of method of judging in the ion implantation process section board that produces grain defect, please refer to Fig. 3, is the schematic flow sheet of the said method of one embodiment of the invention, and said method comprises:
Step S1 provides the Semiconductor substrate through the ion implantation process section, and said ion implantation process section comprises a plurality of ion implantation steps, and each ion implantation step adopts corresponding mask layer to carry out;
Step S2 obtains the grain defect figure of said semiconductor substrate surface;
Step S3; Confirm the grain defect ratio that each mask layer is corresponding, said grain defect ratio is: the number of the grain defect of the position that is not covered by this mask layer of this Semiconductor substrate and this Semiconductor substrate by the ratio of the number of the grain defect of the position of this mask layer covering;
Step S4 confirms grain defect than maximum mask layer, and the board that the ion implantation technology step that this mask layer is corresponding is adopted is the board that produces grain defect.
Below in conjunction with concrete embodiment technical scheme of the present invention is carried out detailed explanation.
At first; Semiconductor substrate is provided, and said Semiconductor substrate is through an ion implanted region section, promptly a plurality of ion implantation technology steps; Utilize on the defective scanning machine grain defect to analyze, obtain the grain defect figure of said semiconductor substrate surface semiconductor substrate surface.As an embodiment, said a plurality of ion implantation technology steps are 3, utilize the mask layer of 3 different patterns to carry out, and the material of said mask layer is a photoresist.
In the present embodiment, the total number of the grain defect among the said grain defect figure is 200.
Then; Confirm the grain defect ratio that each mask layer is corresponding, said grain defect ratio is: the number of the grain defect of the position that is not covered by this mask layer of this Semiconductor substrate and this Semiconductor substrate by the ratio of the number of the grain defect of the position of this mask layer covering.As an embodiment; The acquisition methods of said grain defect ratio is: the figure of this mask layer and the figure of grain defect figure are superposeed; Obtain to be positioned among this grain defect figure the number of the grain defect beyond first mask layer, this number is in the Semiconductor substrate not by the number of the grain defect of the position of this mask layer covering; The number of the defect particles of the position that also obtains simultaneously to be covered by first mask layer among this grain defect figure, this number is the number of the defect particles that is covered by this mask layer in the said Semiconductor substrate.The figure of said mask layer and the stack of the figure of grain defect utilize the defective scanner to carry out.As a real embodiment, said mask layer has three, and the grain defect ratio of first mask layer is that the grain defect ratio of 130/70, the second mask layer is that the grain defect ratio of 124/76, the three mask layer is 185/15.
Then, confirm grain defect than maximum mask layer, the board that the ion implantation technology step that this mask layer is corresponding is adopted is the board that produces grain defect.As an embodiment, grain defect is the 3rd mask layer than maximum mask layer, and then the 3rd the corresponding board that the ion implantation technology step adopted of mask layer is the board that produces grain defect.
To sum up; Method provided by the invention is confirmed the grain defect ratio that each mask layer is corresponding through figure and grain defect figure binding analysis with mask layer, and the ion implantor platform that the corresponding ion implantation step of peaked mask layer is adopted in this grain defect ratio is the board that produces grain defect; Do not need so successively to scan; Need not detect yet, not only raise the efficiency, and save manpower each ion implantor platform.
Therefore, above-mentioned preferred embodiment is merely explanation technical conceive of the present invention and characteristics, and its purpose is to let the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (4)
1. judge the method that produces the board of grain defect in the ion implantation process section for one kind, it is characterized in that, comprising:
Semiconductor substrate through the ion implantation process section is provided, and said ion implantation process section comprises a plurality of ion implantation steps, and each ion implantation step adopts corresponding mask layer to carry out;
Obtain the grain defect figure of said semiconductor substrate surface;
Confirm the grain defect ratio that each mask layer is corresponding, said grain defect ratio is: the number of the grain defect of the position that is not covered by this mask layer of this Semiconductor substrate and this Semiconductor substrate by the ratio of the number of the grain defect of the position of this mask layer covering;
Confirm grain defect than maximum mask layer, the board that the ion implantation technology step that this mask layer is corresponding is adopted is the board that produces grain defect.
2. the method for claim 1 is characterized in that, said grain defect is desired to make money or profit and with the defective scanner acquisition scanned on the surface of Semiconductor substrate.
3. the method for claim 1; It is characterized in that said Semiconductor substrate is not to utilize the position of figure correspondence in grain defect figure of this mask layer to carry out the binding analysis acquisition by the number that is covered the grain defect of position by this mask layer of the number of the grain defect of the position of this mask layer covering and this Semiconductor substrate.
4. like the described method of arbitrary claim in the claim 1 ~ 3, it is characterized in that said mask layer is a photoresist layer.
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| CN201210335261XA CN102832153A (en) | 2012-09-11 | 2012-09-11 | Method for determining machine generating granule defects in ion injection process section |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839849A (en) * | 2014-02-21 | 2014-06-04 | 上海华力微电子有限公司 | Method for judging failed machine in ion implantation section |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614420A (en) * | 1996-05-16 | 1997-03-25 | Taiwan Semicondoctor Manufacturing Company Ltd. | Method of preventing mask tone error |
| CN1770418A (en) * | 2004-11-02 | 2006-05-10 | 力晶半导体股份有限公司 | Defect detection method |
| CN101996908A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method and device for detecting wafer |
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- 2012-09-11 CN CN201210335261XA patent/CN102832153A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614420A (en) * | 1996-05-16 | 1997-03-25 | Taiwan Semicondoctor Manufacturing Company Ltd. | Method of preventing mask tone error |
| CN1770418A (en) * | 2004-11-02 | 2006-05-10 | 力晶半导体股份有限公司 | Defect detection method |
| CN101996908A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method and device for detecting wafer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839849A (en) * | 2014-02-21 | 2014-06-04 | 上海华力微电子有限公司 | Method for judging failed machine in ion implantation section |
| CN103839849B (en) * | 2014-02-21 | 2016-06-29 | 上海华力微电子有限公司 | The decision method of ion implanting section problem board |
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Application publication date: 20121219 |